#include typedef struct { uint32_t en : 1; // 0 Enable uint32_t abort : 1; // 1 Abort request uint32_t dmaen : 1; // 2 DMA enable uint32_t tcen : 1; // 3 Timeout counter enable uint32_t reserve0 : 2; // 4 Reserve uint32_t dqm : 1; // 6 Dual-quad mode uint32_t fsel : 1; // 7 FLASH memory selection uint32_t fthres : 5; // 8 IFO threshold level uint32_t reserve1 : 3; // 13 Reserve uint32_t teie : 1; // 16 Transfer error interrupt enable uint32_t tcie : 1; // 17 Transfer complete interrupt enable uint32_t ftie : 1; // 18 FIFO threshold interrupt enable uint32_t smie : 1; // 19 Status match interrupt enable uint32_t toie : 1; // 20 TimeOut interrupt enable uint32_t reserve2 : 1; // 21 Reserve uint32_t apms : 1; // 22 Automatic poll mode stop uint32_t pmm : 1; // 23 Polling match mode uint32_t reserve3 : 4; // 24 Reserve uint32_t fmode : 2; // 28 Functional mode uint32_t reserve4 : 2; // 30 Reserve } reg_octospi_cr_t; typedef struct { uint32_t ckmode : 1; // 0 Mode 0 / mode 3 uint32_t frck : 1; // 1 Free running clock uint32_t reserve0 : 1; // 2 Reserve uint32_t dlybyp : 1; // 3 Delay block bypass uint32_t reserve1 : 4; // 4 Reserve uint32_t csht : 6; // 8 Chip-select high time uint32_t reserve2 : 2; // 14 Reserve uint32_t devsize : 5; // 16 Device size uint32_t reserve3 : 3; // 21 Reserve uint32_t mtyp : 3; // 24 Memory type uint32_t reserve4 : 5; // 27 Reserve } reg_octospi_dcr1_t; typedef struct { uint32_t prescaler : 8; // 0 Clock prescaler uint32_t reserve0 : 8; // 8 Reserve uint32_t wrapsize : 3; // 16 Wrap size uint32_t reserve1 : 13; // 19 Reserve } reg_octospi_dcr2_t; typedef struct { uint32_t maxtran : 8; // 0 Maximum transfer uint32_t reserve0 : 8; // 8 Reserve uint32_t csbound : 5; // 16 CS boundary uint32_t reserve1 : 11; // 21 Reserve } reg_octospi_dcr3_t; typedef struct { uint32_t refresh : 32; // 0 Refresh rate } reg_octospi_dcr4_t; typedef struct { uint32_t tef : 1; // 0 Transfer error flag uint32_t tcf : 1; // 1 transfer complete flag uint32_t ftf : 1; // 2 FIFO threshold flag uint32_t smf : 1; // 3 status match flag uint32_t tof : 1; // 4 timeout flag uint32_t busy : 1; // 5 BUSY uint32_t reserve0 : 2; // 6 Reserve uint32_t flevel : 6; // 8 FIFO level uint32_t reserve1 : 18; // 14 Reserve } reg_octospi_sr_t; typedef struct { uint32_t ctef : 1; // 0 Clear Transfer error flag uint32_t ctcf : 1; // 1 Clear transfer complete flag uint32_t reserve0 : 1; // 2 Reserve uint32_t csmf : 1; // 3 Clear status match flag uint32_t ctof : 1; // 4 Clear timeout flag uint32_t reserve1 : 27; // 5 Reserve } reg_octospi_fcr_t; typedef struct { uint32_t dl : 32; // 0 Data length } reg_octospi_dlr_t; typedef struct { uint32_t address : 32; // 0 ADDRESS } reg_octospi_ar_t; typedef struct { uint32_t data : 32; // 0 DATA } reg_octospi_dr_t; typedef struct { uint32_t mask : 32; // 0 Status MASK } reg_octospi_psmkr_t; typedef struct { uint32_t match : 32; // 0 Status match } reg_octospi_psmar_t; typedef struct { uint32_t interval : 16; // 0 polling interval uint32_t reserve0 : 16; // 16 Reserve } reg_octospi_pir_t; typedef struct { uint32_t imode : 3; // 0 Instruction mode uint32_t idtr : 1; // 3 Instruction double transfer rate uint32_t isize : 2; // 4 Instruction size uint32_t reserve0 : 2; // 6 Reserve uint32_t admode : 3; // 8 Address mode uint32_t addtr : 1; // 11 Address double transfer rate uint32_t adsize : 2; // 12 Address size uint32_t reserve1 : 2; // 14 Reserve uint32_t abmode : 3; // 16 Alternate byte mode uint32_t abdtr : 1; // 19 Alternate bytes double transfer rate uint32_t absize : 2; // 20 Alternate bytes size uint32_t reserve2 : 2; // 22 Reserve uint32_t dmode : 3; // 24 Data mode uint32_t ddtr : 1; // 27 Alternate bytes double transfer rate uint32_t reserve3 : 1; // 28 Reserve uint32_t dqse : 1; // 29 DQS enable uint32_t reserve4 : 1; // 30 Reserve uint32_t sioo : 1; // 31 Send instruction only once mode } reg_octospi_ccr_t; typedef struct { uint32_t dcyc : 5; // 0 Number of dummy cycles uint32_t reserve0 : 23; // 5 Reserve uint32_t dhqc : 1; // 28 Delay hold quarter cycle uint32_t reserve1 : 1; // 29 Reserve uint32_t sshift : 1; // 30 Sample shift uint32_t reserve2 : 1; // 31 Reserve } reg_octospi_tcr_t; typedef struct { uint32_t instruction: 32; // 0 INSTRUCTION } reg_octospi_ir_t; typedef struct { uint32_t alternate : 32; // 0 Alternate bytes } reg_octospi_abr_t; typedef struct { uint32_t timeout : 16; // 0 Timeout period uint32_t reserve0 : 16; // 16 Reserve } reg_octospi_lptr_t; typedef struct { uint32_t imode : 3; // 0 Instruction mode uint32_t idtr : 1; // 3 Instruction double transfer rate uint32_t isize : 2; // 4 Instruction size uint32_t reserve0 : 2; // 6 Reserve uint32_t admode : 3; // 8 Address mode uint32_t addtr : 1; // 11 Address double transfer rate uint32_t adsize : 2; // 12 Address size uint32_t reserve1 : 2; // 14 Reserve uint32_t abmode : 3; // 16 Alternate byte mode uint32_t abdtr : 1; // 19 Alternate bytes double transfer rate uint32_t absize : 2; // 20 Alternate bytes size uint32_t reserve2 : 2; // 22 Reserve uint32_t dmode : 3; // 24 Data mode uint32_t ddtr : 1; // 27 alternate bytes double transfer rate uint32_t reserve3 : 1; // 28 Reserve uint32_t dqse : 1; // 29 DQS enable uint32_t reserve4 : 2; // 30 Reserve } reg_octospi_wpccr_t; typedef struct { uint32_t dcyc : 5; // 0 Number of dummy cycles uint32_t reserve0 : 23; // 5 Reserve uint32_t dhqc : 1; // 28 Delay hold quarter cycle uint32_t reserve1 : 1; // 29 Reserve uint32_t sshift : 1; // 30 Sample shift uint32_t reserve2 : 1; // 31 Reserve } reg_octospi_wptcr_t; typedef struct { uint32_t instruction: 32; // 0 INSTRUCTION } reg_octospi_wpir_t; typedef struct { uint32_t alternate : 32; // 0 Alternate bytes } reg_octospi_wpabr_t; typedef struct { uint32_t imode : 3; // 0 Instruction mode uint32_t idtr : 1; // 3 Instruction double transfer rate uint32_t isize : 2; // 4 Instruction size uint32_t reserve0 : 2; // 6 Reserve uint32_t admode : 3; // 8 Address mode uint32_t addtr : 1; // 11 Address double transfer rate uint32_t adsize : 2; // 12 Address size uint32_t reserve1 : 2; // 14 Reserve uint32_t abmode : 3; // 16 Alternate byte mode uint32_t abdtr : 1; // 19 Alternate bytes double transfer rate uint32_t absize : 2; // 20 Alternate bytes size uint32_t reserve2 : 2; // 22 Reserve uint32_t dmode : 3; // 24 Data mode uint32_t ddtr : 1; // 27 alternate bytes double transfer rate uint32_t reserve3 : 1; // 28 Reserve uint32_t dqse : 1; // 29 DQS enable uint32_t reserve4 : 2; // 30 Reserve } reg_octospi_wccr_t; typedef struct { uint32_t dcyc : 5; // 0 Number of dummy cycles uint32_t reserve0 : 27; // 5 Reserve } reg_octospi_wtcr_t; typedef struct { uint32_t instruction: 32; // 0 INSTRUCTION } reg_octospi_wir_t; typedef struct { uint32_t alternate : 32; // 0 ALTERNATE } reg_octospi_wabr_t; typedef struct { uint32_t lm : 1; // 0 Latency mode uint32_t wzl : 1; // 1 Write zero latency uint32_t reserve0 : 6; // 2 Reserve uint32_t tacc : 8; // 8 Access time uint32_t trwr : 8; // 16 Read write recovery time uint32_t reserve1 : 8; // 24 Reserve } reg_octospi_hlcr_t; typedef struct { volatile reg_octospi_cr_t cr; volatile uint32_t reserve0[1]; volatile reg_octospi_dcr1_t dcr1; volatile reg_octospi_dcr2_t dcr2; volatile reg_octospi_dcr3_t dcr3; volatile reg_octospi_dcr4_t dcr4; volatile uint32_t reserve1[2]; volatile reg_octospi_sr_t sr; volatile reg_octospi_fcr_t fcr; volatile uint32_t reserve2[6]; volatile reg_octospi_dlr_t dlr; volatile uint32_t reserve3[1]; volatile reg_octospi_ar_t ar; volatile uint32_t reserve4[1]; volatile reg_octospi_dr_t dr; volatile uint32_t reserve5[11]; volatile reg_octospi_psmkr_t psmkr; volatile uint32_t reserve6[1]; volatile reg_octospi_psmar_t psmar; volatile uint32_t reserve7[1]; volatile reg_octospi_pir_t pir; volatile uint32_t reserve8[27]; volatile reg_octospi_ccr_t ccr; volatile uint32_t reserve9[1]; volatile reg_octospi_tcr_t tcr; volatile uint32_t reserve10[1]; volatile reg_octospi_ir_t ir; volatile uint32_t reserve11[3]; volatile reg_octospi_abr_t abr; volatile uint32_t reserve12[3]; volatile reg_octospi_lptr_t lptr; volatile uint32_t reserve13[3]; volatile reg_octospi_wpccr_t wpccr; volatile uint32_t reserve14[1]; volatile reg_octospi_wptcr_t wptcr; volatile uint32_t reserve15[1]; volatile reg_octospi_wpir_t wpir; volatile uint32_t reserve16[3]; volatile reg_octospi_wpabr_t wpabr; volatile uint32_t reserve17[7]; volatile reg_octospi_wccr_t wccr; volatile uint32_t reserve18[1]; volatile reg_octospi_wtcr_t wtcr; volatile uint32_t reserve19[1]; volatile reg_octospi_wir_t wir; volatile uint32_t reserve20[3]; volatile reg_octospi_wabr_t wabr; volatile uint32_t reserve21[23]; volatile reg_octospi_hlcr_t hlcr; } reg_octospi_t;