#include typedef struct { uint32_t pe : 1; // 0 Peripheral enable uint32_t txie : 1; // 1 TX Interrupt enable uint32_t rxie : 1; // 2 RX Interrupt enable uint32_t addrie : 1; // 3 Address match interrupt enable (slave only) uint32_t nackie : 1; // 4 Not acknowledge received interrupt enable uint32_t stopie : 1; // 5 STOP detection Interrupt enable uint32_t tcie : 1; // 6 Transfer Complete interrupt enable uint32_t errie : 1; // 7 Error interrupts enable uint32_t dnf : 4; // 8 Digital noise filter uint32_t anfoff : 1; // 12 Analog noise filter OFF uint32_t reserve0 : 1; // 13 Reserve uint32_t txdmaen : 1; // 14 DMA transmission requests enable uint32_t rxdmaen : 1; // 15 DMA reception requests enable uint32_t sbc : 1; // 16 Slave byte control uint32_t nostretch : 1; // 17 Clock stretching disable uint32_t wupen : 1; // 18 Wakeup from STOP enable uint32_t gcen : 1; // 19 General call enable uint32_t smbhen : 1; // 20 SMBus Host address enable uint32_t smbden : 1; // 21 SMBus Device Default address enable uint32_t alerten : 1; // 22 SMBUS alert enable uint32_t pecen : 1; // 23 PEC enable uint32_t fmp : 1; // 24 Fast-mode Plus 20 mA drive enable uint32_t reserve1 : 5; // 25 Reserve uint32_t addraclr : 1; // 30 Address match flag (ADDR) automatic clear uint32_t stopfaclr : 1; // 31 STOP detection flag (STOPF) automatic clear } reg_i2c_cr1_t; typedef struct { uint32_t sadd : 10; // 0 Slave address bit (master mode) uint32_t rd_wrn : 1; // 10 Transfer direction (master mode) uint32_t add10 : 1; // 11 10-bit addressing mode (master mode) uint32_t head10r : 1; // 12 10-bit address header only read direction (master receiver mode) uint32_t start : 1; // 13 Start generation uint32_t stop : 1; // 14 Stop generation (master mode) uint32_t nack : 1; // 15 NACK generation (slave mode) uint32_t nbytes : 8; // 16 Number of bytes uint32_t reload : 1; // 24 NBYTES reload mode uint32_t autoend : 1; // 25 Automatic end mode (master mode) uint32_t pecbyte : 1; // 26 Packet error checking byte uint32_t reserve0 : 5; // 27 Reserve } reg_i2c_cr2_t; typedef struct { uint32_t oa1 : 10; // 0 Interface address uint32_t oa1mode : 1; // 10 Own Address 1 10-bit mode uint32_t reserve0 : 4; // 11 Reserve uint32_t oa1en : 1; // 15 Own Address 1 enable uint32_t reserve1 : 16; // 16 Reserve } reg_i2c_oar1_t; typedef struct { uint32_t reserve0 : 1; // 0 Reserve uint32_t oa2 : 7; // 1 Interface address uint32_t oa2msk : 3; // 8 Own Address 2 masks uint32_t reserve1 : 4; // 11 Reserve uint32_t oa2en : 1; // 15 Own Address 2 enable uint32_t reserve2 : 16; // 16 Reserve } reg_i2c_oar2_t; typedef struct { uint32_t scll : 8; // 0 SCL low period (master mode) uint32_t sclh : 8; // 8 SCL high period (master mode) uint32_t sdadel : 4; // 16 Data hold time uint32_t scldel : 4; // 20 Data setup time uint32_t reserve0 : 4; // 24 Reserve uint32_t presc : 4; // 28 Timing prescaler } reg_i2c_timingr_t; typedef struct { uint32_t timeouta : 12; // 0 Bus timeout A uint32_t tidle : 1; // 12 Idle clock timeout detection uint32_t reserve0 : 2; // 13 Reserve uint32_t timouten : 1; // 15 Clock timeout enable uint32_t timeoutb : 12; // 16 Bus timeout B uint32_t reserve1 : 3; // 28 Reserve uint32_t texten : 1; // 31 Extended clock timeout enable } reg_i2c_timeoutr_t; typedef struct { uint32_t txe : 1; // 0 Transmit data register empty (transmitters) uint32_t txis : 1; // 1 Transmit interrupt status (transmitters) uint32_t rxne : 1; // 2 Receive data register not empty (receivers) uint32_t addr : 1; // 3 Address matched (slave mode) uint32_t nackf : 1; // 4 Not acknowledge received flag uint32_t stopf : 1; // 5 Stop detection flag uint32_t tc : 1; // 6 Transfer Complete (master mode) uint32_t tcr : 1; // 7 Transfer Complete Reload uint32_t berr : 1; // 8 Bus error uint32_t arlo : 1; // 9 Arbitration lost uint32_t ovr : 1; // 10 Overrun/Underrun (slave mode) uint32_t pecerr : 1; // 11 PEC Error in reception uint32_t timeout : 1; // 12 Timeout or t_low detection flag uint32_t alert : 1; // 13 SMBus alert uint32_t reserve0 : 1; // 14 Reserve uint32_t busy : 1; // 15 Bus busy uint32_t dir : 1; // 16 Transfer direction (Slave mode) uint32_t addcode : 7; // 17 Address match code (Slave mode) uint32_t reserve1 : 8; // 24 Reserve } reg_i2c_isr_t; typedef struct { uint32_t reserve0 : 3; // 0 Reserve uint32_t addrcf : 1; // 3 Address Matched flag clear uint32_t nackcf : 1; // 4 Not Acknowledge flag clear uint32_t stopcf : 1; // 5 Stop detection flag clear uint32_t reserve1 : 2; // 6 Reserve uint32_t berrcf : 1; // 8 Bus error flag clear uint32_t arlocf : 1; // 9 Arbitration lost flag clear uint32_t ovrcf : 1; // 10 Overrun/Underrun flag clear uint32_t peccf : 1; // 11 PEC Error flag clear uint32_t timoutcf : 1; // 12 Timeout detection flag clear uint32_t alertcf : 1; // 13 Alert flag clear uint32_t reserve2 : 18; // 14 Reserve } reg_i2c_icr_t; typedef struct { uint32_t pec : 8; // 0 Packet error checking register uint32_t reserve0 : 24; // 8 Reserve } reg_i2c_pecr_t; typedef struct { uint32_t rxdata : 8; // 0 8-bit receive data uint32_t reserve0 : 24; // 8 Reserve } reg_i2c_rxdr_t; typedef struct { uint32_t txdata : 8; // 0 8-bit transmit data uint32_t reserve0 : 24; // 8 Reserve } reg_i2c_txdr_t; typedef struct { uint32_t reserve0 : 6; // 0 Reserve uint32_t tcdmaen : 1; // 6 DMA request enable on Transfer Complete event uint32_t tcrdmaen : 1; // 7 DMA request enable on Transfer Complete Reload event uint32_t reserve1 : 8; // 8 Reserve uint32_t trigsel : 4; // 16 Trigger selection uint32_t trigpol : 1; // 20 Trigger polarity uint32_t trigen : 1; // 21 Trigger enable uint32_t reserve2 : 10; // 22 Reserve } reg_i2c_autocr_t; typedef struct { volatile reg_i2c_cr1_t cr1; volatile reg_i2c_cr2_t cr2; volatile reg_i2c_oar1_t oar1; volatile reg_i2c_oar2_t oar2; volatile reg_i2c_timingr_t timingr; volatile reg_i2c_timeoutr_t timeoutr; volatile reg_i2c_isr_t isr; volatile reg_i2c_icr_t icr; volatile reg_i2c_pecr_t pecr; volatile reg_i2c_rxdr_t rxdr; volatile reg_i2c_txdr_t txdr; volatile reg_i2c_autocr_t autocr; } reg_i2c_t;