#include typedef struct { uint32_t trgo : 1; // 0 Trigger output control Set by software and reset by uint32_t reserve0 : 31; // 1 Reserve } reg_adf_gcr_t; typedef struct { uint32_t ckgden : 1; // 0 CKGEN dividers enable uint32_t cck0en : 1; // 1 ADF_CCK0 clock enable uint32_t cck1en : 1; // 2 ADF_CCK1 clock enable uint32_t reserve0 : 1; // 3 Reserve uint32_t ckgmod : 1; // 4 Clock generator mode uint32_t cck0dir : 1; // 5 ADF_CCK0 direction uint32_t cck1dir : 1; // 6 ADF_CCK1 direction uint32_t reserve1 : 1; // 7 Reserve uint32_t trgsens : 1; // 8 CKGEN trigger sensitivity selection uint32_t reserve2 : 3; // 9 Reserve uint32_t trgsrc : 4; // 12 Digital filter trigger signal selection uint32_t cckdiv : 4; // 16 Divider to control the ADF_CCK clock uint32_t reserve3 : 4; // 20 Reserve uint32_t procdiv : 7; // 24 Divider to control the serial interface clock uint32_t ckgactive : 1; // 31 Clock generator active flag } reg_adf_ckgcr_t; typedef struct { uint32_t sitfen : 1; // 0 SITFEN uint32_t scksrc : 2; // 1 SCKSRC uint32_t reserve0 : 1; // 3 Reserve uint32_t sitfmod : 2; // 4 SITFMOD uint32_t reserve1 : 2; // 6 Reserve uint32_t sth : 5; // 8 STH uint32_t reserve2 : 18; // 13 Reserve uint32_t sitfactive: 1; // 31 SITFACTIVE } reg_adf_sitf0cr_t; typedef struct { uint32_t bssel : 5; // 0 Bitstream selection uint32_t reserve0 : 26; // 5 Reserve uint32_t bsmxactive: 1; // 31 BSMX active flag } reg_adf_bsmx0cr_t; typedef struct { uint32_t dflten : 1; // 0 DFLT0 enable uint32_t dmaen : 1; // 1 DMA requests enable uint32_t fth : 1; // 2 RXFIFO threshold selection uint32_t reserve0 : 1; // 3 Reserve uint32_t acqmod : 3; // 4 DFLT0 trigger mode uint32_t reserve1 : 5; // 7 Reserve uint32_t trgsrc : 4; // 12 DFLT0 trigger signal selection uint32_t reserve2 : 4; // 16 Reserve uint32_t nbdis : 8; // 20 Number of samples to be discarded uint32_t reserve3 : 2; // 28 Reserve uint32_t dfltrun : 1; // 30 DFLT0 run status flag uint32_t dfltactive: 1; // 31 DFLT0 active flag } reg_adf_dflt0cr_t; typedef struct { uint32_t datsrc : 2; // 0 Source data for the digital filter uint32_t reserve0 : 2; // 2 Reserve uint32_t cicmod : 3; // 4 Select the CIC order uint32_t reserve1 : 1; // 7 Reserve uint32_t mcicd : 9; // 8 CIC decimation ratio selection uint32_t reserve2 : 3; // 17 Reserve uint32_t scale : 6; // 20 Scaling factor selection uint32_t reserve3 : 6; // 26 Reserve } reg_adf_dflt0cicr_t; typedef struct { uint32_t rsfltbyp : 1; // 0 Reshaper filter bypass uint32_t reserve0 : 3; // 1 Reserve uint32_t rsfltd : 1; // 4 Reshaper filter decimation ratio uint32_t reserve1 : 2; // 5 Reserve uint32_t hpfbyp : 1; // 7 High-pass filter bypass uint32_t hpfc : 2; // 8 High-pass filter cut-off frequency uint32_t reserve2 : 22; // 10 Reserve } reg_adf_dflt0rsfr_t; typedef struct { uint32_t skpdly : 7; // 0 Delay to apply to a bitstream uint32_t reserve0 : 24; // 7 Reserve uint32_t skpbf : 1; // 31 Skip busy flag } reg_adf_dly0cr_t; typedef struct { uint32_t fthie : 1; // 0 RXFIFO threshold interrupt enable uint32_t dovrie : 1; // 1 Data overflow interrupt enable uint32_t reserve0 : 7; // 2 Reserve uint32_t satie : 1; // 9 Saturation detection interrupt enable uint32_t ckabie : 1; // 10 Clock absence detection interrupt enable uint32_t rfovrie : 1; // 11 Reshape filter overrun interrupt enable uint32_t sddetie : 1; // 12 Sound activity detection interrupt enable uint32_t sdlvlie : 1; // 13 SAD sound-level value ready enable uint32_t reserve1 : 18; // 14 Reserve } reg_adf_dflt0ier_t; typedef struct { uint32_t fthf : 1; // 0 RXFIFO threshold flag uint32_t dovrf : 1; // 1 Data overflow flag uint32_t reserve0 : 1; // 2 Reserve uint32_t rxnef : 1; // 3 RXFIFO not empty flag uint32_t reserve1 : 5; // 4 Reserve uint32_t satf : 1; // 9 Saturation detection flag uint32_t ckabf : 1; // 10 Clock absence detection flag uint32_t rfovrf : 1; // 11 Reshape filter overrun detection flag uint32_t sddetf : 1; // 12 Sound activity detection flag uint32_t sdlvlf : 1; // 13 Sound level value ready flag uint32_t reserve2 : 18; // 14 Reserve } reg_adf_dflt0isr_t; typedef struct { uint32_t saden : 1; // 0 Sound activity detector enable uint32_t datcap : 2; // 1 Data capture mode uint32_t detcfg : 1; // 3 Sound trigger event configuration uint32_t sadst : 2; // 4 SAD state uint32_t reserve0 : 1; // 6 Reserve uint32_t hysten : 1; // 7 Hysteresis enable uint32_t frsize : 3; // 8 Frame size uint32_t reserve1 : 1; // 11 Reserve uint32_t sadmod : 2; // 12 SAD working mode uint32_t reserve2 : 17; // 14 Reserve uint32_t sadactive : 1; // 31 SAD Active flag } reg_adf_sadcr_t; typedef struct { uint32_t snthr : 4; // 0 SNTHR uint32_t anslp : 3; // 4 ANSLP uint32_t reserve0 : 1; // 7 Reserve uint32_t lfrnb : 3; // 8 LFRNB uint32_t reserve1 : 1; // 11 Reserve uint32_t hgovr : 3; // 12 Hangover time window uint32_t reserve2 : 1; // 15 Reserve uint32_t anmin : 13; // 16 ANMIN uint32_t reserve3 : 3; // 29 Reserve } reg_adf_sadcfgr_t; typedef struct { uint32_t sdlvl : 15; // 0 SDLVL uint32_t reserve0 : 17; // 15 Reserve } reg_adf_sadsdlvr_t; typedef struct { uint32_t anlvl : 15; // 0 ANLVL uint32_t reserve0 : 17; // 15 Reserve } reg_adf_sadanlvr_t; typedef struct { uint32_t reserve0 : 8; // 0 Reserve uint32_t dr : 24; // 8 DR } reg_adf_dflt0dr_t; typedef struct { volatile reg_adf_gcr_t gcr; volatile reg_adf_ckgcr_t ckgcr; volatile uint32_t reserve0[30]; volatile reg_adf_sitf0cr_t sitf0cr; volatile reg_adf_bsmx0cr_t bsmx0cr; volatile reg_adf_dflt0cr_t dflt0cr; volatile reg_adf_dflt0cicr_t dflt0cicr; volatile reg_adf_dflt0rsfr_t dflt0rsfr; volatile uint32_t reserve1[4]; volatile reg_adf_dly0cr_t dly0cr; volatile uint32_t reserve2[1]; volatile reg_adf_dflt0ier_t dflt0ier; volatile reg_adf_dflt0isr_t dflt0isr; volatile uint32_t reserve3[1]; volatile reg_adf_sadcr_t sadcr; volatile reg_adf_sadcfgr_t sadcfgr; volatile reg_adf_sadsdlvr_t sadsdlvr; volatile reg_adf_sadanlvr_t sadanlvr; volatile uint32_t reserve4[10]; volatile reg_adf_dflt0dr_t dflt0dr; } reg_adf_t;