#ifndef REG_DCMI_H
#define REG_DCMI_H

#include <stm32u5xx.h>


typedef struct {
    uint32_t capture: 1; // capture enable
    uint32_t cm: 1;      // capture mode
    uint32_t crop: 1;    // crop enable
    uint32_t jpeg: 1;    // jpeg enable
    uint32_t ess: 1;     // embedded synchronization select
    uint32_t pckpol: 1;  // pixel clock polarity
    uint32_t hspol: 1;   // horizontal synchronization polarity
    uint32_t vspol: 1;   // vertical synchronization polarity
    uint32_t fcrc: 2;    // frame capture rate control
    uint32_t edm: 2;     // extended data mode
    uint32_t resv: 2;    // reserved
    uint32_t enable: 1;  // DCMI enable
    uint32_t resv2: 1;
    uint32_t bsm: 2;     // byte select mode
    uint32_t oebs: 1;    // odd/even byte select
    uint32_t lsm: 1;     // line select mode
    uint32_t oels: 1;    // odd/even line select
    uint32_t resv3: 11;
} reg_dcmi_cr_t;

typedef struct {
    uint32_t hsync: 1; // horizontal synchronization
    uint32_t vsync: 1; // vertical synchronization
    uint32_t fne: 1;   // frame end
    uint32_t resv: 29;
} reg_dcmi_sr_t;

typedef struct {
    uint32_t frame_ris: 1; // frame capture complete raw interrupt status
    uint32_t ovr_ris: 1;   // overrun raw interrupt status
    uint32_t err_ris: 1;   // synchronization error raw interrupt status
    uint32_t vsync_ris: 1; // vsync raw interrupt status
    uint32_t line_ris: 1;  // line raw interrupt status
    uint32_t resv: 27;
} reg_dcmi_ris_t; // raw interrupt status register

typedef struct {
    uint32_t frame_ie: 1; // frame capture complete interrupt enable
    uint32_t ovr_ie: 1;   // overrun interrupt enable
    uint32_t err_ie: 1;   // synchronization error interrupt enable
    uint32_t vsync_ie: 1; // vsync interrupt enable
    uint32_t line_ie: 1;  // line interrupt enable
    uint32_t resv: 27;
} reg_dcmi_ier_t; // interrupt enable register

typedef struct {
    uint32_t frame_mis: 1; // frame capture complete masked interrupt status
    uint32_t ovr_mis: 1;   // overrun masked interrupt status
    uint32_t err_mis: 1;   // synchronization error masked interrupt status
    uint32_t vsync_mis: 1; // vsync masked interrupt status
    uint32_t line_mis: 1;  // line masked interrupt status
    uint32_t resv: 27;
} reg_dcmi_misr_t;  // masked interrupt status register

// icr
typedef struct {
    uint32_t frame_isc: 1; // frame capture complete interrupt status clear
    uint32_t ovr_isc: 1;   // overrun interrupt status clear
    uint32_t err_isc: 1;   // synchronization error interrupt status clear
    uint32_t vsync_isc: 1; // vsync interrupt status clear
    uint32_t line_isc: 1;  // line interrupt status clear
    uint32_t resv: 27;
} reg_dcmi_icr_t; // interrupt clear register

typedef struct {
    uint32_t byte0: 8;
    uint32_t byte1: 8;
    uint32_t byte2: 8;
    uint32_t byte3: 8;
} reg_dcmi_dr_t; // data register

typedef struct {
    reg_dcmi_cr_t cr;
    reg_dcmi_sr_t sr;
    reg_dcmi_ris_t risr;
    reg_dcmi_ier_t ier;
    reg_dcmi_misr_t misr;
    reg_dcmi_icr_t icr;
    uint32_t escr;
    uint32_t esur;
    uint32_t cwstrtr;
    uint32_t cwsizer;
    reg_dcmi_dr_t dr;
} reg_dcmi_s;

#endif