#include <stdint.h>

typedef struct {
    uint32_t  syscfgsec : 1;  // 0	 SYSCFG clock control security
    uint32_t  classbsec : 1;  // 1	 CLASSBSEC
    uint32_t  reserve0  : 1; // 2    Reserve
    uint32_t  fpusec    : 1;  // 3	 FPUSEC
    uint32_t  reserve1  : 28; // 4    Reserve
} reg_syscfg_seccfgr_t;

typedef struct {
    uint32_t  reserve0  : 8; // 0    Reserve
    uint32_t  boosten   : 1;  // 8	 I/O analog switch voltage booster enable
    uint32_t  anaswvdd  : 1;  // 9	 GPIO analog switch control voltage selection
    uint32_t  reserve1  : 6; // 10   Reserve
    uint32_t  pb6_fmp   : 1;  // 16	 PB6_FMP
    uint32_t  pb7_fmp   : 1;  // 17	 PB7_FMP
    uint32_t  pb8_fmp   : 1;  // 18	 PB8_FMP
    uint32_t  pb9_fmp   : 1;  // 19	 PB9_FMP
    uint32_t  reserve2  : 12; // 20   Reserve
} reg_syscfg_cfgr1_t;

typedef struct {
    uint32_t  fpu_ie    : 6;  // 0	 Floating point unit interrupts enable bits
    uint32_t  reserve0  : 26; // 6    Reserve
} reg_syscfg_fpuimr_t;

typedef struct {
    uint32_t  locknsvtor: 1;  // 0	 VTOR_NS register lock
    uint32_t  locknsmpu : 1;  // 1	 Non-secure MPU registers lock
    uint32_t  reserve0  : 30; // 2    Reserve
} reg_syscfg_cnslckr_t;

typedef struct {
    uint32_t  locksvtaircr: 1;  // 0	 LOCKSVTAIRCR
    uint32_t  locksmpu  : 1;  // 1	 LOCKSMPU
    uint32_t  locksau   : 1;  // 2	 LOCKSAU
    uint32_t  reserve0  : 29; // 3    Reserve
} reg_syscfg_cslockr_t;

typedef struct {
    uint32_t  cll       : 1;  // 0	 LOCKUP (hardfault) output enable bit
    uint32_t  spl       : 1;  // 1	 SRAM ECC lock bit
    uint32_t  pvdl      : 1;  // 2	 PVD lock enable bit
    uint32_t  eccl      : 1;  // 3	 ECC Lock
    uint32_t  reserve0  : 28; // 4    Reserve
} reg_syscfg_cfgr2_t;

typedef struct {
    uint32_t  mclr      : 1;  // 0	 MCLR
    uint32_t  reserve0  : 15; // 1    Reserve
    uint32_t  ipmee     : 1;  // 16	 IPMEE
    uint32_t  reserve1  : 15; // 17   Reserve
} reg_syscfg_mesr_t;

typedef struct {
    uint32_t  en1       : 1;  // 0	 EN1
    uint32_t  cs1       : 1;  // 1	 CS1
    uint32_t  en2       : 1;  // 2	 EN2
    uint32_t  cs2       : 1;  // 3	 CS2
    uint32_t  reserve0  : 4; // 4    Reserve
    uint32_t  rdy1      : 1;  // 8	 RDY1
    uint32_t  rdy2      : 1;  // 9	 RDY2
    uint32_t  reserve1  : 22; // 10   Reserve
} reg_syscfg_cccsr_t;

typedef struct {
    uint32_t  ncv1      : 4;  // 0	 NCV1
    uint32_t  pcv1      : 4;  // 4	 PCV1
    uint32_t  ncv2      : 4;  // 8	 NCV2
    uint32_t  pcv2      : 4;  // 12	 PCV2
    uint32_t  reserve0  : 16; // 16   Reserve
} reg_syscfg_ccvr_t;

typedef struct {
    uint32_t  ncc1      : 4;  // 0	 NCC1
    uint32_t  pcc1      : 4;  // 4	 PCC1
    uint32_t  ncc2      : 4;  // 8	 NCC2
    uint32_t  pcc2      : 4;  // 12	 PCC2
    uint32_t  reserve0  : 16; // 16   Reserve
} reg_syscfg_cccr_t;

typedef struct {
    uint32_t  rsscmd    : 16; // 0	 RSS commands
    uint32_t  reserve0  : 16; // 16   Reserve
} reg_syscfg_rsscmdr_t;

typedef struct {
    uint32_t  cc1enrxfilter: 1;  // 0	 CC1ENRXFILTER
    uint32_t  cc2enrxfilter: 1;  // 1	 CC2ENRXFILTER
    uint32_t  reserve0  : 30; // 2    Reserve
} reg_syscfg_ucpdr_t;

typedef struct {
    volatile reg_syscfg_seccfgr_t seccfgr;
    volatile reg_syscfg_cfgr1_t cfgr1;
    volatile reg_syscfg_fpuimr_t fpuimr;
    volatile reg_syscfg_cnslckr_t cnslckr;
    volatile reg_syscfg_cslockr_t cslockr;
    volatile reg_syscfg_cfgr2_t cfgr2;
    volatile reg_syscfg_mesr_t mesr;
    volatile reg_syscfg_cccsr_t cccsr;
    volatile reg_syscfg_ccvr_t ccvr;
    volatile reg_syscfg_cccr_t cccr;
    volatile uint32_t reserve0[1];
    volatile reg_syscfg_rsscmdr_t rsscmdr;
    volatile uint32_t reserve1[16];
    volatile reg_syscfg_ucpdr_t ucpdr;
} reg_syscfg_t;