#include typedef struct { uint32_t glock : 1; // 0 lock the control register of the MPCBB until next reset uint32_t reserve0 : 29; // 1 Reserve uint32_t invsecstate: 1; // 30 SRAMx clocks security state uint32_t srwiladis : 1; // 31 secure read/write illegal access disable } reg_gtzc2_mpcbb_mpcbb4_cr_t; typedef struct { uint32_t splck0 : 1; // 0 Security/privilege configuration lock for super-block 0 uint32_t reserve0 : 31; // 1 Reserve } reg_gtzc2_mpcbb_mpcbb4_cfglock_t; typedef struct { uint32_t sec0 : 1; // 0 SEC0 uint32_t sec1 : 1; // 1 SEC1 uint32_t sec2 : 1; // 2 SEC2 uint32_t sec3 : 1; // 3 SEC3 uint32_t sec4 : 1; // 4 SEC4 uint32_t sec5 : 1; // 5 SEC5 uint32_t sec6 : 1; // 6 SEC6 uint32_t sec7 : 1; // 7 SEC7 uint32_t sec8 : 1; // 8 SEC8 uint32_t sec9 : 1; // 9 SEC9 uint32_t sec10 : 1; // 10 SEC10 uint32_t sec11 : 1; // 11 SEC11 uint32_t sec12 : 1; // 12 SEC12 uint32_t sec13 : 1; // 13 SEC13 uint32_t sec14 : 1; // 14 SEC14 uint32_t sec15 : 1; // 15 SEC15 uint32_t sec16 : 1; // 16 SEC16 uint32_t sec17 : 1; // 17 SEC17 uint32_t sec18 : 1; // 18 SEC18 uint32_t sec19 : 1; // 19 SEC19 uint32_t sec20 : 1; // 20 SEC20 uint32_t sec21 : 1; // 21 SEC21 uint32_t sec22 : 1; // 22 SEC22 uint32_t sec23 : 1; // 23 SEC23 uint32_t sec24 : 1; // 24 SEC24 uint32_t sec25 : 1; // 25 SEC25 uint32_t sec26 : 1; // 26 SEC26 uint32_t sec27 : 1; // 27 SEC27 uint32_t sec28 : 1; // 28 SEC28 uint32_t sec29 : 1; // 29 SEC29 uint32_t sec30 : 1; // 30 SEC30 uint32_t sec31 : 1; // 31 SEC31 } reg_gtzc2_mpcbb_mpcbb4_seccfgr0_t; typedef struct { uint32_t priv0 : 1; // 0 PRIV0 uint32_t priv1 : 1; // 1 PRIV1 uint32_t priv2 : 1; // 2 PRIV2 uint32_t priv3 : 1; // 3 PRIV3 uint32_t priv4 : 1; // 4 PRIV4 uint32_t priv5 : 1; // 5 PRIV5 uint32_t priv6 : 1; // 6 PRIV6 uint32_t priv7 : 1; // 7 PRIV7 uint32_t priv8 : 1; // 8 PRIV8 uint32_t priv9 : 1; // 9 PRIV9 uint32_t priv10 : 1; // 10 PRIV10 uint32_t priv11 : 1; // 11 PRIV11 uint32_t priv12 : 1; // 12 PRIV12 uint32_t priv13 : 1; // 13 PRIV13 uint32_t priv14 : 1; // 14 PRIV14 uint32_t priv15 : 1; // 15 PRIV15 uint32_t priv16 : 1; // 16 PRIV16 uint32_t priv17 : 1; // 17 PRIV17 uint32_t priv18 : 1; // 18 PRIV18 uint32_t priv19 : 1; // 19 PRIV19 uint32_t priv20 : 1; // 20 PRIV20 uint32_t priv21 : 1; // 21 PRIV21 uint32_t priv22 : 1; // 22 PRIV22 uint32_t priv23 : 1; // 23 PRIV23 uint32_t priv24 : 1; // 24 PRIV24 uint32_t priv25 : 1; // 25 PRIV25 uint32_t priv26 : 1; // 26 PRIV26 uint32_t priv27 : 1; // 27 PRIV27 uint32_t priv28 : 1; // 28 PRIV28 uint32_t priv29 : 1; // 29 PRIV29 uint32_t priv30 : 1; // 30 PRIV30 uint32_t priv31 : 1; // 31 PRIV31 } reg_gtzc2_mpcbb_mpcbb4_privcfgr0_t; typedef struct { volatile reg_gtzc2_mpcbb_mpcbb4_cr_t mpcbb4_cr; volatile uint32_t reserve0[3]; volatile reg_gtzc2_mpcbb_mpcbb4_cfglock_t mpcbb4_cfglock; volatile uint32_t reserve1[59]; volatile reg_gtzc2_mpcbb_mpcbb4_seccfgr0_t mpcbb4_seccfgr0; volatile uint32_t reserve2[63]; volatile reg_gtzc2_mpcbb_mpcbb4_privcfgr0_t mpcbb4_privcfgr0; } reg_gtzc2_mpcbb_t;