#include typedef struct { uint32_t ecce : 1; // 0 ECCE uint32_t reserve0 : 3; // 1 Reserve uint32_t ale : 1; // 4 ALE uint32_t reserve1 : 3; // 5 Reserve uint32_t sramer : 1; // 8 SRAMER uint32_t reserve2 : 7; // 9 Reserve uint32_t wsc : 3; // 16 WSC uint32_t reserve3 : 13; // 19 Reserve } reg_sec_ramcfg_ram1cr_t; typedef struct { uint32_t sedc : 1; // 0 SEDC uint32_t ded : 1; // 1 DED uint32_t reserve0 : 6; // 2 Reserve uint32_t srambusy : 1; // 8 SRAMBUSY uint32_t reserve1 : 23; // 9 Reserve } reg_sec_ramcfg_ram1isr_t; typedef struct { uint32_t erasekey : 8; // 0 ERASEKEY uint32_t reserve0 : 24; // 8 Reserve } reg_sec_ramcfg_ram1erkeyr_t; typedef struct { uint32_t ecce : 1; // 0 ECCE uint32_t reserve0 : 3; // 1 Reserve uint32_t ale : 1; // 4 ALE uint32_t reserve1 : 3; // 5 Reserve uint32_t sramer : 1; // 8 SRAMER uint32_t reserve2 : 7; // 9 Reserve uint32_t wsc : 3; // 16 WSC uint32_t reserve3 : 13; // 19 Reserve } reg_sec_ramcfg_ram2cr_t; typedef struct { uint32_t seie : 1; // 0 SEIE uint32_t deie : 1; // 1 DEIE uint32_t reserve0 : 1; // 2 Reserve uint32_t eccnmi : 1; // 3 ECCNMI uint32_t reserve1 : 28; // 4 Reserve } reg_sec_ramcfg_ram2ier_t; typedef struct { uint32_t sedc : 1; // 0 SEDC uint32_t ded : 1; // 1 DED uint32_t reserve0 : 6; // 2 Reserve uint32_t srambusy : 1; // 8 SRAMBUSY uint32_t reserve1 : 23; // 9 Reserve } reg_sec_ramcfg_ram2isr_t; typedef struct { uint32_t esea : 32; // 0 ESEA } reg_sec_ramcfg_ram2sear_t; typedef struct { uint32_t edea : 32; // 0 EDEA } reg_sec_ramcfg_ram2dear_t; typedef struct { uint32_t csedc : 1; // 0 CSEDC uint32_t cded : 1; // 1 CDED uint32_t reserve0 : 30; // 2 Reserve } reg_sec_ramcfg_ram2icr_t; typedef struct { uint32_t p0wp : 1; // 0 P0WP uint32_t p1wp : 1; // 1 P1WP uint32_t p2wp : 1; // 2 P2WP uint32_t p3wp : 1; // 3 P3WP uint32_t p4wp : 1; // 4 P4WP uint32_t p5wp : 1; // 5 P5WP uint32_t p6wp : 1; // 6 P6WP uint32_t p7wp : 1; // 7 P7WP uint32_t p8wp : 1; // 8 P8WP uint32_t p9wp : 1; // 9 P9WP uint32_t p10wp : 1; // 10 P10WP uint32_t p11wp : 1; // 11 P11WP uint32_t p12wp : 1; // 12 P12WP uint32_t p13wp : 1; // 13 P13WP uint32_t p14wp : 1; // 14 P14WP uint32_t p15wp : 1; // 15 P15WP uint32_t p16wp : 1; // 16 P16WP uint32_t p17wp : 1; // 17 P17WP uint32_t p18wp : 1; // 18 P18WP uint32_t p19wp : 1; // 19 P19WP uint32_t p20wp : 1; // 20 P20WP uint32_t p21wp : 1; // 21 P21WP uint32_t p22wp : 1; // 22 P22WP uint32_t p23wp : 1; // 23 P23WP uint32_t p24wp : 1; // 24 P24WP uint32_t p25wp : 1; // 25 P25WP uint32_t p26wp : 1; // 26 P26WP uint32_t p27wp : 1; // 27 P27WP uint32_t p28wp : 1; // 28 P28WP uint32_t p29wp : 1; // 29 P29WP uint32_t p30wp : 1; // 30 P30WP uint32_t p31wp : 1; // 31 P31WP } reg_sec_ramcfg_ram2wpr1_t; typedef struct { uint32_t p32wp : 1; // 0 P32WP uint32_t p33wp : 1; // 1 P33WP uint32_t p34wp : 1; // 2 P34WP uint32_t p35wp : 1; // 3 P35WP uint32_t p36wp : 1; // 4 P36WP uint32_t p37wp : 1; // 5 P37WP uint32_t p38wp : 1; // 6 P38WP uint32_t p39wp : 1; // 7 P39WP uint32_t p40wp : 1; // 8 P40WP uint32_t p41wp : 1; // 9 P41WP uint32_t p42wp : 1; // 10 P42WP uint32_t p43wp : 1; // 11 P43WP uint32_t p44wp : 1; // 12 P44WP uint32_t p45wp : 1; // 13 P45WP uint32_t p46wp : 1; // 14 P46WP uint32_t p47wp : 1; // 15 P47WP uint32_t p48wp : 1; // 16 P48WP uint32_t p49wp : 1; // 17 P49WP uint32_t p50wp : 1; // 18 P50WP uint32_t p51wp : 1; // 19 P51WP uint32_t p52wp : 1; // 20 P52WP uint32_t p53wp : 1; // 21 P53WP uint32_t p54wp : 1; // 22 P54WP uint32_t p55wp : 1; // 23 P55WP uint32_t p56wp : 1; // 24 P56WP uint32_t p57wp : 1; // 25 P57WP uint32_t p58wp : 1; // 26 P58WP uint32_t p59wp : 1; // 27 P59WP uint32_t p60wp : 1; // 28 P60WP uint32_t p61wp : 1; // 29 P61WP uint32_t p62wp : 1; // 30 P62WP uint32_t p63wp : 1; // 31 P63WP } reg_sec_ramcfg_ram2wpr2_t; typedef struct { uint32_t ecckey : 8; // 0 ECCKEY uint32_t reserve0 : 24; // 8 Reserve } reg_sec_ramcfg_ram2ecckeyr_t; typedef struct { uint32_t erasekey : 8; // 0 ERASEKEY uint32_t reserve0 : 24; // 8 Reserve } reg_sec_ramcfg_ram2erkeyr_t; typedef struct { uint32_t ecce : 1; // 0 ECCE uint32_t reserve0 : 3; // 1 Reserve uint32_t ale : 1; // 4 ALE uint32_t reserve1 : 3; // 5 Reserve uint32_t sramer : 1; // 8 SRAMER uint32_t reserve2 : 7; // 9 Reserve uint32_t wsc : 3; // 16 WSC uint32_t reserve3 : 13; // 19 Reserve } reg_sec_ramcfg_ram3cr_t; typedef struct { uint32_t seie : 1; // 0 SEIE uint32_t deie : 1; // 1 DEIE uint32_t reserve0 : 1; // 2 Reserve uint32_t eccnmi : 1; // 3 ECCNMI uint32_t reserve1 : 28; // 4 Reserve } reg_sec_ramcfg_ram3ier_t; typedef struct { uint32_t sedc : 1; // 0 SEDC uint32_t ded : 1; // 1 DED uint32_t reserve0 : 6; // 2 Reserve uint32_t srambusy : 1; // 8 SRAMBUSY uint32_t reserve1 : 23; // 9 Reserve } reg_sec_ramcfg_ram3isr_t; typedef struct { uint32_t esea : 32; // 0 ESEA } reg_sec_ramcfg_ram3sear_t; typedef struct { uint32_t edea : 32; // 0 EDEA } reg_sec_ramcfg_ram3dear_t; typedef struct { uint32_t csedc : 1; // 0 CSEDC uint32_t cded : 1; // 1 CDED uint32_t reserve0 : 30; // 2 Reserve } reg_sec_ramcfg_ram3icr_t; typedef struct { uint32_t ecckey : 8; // 0 ECCKEY uint32_t reserve0 : 24; // 8 Reserve } reg_sec_ramcfg_ram3ecckeyr_t; typedef struct { uint32_t erasekey : 8; // 0 ERASEKEY uint32_t reserve0 : 24; // 8 Reserve } reg_sec_ramcfg_ram3erkeyr_t; typedef struct { uint32_t ecce : 1; // 0 ECCE uint32_t reserve0 : 3; // 1 Reserve uint32_t ale : 1; // 4 ALE uint32_t reserve1 : 3; // 5 Reserve uint32_t sramer : 1; // 8 SRAMER uint32_t reserve2 : 7; // 9 Reserve uint32_t wsc : 3; // 16 WSC uint32_t reserve3 : 13; // 19 Reserve } reg_sec_ramcfg_ram4cr_t; typedef struct { uint32_t sedc : 1; // 0 SEDC uint32_t ded : 1; // 1 DED uint32_t reserve0 : 6; // 2 Reserve uint32_t srambusy : 1; // 8 SRAMBUSY uint32_t reserve1 : 23; // 9 Reserve } reg_sec_ramcfg_ram4isr_t; typedef struct { uint32_t erasekey : 8; // 0 ERASEKEY uint32_t reserve0 : 24; // 8 Reserve } reg_sec_ramcfg_ram4erkeyr_t; typedef struct { uint32_t ecce : 1; // 0 ECCE uint32_t reserve0 : 3; // 1 Reserve uint32_t ale : 1; // 4 ALE uint32_t reserve1 : 3; // 5 Reserve uint32_t sramer : 1; // 8 SRAMER uint32_t reserve2 : 7; // 9 Reserve uint32_t wsc : 3; // 16 WSC uint32_t reserve3 : 13; // 19 Reserve } reg_sec_ramcfg_ram5cr_t; typedef struct { uint32_t seie : 1; // 0 SEIE uint32_t deie : 1; // 1 DEIE uint32_t reserve0 : 1; // 2 Reserve uint32_t eccnmi : 1; // 3 ECCNMI uint32_t reserve1 : 28; // 4 Reserve } reg_sec_ramcfg_ram5ier_t; typedef struct { uint32_t sedc : 1; // 0 SEDC uint32_t ded : 1; // 1 DED uint32_t reserve0 : 6; // 2 Reserve uint32_t srambusy : 1; // 8 SRAMBUSY uint32_t reserve1 : 23; // 9 Reserve } reg_sec_ramcfg_ram5isr_t; typedef struct { uint32_t esea : 32; // 0 ESEA } reg_sec_ramcfg_ram5sear_t; typedef struct { uint32_t edea : 32; // 0 EDEA } reg_sec_ramcfg_ram5dear_t; typedef struct { uint32_t csedc : 1; // 0 CSEDC uint32_t cded : 1; // 1 CDED uint32_t reserve0 : 30; // 2 Reserve } reg_sec_ramcfg_ram5icr_t; typedef struct { volatile reg_sec_ramcfg_ram1cr_t ram1cr; volatile uint32_t reserve0[1]; volatile reg_sec_ramcfg_ram1isr_t ram1isr; volatile uint32_t reserve1[7]; volatile reg_sec_ramcfg_ram1erkeyr_t ram1erkeyr; volatile uint32_t reserve2[5]; volatile reg_sec_ramcfg_ram2cr_t ram2cr; volatile reg_sec_ramcfg_ram2ier_t ram2ier; volatile reg_sec_ramcfg_ram2isr_t ram2isr; volatile reg_sec_ramcfg_ram2sear_t ram2sear; volatile reg_sec_ramcfg_ram2dear_t ram2dear; volatile reg_sec_ramcfg_ram2icr_t ram2icr; volatile reg_sec_ramcfg_ram2wpr1_t ram2wpr1; volatile reg_sec_ramcfg_ram2wpr2_t ram2wpr2; volatile uint32_t reserve3[1]; volatile reg_sec_ramcfg_ram2ecckeyr_t ram2ecckeyr; volatile reg_sec_ramcfg_ram2erkeyr_t ram2erkeyr; volatile uint32_t reserve4[5]; volatile reg_sec_ramcfg_ram3cr_t ram3cr; volatile reg_sec_ramcfg_ram3ier_t ram3ier; volatile reg_sec_ramcfg_ram3isr_t ram3isr; volatile reg_sec_ramcfg_ram3sear_t ram3sear; volatile reg_sec_ramcfg_ram3dear_t ram3dear; volatile reg_sec_ramcfg_ram3icr_t ram3icr; volatile uint32_t reserve5[3]; volatile reg_sec_ramcfg_ram3ecckeyr_t ram3ecckeyr; volatile reg_sec_ramcfg_ram3erkeyr_t ram3erkeyr; volatile uint32_t reserve6[5]; volatile reg_sec_ramcfg_ram4cr_t ram4cr; volatile uint32_t reserve7[1]; volatile reg_sec_ramcfg_ram4isr_t ram4isr; volatile uint32_t reserve8[7]; volatile reg_sec_ramcfg_ram4erkeyr_t ram4erkeyr; volatile uint32_t reserve9[5]; volatile reg_sec_ramcfg_ram5cr_t ram5cr; volatile reg_sec_ramcfg_ram5ier_t ram5ier; volatile reg_sec_ramcfg_ram5isr_t ram5isr; volatile reg_sec_ramcfg_ram5sear_t ram5sear; volatile reg_sec_ramcfg_ram5dear_t ram5dear; volatile reg_sec_ramcfg_ram5icr_t ram5icr; } reg_sec_ramcfg_t;