#include typedef struct { uint32_t pwrctrl : 2; // 0 SDMMC state control bits uint32_t vswitch : 1; // 2 Voltage switch sequence start uint32_t vswitchen : 1; // 3 Voltage switch procedure enable uint32_t dirpol : 1; // 4 Data and command direction signals polarity selection uint32_t reserve0 : 27; // 5 Reserve } reg_sdmmc_power_t2; typedef struct { uint32_t clkdiv : 10; // 0 Clock divide factor uint32_t reserve0 : 2; // 10 Reserve uint32_t pwrsav : 1; // 12 Power saving configuration bit uint32_t reserve1 : 1; // 13 Reserve uint32_t widbus : 2; // 14 Wide bus mode enable bit uint32_t negedge : 1; // 16 SDIO_CK dephasing selection bit uint32_t hwfc_en : 1; // 17 HW Flow Control enable uint32_t ddr : 1; // 18 Data rate signaling selection uint32_t busspeed : 1; // 19 Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50,DDR50, SDR104 uint32_t selclkrx : 2; // 20 Receive clock selection uint32_t reserve2 : 10; // 22 Reserve } reg_sdmmc_clkcr_t2; typedef struct { uint32_t cmdarg : 32; // 0 Command argument } reg_sdmmc_argr_t; typedef struct { uint32_t cmdindex : 6; // 0 Command index uint32_t cmdtrans : 1; // 6 The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM uint32_t cmdstop : 1; // 7 The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM uint32_t waitresp : 2; // 8 Wait for response bits uint32_t waitint : 1; // 10 CPSM waits for interrupt request uint32_t waitpend : 1; // 11 CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM uint32_t cpsmen : 1; // 12 Command path state machine (CPSM) Enable bit uint32_t dthold : 1; // 13 Hold new data block transmission and reception in the DPSM uint32_t bootmode : 1; // 14 Select the boot mode procedure to be used uint32_t booten : 1; // 15 Enable boot mode procedure uint32_t cmdsuspend: 1; // 16 The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end uint32_t reserve0 : 15; // 17 Reserve } reg_sdmmc_cmdr_t; typedef struct { uint32_t respcmd : 6; // 0 Response command index uint32_t reserve0 : 26; // 6 Reserve } reg_sdmmc_respcmdr_t; typedef struct { uint32_t cardstatus1: 32; // 0 CARDSTATUS1 } reg_sdmmc_resp1_t; typedef struct { uint32_t cardstatus2: 32; // 0 CARDSTATUS2 } reg_sdmmc_resp2_t; typedef struct { uint32_t cardstatus3: 32; // 0 CARDSTATUS3 } reg_sdmmc_resp3_t; typedef struct { uint32_t cardstatus4: 32; // 0 CARDSTATUS4 } reg_sdmmc_resp4_t; typedef struct { uint32_t datatime : 32; // 0 Data and R1b busy timeout period } reg_sdmmc_dtimer_t; typedef struct { uint32_t datalength: 25; // 0 Data length value uint32_t reserve0 : 7; // 25 Reserve } reg_sdmmc_dlenr_t; typedef struct { uint32_t dten : 1; // 0 DTEN uint32_t dtdir : 1; // 1 Data transfer direction selection uint32_t dtmode : 2; // 2 Data transfer mode selection uint32_t dblocksize: 4; // 4 Data block size uint32_t rwstart : 1; // 8 Read wait start uint32_t rwstop : 1; // 9 Read wait stop uint32_t rwmod : 1; // 10 Read wait mode uint32_t sdioen : 1; // 11 SD I/O enable functions uint32_t bootacken : 1; // 12 Enable the reception of the boot acknowledgment uint32_t fiforst : 1; // 13 FIFO reset, will flush any remaining data uint32_t reserve0 : 18; // 14 Reserve } reg_sdmmc_dctrl_t2; typedef struct { uint32_t datacount : 25; // 0 Data count value uint32_t reserve0 : 7; // 25 Reserve } reg_sdmmc_dcntr_t; typedef struct { uint32_t ccrcfail : 1; // 0 Command response received (CRC check failed) uint32_t dcrcfail : 1; // 1 Data block sent/received (CRC check failed) uint32_t ctimeout : 1; // 2 Command response timeout uint32_t dtimeout : 1; // 3 Data timeout uint32_t txunderr : 1; // 4 Transmit FIFO underrun error (masked by hardware when IDMA is enabled) uint32_t rxoverr : 1; // 5 Received FIFO overrun error (masked by hardware when IDMA is enabled) uint32_t cmdrend : 1; // 6 Command response received (CRC check passed, or no CRC) uint32_t cmdsent : 1; // 7 Command sent (no response required) uint32_t dataend : 1; // 8 Data transfer ended correctly uint32_t dhold : 1; // 9 Data transfer Hold uint32_t dbckend : 1; // 10 Data block sent/received uint32_t dabort : 1; // 11 Data transfer aborted by CMD12 uint32_t dpsmact : 1; // 12 Data path state machine active, i.e. not in Idle state uint32_t cpsmact : 1; // 13 Command path state machine active, i.e. not in Idle state uint32_t txfifohe : 1; // 14 Transmit FIFO half empty uint32_t rxfifohf : 1; // 15 Receive FIFO half full uint32_t txfifof : 1; // 16 Transmit FIFO full uint32_t rxfifof : 1; // 17 Receive FIFO full uint32_t txfifoe : 1; // 18 Transmit FIFO empty uint32_t rxfifoe : 1; // 19 Receive FIFO empty uint32_t busyd0 : 1; // 20 Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response uint32_t busyd0end : 1; // 21 end of SDMMC_D0 Busy following a CMD response detected uint32_t sdioit : 1; // 22 SDIO interrupt received uint32_t ackfail : 1; // 23 Boot acknowledgment received (boot acknowledgment check fail) uint32_t acktimeout: 1; // 24 Boot acknowledgment timeout uint32_t vswend : 1; // 25 Voltage switch critical timing section completion uint32_t ckstop : 1; // 26 SDMMC_CK stopped in Voltage switch procedure uint32_t idmate : 1; // 27 IDMA transfer error uint32_t idmabtc : 1; // 28 IDMA buffer transfer complete uint32_t reserve0 : 3; // 29 Reserve } reg_sdmmc_star_t; typedef struct { uint32_t ccrcfailc : 1; // 0 CCRCFAIL flag clear bit uint32_t dcrcfailc : 1; // 1 DCRCFAIL flag clear bit uint32_t ctimeoutc : 1; // 2 CTIMEOUT flag clear bit uint32_t dtimeoutc : 1; // 3 DTIMEOUT flag clear bit uint32_t txunderrc : 1; // 4 TXUNDERR flag clear bit uint32_t rxoverrc : 1; // 5 RXOVERR flag clear bit uint32_t cmdrendc : 1; // 6 CMDREND flag clear bit uint32_t cmdsentc : 1; // 7 CMDSENT flag clear bit uint32_t dataendc : 1; // 8 DATAEND flag clear bit uint32_t dholdc : 1; // 9 DHOLD flag clear bit uint32_t dbckendc : 1; // 10 DBCKEND flag clear bit uint32_t dabortc : 1; // 11 DABORT flag clear bit uint32_t reserve0 : 9; // 12 Reserve uint32_t busyd0endc: 1; // 21 BUSYD0END flag clear bit uint32_t sdioitc : 1; // 22 SDIOIT flag clear bit uint32_t ackfailc : 1; // 23 ACKFAIL flag clear bit uint32_t acktimeoutc: 1; // 24 ACKTIMEOUT flag clear bit uint32_t vswendc : 1; // 25 VSWEND flag clear bit uint32_t ckstopc : 1; // 26 CKSTOP flag clear bit uint32_t idmatec : 1; // 27 IDMA transfer error clear bit uint32_t idmabtcc : 1; // 28 IDMA buffer transfer complete clear bit uint32_t reserve1 : 3; // 29 Reserve } reg_sdmmc_icr_t; typedef struct { uint32_t ccrcfailie: 1; // 0 Command CRC fail interrupt enable uint32_t dcrcfailie: 1; // 1 Data CRC fail interrupt enable uint32_t ctimeoutie: 1; // 2 Command timeout interrupt enable uint32_t dtimeoutie: 1; // 3 Data timeout interrupt enable uint32_t txunderrie: 1; // 4 Tx FIFO underrun error interrupt enable uint32_t rxoverrie : 1; // 5 Rx FIFO overrun error interrupt enable uint32_t cmdrendie : 1; // 6 Command response received interrupt enable uint32_t cmdsentie : 1; // 7 Command sent interrupt enable uint32_t dataendie : 1; // 8 Data end interrupt enable uint32_t dholdie : 1; // 9 Data hold interrupt enable uint32_t dbckendie : 1; // 10 Data block end interrupt enable uint32_t dabortie : 1; // 11 Data transfer aborted interrupt enable uint32_t reserve0 : 2; // 12 Reserve uint32_t txfifoheie: 1; // 14 Tx FIFO half empty interrupt enable uint32_t rxfifohfie: 1; // 15 Rx FIFO half full interrupt enable uint32_t reserve1 : 1; // 16 Reserve uint32_t rxfifofie : 1; // 17 Rx FIFO full interrupt enable uint32_t txfifoeie : 1; // 18 Tx FIFO empty interrupt enable uint32_t reserve2 : 2; // 19 Reserve uint32_t busyd0endie: 1; // 21 BUSYD0END interrupt enable uint32_t sdioitie : 1; // 22 SDIO mode interrupt received interrupt enable uint32_t ackfailie : 1; // 23 Acknowledgment Fail interrupt enable uint32_t acktimeoutie: 1; // 24 Acknowledgment timeout interrupt enable uint32_t vswendie : 1; // 25 Voltage switch critical timing section completion interrupt enable uint32_t ckstopie : 1; // 26 Voltage Switch clock stopped interrupt enable uint32_t reserve3 : 1; // 27 Reserve uint32_t idmabtcie : 1; // 28 IDMA buffer transfer complete interrupt enable uint32_t reserve4 : 3; // 29 Reserve } reg_sdmmc_maskr_t; typedef struct { uint32_t acktime : 25; // 0 Boot acknowledgment timeout period uint32_t reserve0 : 7; // 25 Reserve } reg_sdmmc_acktimer_t; typedef struct { uint32_t fifodata : 32; // 0 Receive and transmit FIFO data } reg_sdmmc_fifor0_t; typedef struct { uint32_t fifodata : 32; // 0 Receive and transmit FIFO data } reg_sdmmc_fifor1_t; typedef struct { uint32_t fifodata : 32; // 0 Receive and transmit FIFO data } reg_sdmmc_fifor2_t; typedef struct { uint32_t fifodata : 32; // 0 Receive and transmit FIFO data } reg_sdmmc_fifor3_t; typedef struct { uint32_t fifodata : 32; // 0 Receive and transmit FIFO data } reg_sdmmc_fifor4_t; typedef struct { uint32_t fifodata : 32; // 0 Receive and transmit FIFO data } reg_sdmmc_fifor5_t; typedef struct { uint32_t fifodata : 32; // 0 Receive and transmit FIFO data } reg_sdmmc_fifor6_t; typedef struct { uint32_t fifodata : 32; // 0 Receive and transmit FIFO data } reg_sdmmc_fifor7_t; typedef struct { uint32_t fifodata : 32; // 0 Receive and transmit FIFO data } reg_sdmmc_fifor8_t; typedef struct { uint32_t fifodata : 32; // 0 Receive and transmit FIFO data } reg_sdmmc_fifor9_t; typedef struct { uint32_t fifodata : 32; // 0 Receive and transmit FIFO data } reg_sdmmc_fifor10_t; typedef struct { uint32_t fifodata : 32; // 0 Receive and transmit FIFO data } reg_sdmmc_fifor11_t; typedef struct { uint32_t fifodata : 32; // 0 Receive and transmit FIFO data } reg_sdmmc_fifor12_t; typedef struct { uint32_t fifodata : 32; // 0 Receive and transmit FIFO data } reg_sdmmc_fifor13_t; typedef struct { uint32_t fifodata : 32; // 0 Receive and transmit FIFO data } reg_sdmmc_fifor14_t; typedef struct { uint32_t fifodata : 32; // 0 Receive and transmit FIFO data } reg_sdmmc_fifor15_t; typedef struct { uint32_t idmaen : 1; // 0 IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). uint32_t idmabmode : 1; // 1 Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). uint32_t reserve0 : 30; // 2 Reserve } reg_sdmmc_idmactrlr_t; typedef struct { uint32_t reserve0 : 5; // 0 Reserve uint32_t idmabndt : 12; // 5 Number of bytes per buffer uint32_t reserve1 : 15; // 17 Reserve } reg_sdmmc_idmabsizer_t; typedef struct { uint32_t idmabase : 32; // 0 Buffer memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only) } reg_sdmmc_idmabaser_t; typedef struct { uint32_t reserve0 : 2; // 0 Reserve uint32_t idmala : 14; // 2 Acknowledge linked list buffer ready uint32_t reserve1 : 13; // 16 Reserve uint32_t abr : 1; // 29 Acknowledge linked list buffer ready uint32_t uls : 1; // 30 Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1) uint32_t ula : 1; // 31 Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode) } reg_sdmmc_idmalar_t2; typedef struct { uint32_t reserve0 : 2; // 0 Reserve uint32_t idmaba : 30; // 2 Word aligned Linked list memory base address } reg_sdmmc_idmabar_t; typedef struct { volatile reg_sdmmc_power_t2 power; volatile reg_sdmmc_clkcr_t2 clkcr; volatile reg_sdmmc_argr_t argr; volatile reg_sdmmc_cmdr_t cmdr; volatile reg_sdmmc_respcmdr_t respcmdr; volatile reg_sdmmc_resp1_t resp1; volatile reg_sdmmc_resp2_t resp2; volatile reg_sdmmc_resp3_t resp3; volatile reg_sdmmc_resp4_t resp4; volatile reg_sdmmc_dtimer_t dtimer; volatile reg_sdmmc_dlenr_t dlenr; volatile reg_sdmmc_dctrl_t2 dctrl; volatile reg_sdmmc_dcntr_t dcntr; volatile reg_sdmmc_star_t star; volatile reg_sdmmc_icr_t icr; volatile reg_sdmmc_maskr_t maskr; volatile reg_sdmmc_acktimer_t acktimer; volatile uint32_t reserve0[3]; volatile reg_sdmmc_idmactrlr_t idmactrlr; volatile reg_sdmmc_idmabsizer_t idmabsizer; volatile reg_sdmmc_idmabaser_t idmabaser; volatile uint32_t reserve2[2]; volatile reg_sdmmc_idmalar_t2 idmalar; volatile reg_sdmmc_idmabar_t idmabar; } reg_sdmmc_t;