#include typedef struct { uint32_t lpms : 3; // 0 Low-power mode selection These bits select the low-power mode entered when the CPU enters the Deepsleep mode. 10x: Standby mode (Standby mode also entered if LPMS = 11X in PWR_CR1 with BREN = 1 in PWR_BDCR1) 11x: Shutdown mode if BREN = 0 in PWR_BDCR1 uint32_t reserve0 : 2; // 3 Reserve uint32_t rrsb1 : 1; // 5 SRAM2 page 1 retention in Stop 3 and Standby modes This bit is used to keep the SRAM2 page 1 content in Stop 3 and Standby modes. The SRAM2 page 1 corresponds to the first 8 Kbytes of the SRAM2 (from SRAM2 base address to SRAM2 base address + 0x1FFF). Note: This bit has no effect in Shutdown mode. uint32_t rrsb2 : 1; // 6 SRAM2 page 2 retention in Stop 3 and Standby modes This bit is used to keep the SRAM2 page 2 content in Stop 3 and Standby modes. The SRAM2 page 2 corresponds to the last 56 Kbytes of the SRAM2 (from SRAM2 base address + 0x2000 to SRAM2 base address + 0xFFFF). Note: This bit has no effect in Shutdown mode. uint32_t ulpmen : 1; // 7 BOR ultra-low power mode This bit is used to reduce the consumption by configuring the BOR in discontinuous mode. This bit must be set to reach the lowest power consumption in the low-power modes. uint32_t sram1pd : 1; // 8 SRAM1 power down This bit is used to reduce the consumption by powering off the SRAM1. uint32_t sram2pd : 1; // 9 SRAM2 power down This bit is used to reduce the consumption by powering off the SRAM2. uint32_t sram3pd : 1; // 10 SRAM3 power down This bit is used to reduce the consumption by powering off the SRAM3. uint32_t sram4pd : 1; // 11 SRAM4 power down This bit is used to reduce the consumption by powering off the SRAM4. uint32_t reserve1 : 20; // 12 Reserve } reg_pwr_cr1_t; typedef struct { uint32_t sram1pds1 : 1; // 0 SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) uint32_t sram1pds2 : 1; // 1 SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) uint32_t sram1pds3 : 1; // 2 SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) uint32_t reserve0 : 1; // 3 Reserve uint32_t sram2pds1 : 1; // 4 SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0, 1, 2) Note: The SRAM2 page 1 retention in Stop 3 is controlled by RRSB1 bit in PWR_CR1. uint32_t sram2pds2 : 1; // 5 SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0, 1, 2) Note: The SRAM2 page 2 retention in Stop 3 is controlled by RRSB2 bit in PWR_CR1. uint32_t sram4pds : 1; // 6 SRAM4 power-down in Stop modes (Stop 0, 1, 2, 3) uint32_t reserve1 : 1; // 7 Reserve uint32_t icrampds : 1; // 8 ICACHE SRAM power-down in Stop modes (Stop 0, 1, 2, 3) uint32_t dc1rampds : 1; // 9 DCACHE1 SRAM power-down in Stop modes (Stop 0, 1, 2, 3) uint32_t dma2drampds: 1; // 10 DMA2D SRAM power-down in Stop modes (Stop 0, 1, 2, 3) uint32_t prampds : 1; // 11 FMAC, FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0, 1, 2, 3) uint32_t pkarampds : 1; // 12 PKA SRAM power-down uint32_t sram4fwu : 1; // 13 SRAM4 fast wakeup from Stop 0, Stop 1 and Stop 2 modes This bit is used to obtain the best trade-off between low-power consumption and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting Stop 0, 1 and 2 modes, and also increases the LPDMA access time to SRAM4 during Stop modes. uint32_t flashfwu : 1; // 14 Flash memory fast wakeup from Stop 0 and Stop 1 modes This bit is used to obtain the best trade-off between low-power consumption and wakeup time when exiting the Stop 0 or Stop 1 modes. When this bit is set, the Flash memory remains in normal mode in Stop 0 and Stop 1 modes, which offers a faster startup time with higher consumption. uint32_t reserve2 : 1; // 15 Reserve uint32_t sram3pds1 : 1; // 16 SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) uint32_t sram3pds2 : 1; // 17 SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) uint32_t sram3pds3 : 1; // 18 SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) uint32_t sram3pds4 : 1; // 19 SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) uint32_t sram3pds5 : 1; // 20 SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) uint32_t sram3pds6 : 1; // 21 SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) uint32_t sram3pds7 : 1; // 22 SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) uint32_t sram3pds8 : 1; // 23 SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) uint32_t reserve3 : 7; // 24 Reserve uint32_t srdrun : 1; // 31 SmartRun domain in Run mode } reg_pwr_cr2_t; typedef struct { uint32_t reserve0 : 1; // 0 Reserve uint32_t regsel : 1; // 1 Regulator selection Note: REGSEL is reserved and must be kept at reset value in packages without SMPS. uint32_t fsten : 1; // 2 Fast soft start uint32_t reserve1 : 29; // 3 Reserve } reg_pwr_cr3_t; typedef struct { uint32_t reserve0 : 14; // 0 Reserve uint32_t boostrdy : 1; // 14 EPOD booster ready This bit is set to 1 by hardware when the power booster startup time is reached. The system clock frequency can be switched higher than 50 MHz only after this bit is set. uint32_t vosrdy : 1; // 15 Ready bit for VCORE voltage scaling output selection uint32_t vos : 2; // 16 Voltage scaling range selection This field is protected against non-secure access when SYSCLKSEC = 1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC = 1 in RCC_SECCFGR and SPRIV = 1 in PWR_PRIVCFGR, or when SYSCLKSEC = 0 and NSPRIV = 1. uint32_t boosten : 1; // 18 EPOD booster enable uint32_t reserve1 : 13; // 19 Reserve } reg_pwr_vosr_t; typedef struct { uint32_t reserve0 : 4; // 0 Reserve uint32_t pvde : 1; // 4 Power voltage detector enable uint32_t pvdls : 3; // 5 Power voltage detector level selection These bits select the voltage threshold detected by the power voltage detector: uint32_t reserve1 : 16; // 8 Reserve uint32_t uvmen : 1; // 24 VDDUSB independent USB voltage monitor enable uint32_t io2vmen : 1; // 25 VDDIO2 independent I/Os voltage monitor enable uint32_t avm1en : 1; // 26 VDDA independent analog supply voltage monitor 1 enable (1.6 V threshold) uint32_t avm2en : 1; // 27 VDDA independent analog supply voltage monitor 2 enable (1.8 V threshold) uint32_t usv : 1; // 28 VDDUSB independent USB supply valid uint32_t io2sv : 1; // 29 VDDIO2 independent I/Os supply valid This bit is used to validate the VDDIO2 supply for electrical and logical isolation purpose. Setting this bit is mandatory to use PG[15:2]. If VDDIO2 is not always present in the application, the VDDIO2 voltage monitor can be used to determine whether this supply is ready or not. uint32_t asv : 1; // 30 VDDA independent analog supply valid uint32_t reserve2 : 1; // 31 Reserve } reg_pwr_svmcr_t; typedef struct { uint32_t wupen1 : 1; // 0 Wakeup pin WKUP1 enable uint32_t wupen2 : 1; // 1 Wakeup pin WKUP2 enable uint32_t wupen3 : 1; // 2 Wakeup pin WKUP3 enable uint32_t wupen4 : 1; // 3 Wakeup pin WKUP4 enable uint32_t wupen5 : 1; // 4 Wakeup pin WKUP5 enable uint32_t wupen6 : 1; // 5 Wakeup pin WKUP6 enable uint32_t wupen7 : 1; // 6 Wakeup pin WKUP7 enable uint32_t wupen8 : 1; // 7 Wakeup pin WKUP8 enable uint32_t reserve0 : 24; // 8 Reserve } reg_pwr_wucr1_t; typedef struct { uint32_t wupp1 : 1; // 0 Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. uint32_t wupp2 : 1; // 1 Wakeup pin WKUP2 polarity This bit must be configured when WUPEN2 = 0. uint32_t wupp3 : 1; // 2 Wakeup pin WKUP3 polarity This bit must be configured when WUPEN3 = 0. uint32_t wupp4 : 1; // 3 Wakeup pin WKUP4 polarity This bit must be configured when WUPEN4 = 0. uint32_t wupp5 : 1; // 4 Wakeup pin WKUP5 polarity This bit must be configured when WUPEN5 = 0. uint32_t wupp6 : 1; // 5 Wakeup pin WKUP6 polarity This bit must be configured when WUPEN6 = 0. uint32_t wupp7 : 1; // 6 Wakeup pin WKUP7 polarity This bit must be configured when WUPEN7 = 0. uint32_t wupp8 : 1; // 7 Wakeup pin WKUP8 polarity This bit must be configured when WUPEN8 = 0. uint32_t reserve0 : 24; // 8 Reserve } reg_pwr_wucr2_t; typedef struct { uint32_t wusel1 : 2; // 0 Wakeup pin WKUP1 selection This field must be configured when WUPEN1 = 0. uint32_t wusel2 : 2; // 2 Wakeup pin WKUP2 selection This field must be configured when WUPEN2 = 0. uint32_t wusel3 : 2; // 4 Wakeup pin WKUP3 selection This field must be configured when WUPEN3 = 0. uint32_t wusel4 : 2; // 6 Wakeup pin WKUP4 selection This field must be configured when WUPEN4 = 0. uint32_t wusel5 : 2; // 8 Wakeup pin WKUP5 selection This field must be configured when WUPEN5 = 0. uint32_t wusel6 : 2; // 10 Wakeup pin WKUP6 selection This field must be configured when WUPEN6 = 0. uint32_t wusel7 : 2; // 12 Wakeup pin WKUP7 selection This field must be configured when WUPEN7 = 0. uint32_t wusel8 : 2; // 14 Wakeup pin WKUP8 selection This field must be configured when WUPEN8 = 0. uint32_t reserve0 : 16; // 16 Reserve } reg_pwr_wucr3_t; typedef struct { uint32_t bren : 1; // 0 Backup RAM retention in Standby and VBAT modes When this bit is set, the backup RAM content is kept in Standby and VBAT modes. If BREN is reset, the backup RAM can still be used in Run, Sleep and Stop modes. However, its content is lost in Standby, Shutdown and VBAT modes. This bit can be written only when the regulator is LDO, which must be configured before switching to SMPS. Note: Backup RAM cannot be preserved in Shutdown mode. uint32_t reserve0 : 3; // 1 Reserve uint32_t monen : 1; // 4 Backup domain voltage and temperature monitoring enable uint32_t reserve1 : 27; // 5 Reserve } reg_pwr_bdcr1_t; typedef struct { uint32_t vbe : 1; // 0 VBAT charging enable uint32_t vbrs : 1; // 1 VBAT charging resistor selection uint32_t reserve0 : 30; // 2 Reserve } reg_pwr_bdcr2_t; typedef struct { uint32_t dbp : 1; // 0 Disable Backup domain write protection In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers. uint32_t reserve0 : 31; // 1 Reserve } reg_pwr_dbpr_t; typedef struct { uint32_t ucpd_dbdis: 1; // 0 UCPD dead battery disable After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to handover control to the UCPD (the UCPD must be initialized before doing the disable). uint32_t ucpd_stby : 1; // 1 UCPD Standby mode When set, this bit is used to memorize the UCPD configuration in Standby mode. This bit must be written to 1 just before entering Standby mode when using UCPD. It must be written to 0 after exiting the Standby mode and before writing any UCPD registers. uint32_t reserve0 : 30; // 2 Reserve } reg_pwr_ucpdr_t; typedef struct { uint32_t wup1sec : 1; // 0 WUP1 secure protection uint32_t wup2sec : 1; // 1 WUP2 secure protection uint32_t wup3sec : 1; // 2 WUP3 secure protection uint32_t wup4sec : 1; // 3 WUP4 secure protection uint32_t wup5sec : 1; // 4 WUP5 secure protection uint32_t wup6sec : 1; // 5 WUP6 secure protection uint32_t wup7sec : 1; // 6 WUP7 secure protection uint32_t wup8sec : 1; // 7 WUP8 secure protection uint32_t reserve0 : 4; // 8 Reserve uint32_t lpmsec : 1; // 12 Low-power modes secure protection uint32_t vdmsec : 1; // 13 Voltage detection and monitoring secure protection uint32_t vbsec : 1; // 14 Backup domain secure protection uint32_t apcsec : 1; // 15 Pull-up/pull-down secure protection uint32_t reserve1 : 16; // 16 Reserve } reg_pwr_seccfgr_t; typedef struct { uint32_t spriv : 1; // 0 PWR secure functions privilege configuration This bit is set and reset by software. It can be written only by a secure privileged access. uint32_t nspriv : 1; // 1 PWR non-secure functions privilege configuration This bit is set and reset by software. It can be written only by privileged access, secure or non-secure. uint32_t reserve0 : 30; // 2 Reserve } reg_pwr_privcfgr_t; typedef struct { uint32_t cssf : 1; // 0 Clear Stop and Standby flags This bit is protected against non-secure access when LPMSEC = 1 in PWR_SECCFGR. This bit is protected against unprivileged access when LPMSEC = 1 and SPRIV = 1 in PWR_PRIVCFGR, or when LPMSEC = 0 and NSPRIV = 1. Writing 1 to this bit clears the STOPF and SBF flags. uint32_t stopf : 1; // 1 Stop flag This bit is set by hardware when the device enters a Stop mode, and is cleared by software by writing 1 to the CSSF bit. uint32_t sbf : 1; // 2 Standby flag This bit is set by hardware when the device enters the Standby mode, and is cleared by writing 1 to the CSSF bit, or by a power-on reset. It is not cleared by the system reset. uint32_t reserve0 : 29; // 3 Reserve } reg_pwr_sr_t; typedef struct { uint32_t reserve0 : 1; // 0 Reserve uint32_t regs : 1; // 1 Regulator selection uint32_t reserve1 : 2; // 2 Reserve uint32_t pvdo : 1; // 4 VDD voltage detector output uint32_t reserve2 : 10; // 5 Reserve uint32_t actvosrdy : 1; // 15 Voltage level ready for currently used VOS uint32_t actvos : 2; // 16 VOS currently applied to VCORE This field provides the last VOS value. uint32_t reserve3 : 6; // 18 Reserve uint32_t vddusbrdy : 1; // 24 VDDUSB ready uint32_t vddio2rdy : 1; // 25 VDDIO2 ready uint32_t vdda1rdy : 1; // 26 VDDA ready versus 1.6V voltage monitor uint32_t vdda2rdy : 1; // 27 VDDA ready versus 1.8 V voltage monitor uint32_t reserve4 : 4; // 28 Reserve } reg_pwr_svmsr_t; typedef struct { uint32_t reserve0 : 1; // 0 Reserve uint32_t vbath : 1; // 1 Backup domain voltage level monitoring versus high threshold uint32_t templ : 1; // 2 Temperature level monitoring versus low threshold uint32_t temph : 1; // 3 Temperature level monitoring versus high threshold uint32_t reserve1 : 28; // 4 Reserve } reg_pwr_bdsr_t; typedef struct { uint32_t wuf1 : 1; // 0 Wakeup flag 1 This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN1 = 0. uint32_t wuf2 : 1; // 1 Wakeup flag 2 This bit is set when a wakeup event is detected on WKUP2 pin. This bit is cleared by writing 1 in the CWUF2 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN2 = 0. uint32_t wuf3 : 1; // 2 Wakeup flag 3 This bit is set when a wakeup event is detected on WKUP3 pin. This bit is cleared by writing 1 in the CWUF3 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN3 = 0. uint32_t wuf4 : 1; // 3 Wakeup flag 4 This bit is set when a wakeup event is detected on WKUP4 pin. This bit is cleared by writing 1 in the CWUF4 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN4 = 0. uint32_t wuf5 : 1; // 4 Wakeup flag 5 This bit is set when a wakeup event is detected on WKUP5 pin. This bit is cleared by writing 1 in the CWUF5 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN5 = 0. uint32_t wuf6 : 1; // 5 Wakeup flag 6 This bit is set when a wakeup event is detected on WKUP6 pin. This bit is cleared by writing 1 in the CWUF6 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN6 = 0. If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared. uint32_t wuf7 : 1; // 6 Wakeup flag 7 This bit is set when a wakeup event is detected on WKUP7 pin. This bit is cleared by writing 1 in the CWUF7 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN7 = 0. If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared. uint32_t wuf8 : 1; // 7 Wakeup flag 8 This bit is set when a wakeup event is detected on WKUP8 pin. This bit is cleared by writing 1 in the CWUF8 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN8 = 0. If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared. uint32_t reserve0 : 24; // 8 Reserve } reg_pwr_wusr_t; typedef struct { uint32_t cwuf1 : 1; // 0 Wakeup flag 1 Writing 1 to this bit clears the WUF1 flag in PWR_WUSR. uint32_t cwuf2 : 1; // 1 Wakeup flag 2 Writing 1 to this bit clears the WUF2 flag in PWR_WUSR. uint32_t cwuf3 : 1; // 2 Wakeup flag 3 Writing 1 to this bit clears the WUF3 flag in PWR_WUSR. uint32_t cwuf4 : 1; // 3 Wakeup flag 4 Writing 1 to this bit clears the WUF4 flag in PWR_WUSR. uint32_t cwuf5 : 1; // 4 Wakeup flag 5 Writing 1 to this bit clears the WUF5 flag in PWR_WUSR. uint32_t cwuf6 : 1; // 5 Wakeup flag 6 Writing 1 to this bit clears the WUF6 flag in PWR_WUSR. uint32_t cwuf7 : 1; // 6 Wakeup flag 7 Writing 1 to this bit clears the WUF7 flag in PWR_WUSR. uint32_t cwuf8 : 1; // 7 Wakeup flag 8 Writing 1 to this bit clears the WUF8 flag in PWR_WUSR. uint32_t reserve0 : 24; // 8 Reserve } reg_pwr_wuscr_t; typedef struct { uint32_t apc : 1; // 0 Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in PWR_PUCRx and PWR_PDCRx are applied. When this bit is cleared, PWR_PUCRx and PWR_PDCRx are not applied to the I/Os. uint32_t reserve0 : 31; // 1 Reserve } reg_pwr_apcr_t; typedef struct { uint32_t pu0 : 1; // 0 Port A pull-up bit uint32_t pu1 : 1; // 1 Port A pull-up bit uint32_t pu2 : 1; // 2 Port A pull-up bit uint32_t pu3 : 1; // 3 Port A pull-up bit uint32_t pu4 : 1; // 4 Port A pull-up bit uint32_t pu5 : 1; // 5 Port A pull-up bit uint32_t pu6 : 1; // 6 Port A pull-up bit uint32_t pu7 : 1; // 7 Port A pull-up bit uint32_t pu8 : 1; // 8 Port A pull-up bit uint32_t pu9 : 1; // 9 Port A pull-up bit uint32_t pu10 : 1; // 10 Port A pull-up bit uint32_t pu11 : 1; // 11 Port A pull-up bit uint32_t pu12 : 1; // 12 Port A pull-up bit uint32_t pu13 : 1; // 13 Port A pull-up bit uint32_t reserve0 : 1; // 14 Reserve uint32_t pu15 : 1; // 15 Port A pull-up bit 15 When set, this bit activates the pull-up on PA15 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PD15 bit is also set. uint32_t reserve1 : 16; // 16 Reserve } reg_pwr_pucra_t; typedef struct { uint32_t pd0 : 1; // 0 Port A pull-down bit uint32_t pd1 : 1; // 1 Port A pull-down bit uint32_t pd2 : 1; // 2 Port A pull-down bit uint32_t pd3 : 1; // 3 Port A pull-down bit uint32_t pd4 : 1; // 4 Port A pull-down bit uint32_t pd5 : 1; // 5 Port A pull-down bit uint32_t pd6 : 1; // 6 Port A pull-down bit uint32_t pd7 : 1; // 7 Port A pull-down bit uint32_t pd8 : 1; // 8 Port A pull-down bit uint32_t pd9 : 1; // 9 Port A pull-down bit uint32_t pd10 : 1; // 10 Port A pull-down bit uint32_t pd11 : 1; // 11 Port A pull-down bit uint32_t pd12 : 1; // 12 Port A pull-down bit uint32_t reserve0 : 1; // 13 Reserve uint32_t pd14 : 1; // 14 Port A pull-down bit uint32_t reserve1 : 17; // 15 Reserve } reg_pwr_pdcra_t; typedef struct { uint32_t pu0 : 1; // 0 Port B pull-up bit uint32_t pu1 : 1; // 1 Port B pull-up bit uint32_t pu2 : 1; // 2 Port B pull-up bit uint32_t pu3 : 1; // 3 Port B pull-up bit uint32_t pu4 : 1; // 4 Port B pull-up bit uint32_t pu5 : 1; // 5 Port B pull-up bit uint32_t pu6 : 1; // 6 Port B pull-up bit uint32_t pu7 : 1; // 7 Port B pull-up bit uint32_t pu8 : 1; // 8 Port B pull-up bit uint32_t pu9 : 1; // 9 Port B pull-up bit uint32_t pu10 : 1; // 10 Port B pull-up bit uint32_t pu11 : 1; // 11 Port B pull-up bit uint32_t pu12 : 1; // 12 Port B pull-up bit uint32_t pu13 : 1; // 13 Port B pull-up bit uint32_t pu14 : 1; // 14 Port B pull-up bit uint32_t pu15 : 1; // 15 Port B pull-up bit uint32_t reserve0 : 16; // 16 Reserve } reg_pwr_pucrb_t; typedef struct { uint32_t pd0 : 1; // 0 Port B pull-down bit uint32_t pd1 : 1; // 1 Port B pull-down bit uint32_t pd2 : 1; // 2 Port B pull-down bit uint32_t pd3 : 1; // 3 Port B pull-down bit uint32_t reserve0 : 1; // 4 Reserve uint32_t pd5 : 1; // 5 Port B pull-down bit uint32_t pd6 : 1; // 6 Port B pull-down bit uint32_t pd7 : 1; // 7 Port B pull-down bit uint32_t pd8 : 1; // 8 Port B pull-down bit uint32_t pd9 : 1; // 9 Port B pull-down bit uint32_t pd10 : 1; // 10 Port B pull-down bit uint32_t pd11 : 1; // 11 Port B pull-down bit uint32_t pd12 : 1; // 12 Port B pull-down bit uint32_t pd13 : 1; // 13 Port B pull-down bit uint32_t pd14 : 1; // 14 Port B pull-down bit uint32_t pd15 : 1; // 15 Port B pull-down bit uint32_t reserve1 : 16; // 16 Reserve } reg_pwr_pdcrb_t; typedef struct { uint32_t pu0 : 1; // 0 Port C pull-up bit uint32_t pu1 : 1; // 1 Port C pull-up bit uint32_t pu2 : 1; // 2 Port C pull-up bit uint32_t pu3 : 1; // 3 Port C pull-up bit uint32_t pu4 : 1; // 4 Port C pull-up bit uint32_t pu5 : 1; // 5 Port C pull-up bit uint32_t pu6 : 1; // 6 Port C pull-up bit uint32_t pu7 : 1; // 7 Port C pull-up bit uint32_t pu8 : 1; // 8 Port C pull-up bit uint32_t pu9 : 1; // 9 Port C pull-up bit uint32_t pu10 : 1; // 10 Port C pull-up bit uint32_t pu11 : 1; // 11 Port C pull-up bit uint32_t pu12 : 1; // 12 Port C pull-up bit uint32_t pu13 : 1; // 13 Port C pull-up bit uint32_t pu14 : 1; // 14 Port C pull-up bit uint32_t pu15 : 1; // 15 Port C pull-up bit uint32_t reserve0 : 16; // 16 Reserve } reg_pwr_pucrc_t; typedef struct { uint32_t pd0 : 1; // 0 Port C pull-down bit uint32_t pd1 : 1; // 1 Port C pull-down bit uint32_t pd2 : 1; // 2 Port C pull-down bit uint32_t pd3 : 1; // 3 Port C pull-down bit uint32_t pd4 : 1; // 4 Port C pull-down bit uint32_t pd5 : 1; // 5 Port C pull-down bit uint32_t pd6 : 1; // 6 Port C pull-down bit uint32_t pd7 : 1; // 7 Port C pull-down bit uint32_t pd8 : 1; // 8 Port C pull-down bit uint32_t pd9 : 1; // 9 Port C pull-down bit uint32_t pd10 : 1; // 10 Port C pull-down bit uint32_t pd11 : 1; // 11 Port C pull-down bit uint32_t pd12 : 1; // 12 Port C pull-down bit uint32_t pd13 : 1; // 13 Port C pull-down bit uint32_t pd14 : 1; // 14 Port C pull-down bit uint32_t pd15 : 1; // 15 Port C pull-down bit uint32_t reserve0 : 16; // 16 Reserve } reg_pwr_pdcrc_t; typedef struct { uint32_t pu0 : 1; // 0 Port D pull-up bit uint32_t pu1 : 1; // 1 Port D pull-up bit uint32_t pu2 : 1; // 2 Port D pull-up bit uint32_t pu3 : 1; // 3 Port D pull-up bit uint32_t pu4 : 1; // 4 Port D pull-up bit uint32_t pu5 : 1; // 5 Port D pull-up bit uint32_t pu6 : 1; // 6 Port D pull-up bit uint32_t pu7 : 1; // 7 Port D pull-up bit uint32_t pu8 : 1; // 8 Port D pull-up bit uint32_t pu9 : 1; // 9 Port D pull-up bit uint32_t pu10 : 1; // 10 Port D pull-up bit uint32_t pu11 : 1; // 11 Port D pull-up bit uint32_t pu12 : 1; // 12 Port D pull-up bit uint32_t pu13 : 1; // 13 Port D pull-up bit uint32_t pu14 : 1; // 14 Port D pull-up bit uint32_t pu15 : 1; // 15 Port D pull-up bit uint32_t reserve0 : 16; // 16 Reserve } reg_pwr_pucrd_t; typedef struct { uint32_t pd0 : 1; // 0 Port D pull-down bit uint32_t pd1 : 1; // 1 Port D pull-down bit uint32_t pd2 : 1; // 2 Port D pull-down bit uint32_t pd3 : 1; // 3 Port D pull-down bit uint32_t pd4 : 1; // 4 Port D pull-down bit uint32_t pd5 : 1; // 5 Port D pull-down bit uint32_t pd6 : 1; // 6 Port D pull-down bit uint32_t pd7 : 1; // 7 Port D pull-down bit uint32_t pd8 : 1; // 8 Port D pull-down bit uint32_t pd9 : 1; // 9 Port D pull-down bit uint32_t pd10 : 1; // 10 Port D pull-down bit uint32_t pd11 : 1; // 11 Port D pull-down bit uint32_t pd12 : 1; // 12 Port D pull-down bit uint32_t pd13 : 1; // 13 Port D pull-down bit uint32_t pd14 : 1; // 14 Port D pull-down bit uint32_t pd15 : 1; // 15 Port D pull-down bit uint32_t reserve0 : 16; // 16 Reserve } reg_pwr_pdcrd_t; typedef struct { uint32_t pu0 : 1; // 0 Port E pull-up bit uint32_t pu1 : 1; // 1 Port E pull-up bit uint32_t pu2 : 1; // 2 Port E pull-up bit uint32_t pu3 : 1; // 3 Port E pull-up bit uint32_t pu4 : 1; // 4 Port E pull-up bit uint32_t pu5 : 1; // 5 Port E pull-up bit uint32_t pu6 : 1; // 6 Port E pull-up bit uint32_t pu7 : 1; // 7 Port E pull-up bit uint32_t pu8 : 1; // 8 Port E pull-up bit uint32_t pu9 : 1; // 9 Port E pull-up bit uint32_t pu10 : 1; // 10 Port E pull-up bit uint32_t pu11 : 1; // 11 Port E pull-up bit uint32_t pu12 : 1; // 12 Port E pull-up bit uint32_t pu13 : 1; // 13 Port E pull-up bit uint32_t pu14 : 1; // 14 Port E pull-up bit uint32_t pu15 : 1; // 15 Port E pull-up bit uint32_t reserve0 : 16; // 16 Reserve } reg_pwr_pucre_t; typedef struct { uint32_t pd0 : 1; // 0 Port E pull-down bit uint32_t pd1 : 1; // 1 Port E pull-down bit uint32_t pd2 : 1; // 2 Port E pull-down bit uint32_t pd3 : 1; // 3 Port E pull-down bit uint32_t pd4 : 1; // 4 Port E pull-down bit uint32_t pd5 : 1; // 5 Port E pull-down bit uint32_t pd6 : 1; // 6 Port E pull-down bit uint32_t pd7 : 1; // 7 Port E pull-down bit uint32_t pd8 : 1; // 8 Port E pull-down bit uint32_t pd9 : 1; // 9 Port E pull-down bit uint32_t pd10 : 1; // 10 Port E pull-down bit uint32_t pd11 : 1; // 11 Port E pull-down bit uint32_t pd12 : 1; // 12 Port E pull-down bit uint32_t pd13 : 1; // 13 Port E pull-down bit uint32_t pd14 : 1; // 14 Port E pull-down bit uint32_t pd15 : 1; // 15 Port E pull-down bit uint32_t reserve0 : 16; // 16 Reserve } reg_pwr_pdcre_t; typedef struct { uint32_t pu0 : 1; // 0 Port F pull-up bit uint32_t pu1 : 1; // 1 Port F pull-up bit uint32_t pu2 : 1; // 2 Port F pull-up bit uint32_t pu3 : 1; // 3 Port F pull-up bit uint32_t pu4 : 1; // 4 Port F pull-up bit uint32_t pu5 : 1; // 5 Port F pull-up bit uint32_t pu6 : 1; // 6 Port F pull-up bit uint32_t pu7 : 1; // 7 Port F pull-up bit uint32_t pu8 : 1; // 8 Port F pull-up bit uint32_t pu9 : 1; // 9 Port F pull-up bit uint32_t pu10 : 1; // 10 Port F pull-up bit uint32_t pu11 : 1; // 11 Port F pull-up bit uint32_t pu12 : 1; // 12 Port F pull-up bit uint32_t pu13 : 1; // 13 Port F pull-up bit uint32_t pu14 : 1; // 14 Port F pull-up bit uint32_t pu15 : 1; // 15 Port F pull-up bit uint32_t reserve0 : 16; // 16 Reserve } reg_pwr_pucrf_t; typedef struct { uint32_t pd0 : 1; // 0 Port F pull-down bit uint32_t pd1 : 1; // 1 Port F pull-down bit uint32_t pd2 : 1; // 2 Port F pull-down bit uint32_t pd3 : 1; // 3 Port F pull-down bit uint32_t pd4 : 1; // 4 Port F pull-down bit uint32_t pd5 : 1; // 5 Port F pull-down bit uint32_t pd6 : 1; // 6 Port F pull-down bit uint32_t pd7 : 1; // 7 Port F pull-down bit uint32_t pd8 : 1; // 8 Port F pull-down bit uint32_t pd9 : 1; // 9 Port F pull-down bit uint32_t pd10 : 1; // 10 Port F pull-down bit uint32_t pd11 : 1; // 11 Port F pull-down bit uint32_t pd12 : 1; // 12 Port F pull-down bit uint32_t pd13 : 1; // 13 Port F pull-down bit uint32_t pd14 : 1; // 14 Port F pull-down bit uint32_t pd15 : 1; // 15 Port F pull-down bit uint32_t reserve0 : 16; // 16 Reserve } reg_pwr_pdcrf_t; typedef struct { uint32_t pu0 : 1; // 0 Port G pull-up bit uint32_t pu1 : 1; // 1 Port G pull-up bit uint32_t pu2 : 1; // 2 Port G pull-up bit uint32_t pu3 : 1; // 3 Port G pull-up bit uint32_t pu4 : 1; // 4 Port G pull-up bit uint32_t pu5 : 1; // 5 Port G pull-up bit uint32_t pu6 : 1; // 6 Port G pull-up bit uint32_t pu7 : 1; // 7 Port G pull-up bit uint32_t pu8 : 1; // 8 Port G pull-up bit uint32_t pu9 : 1; // 9 Port G pull-up bit uint32_t pu10 : 1; // 10 Port G pull-up bit uint32_t pu11 : 1; // 11 Port G pull-up bit uint32_t pu12 : 1; // 12 Port G pull-up bit uint32_t pu13 : 1; // 13 Port G pull-up bit uint32_t pu14 : 1; // 14 Port G pull-up bit uint32_t pu15 : 1; // 15 Port G pull-up bit uint32_t reserve0 : 16; // 16 Reserve } reg_pwr_pucrg_t; typedef struct { uint32_t pd0 : 1; // 0 Port G pull-down bit uint32_t pd1 : 1; // 1 Port G pull-down bit uint32_t pd2 : 1; // 2 Port G pull-down bit uint32_t pd3 : 1; // 3 Port G pull-down bit uint32_t pd4 : 1; // 4 Port G pull-down bit uint32_t pd5 : 1; // 5 Port G pull-down bit uint32_t pd6 : 1; // 6 Port G pull-down bit uint32_t pd7 : 1; // 7 Port G pull-down bit uint32_t pd8 : 1; // 8 Port G pull-down bit uint32_t pd9 : 1; // 9 Port G pull-down bit uint32_t pd10 : 1; // 10 Port G pull-down bit uint32_t pd11 : 1; // 11 Port G pull-down bit uint32_t pd12 : 1; // 12 Port G pull-down bit uint32_t pd13 : 1; // 13 Port G pull-down bit uint32_t pd14 : 1; // 14 Port G pull-down bit uint32_t pd15 : 1; // 15 Port G pull-down bit uint32_t reserve0 : 16; // 16 Reserve } reg_pwr_pdcrg_t; typedef struct { uint32_t pu0 : 1; // 0 Port H pull-up bit uint32_t pu1 : 1; // 1 Port H pull-up bit uint32_t pu2 : 1; // 2 Port H pull-up bit uint32_t pu3 : 1; // 3 Port H pull-up bit uint32_t pu4 : 1; // 4 Port H pull-up bit uint32_t pu5 : 1; // 5 Port H pull-up bit uint32_t pu6 : 1; // 6 Port H pull-up bit uint32_t pu7 : 1; // 7 Port H pull-up bit uint32_t pu8 : 1; // 8 Port H pull-up bit uint32_t pu9 : 1; // 9 Port H pull-up bit uint32_t pu10 : 1; // 10 Port H pull-up bit uint32_t pu11 : 1; // 11 Port H pull-up bit uint32_t pu12 : 1; // 12 Port H pull-up bit uint32_t pu13 : 1; // 13 Port H pull-up bit uint32_t pu14 : 1; // 14 Port H pull-up bit uint32_t pu15 : 1; // 15 Port H pull-up bit uint32_t reserve0 : 16; // 16 Reserve } reg_pwr_pucrh_t; typedef struct { uint32_t pd0 : 1; // 0 Port H pull-down bit uint32_t pd1 : 1; // 1 Port H pull-down bit uint32_t pd2 : 1; // 2 Port H pull-down bit uint32_t pd3 : 1; // 3 Port H pull-down bit uint32_t pd4 : 1; // 4 Port H pull-down bit uint32_t pd5 : 1; // 5 Port H pull-down bit uint32_t pd6 : 1; // 6 Port H pull-down bit uint32_t pd7 : 1; // 7 Port H pull-down bit uint32_t pd8 : 1; // 8 Port H pull-down bit uint32_t pd9 : 1; // 9 Port H pull-down bit uint32_t pd10 : 1; // 10 Port H pull-down bit uint32_t pd11 : 1; // 11 Port H pull-down bit uint32_t pd12 : 1; // 12 Port H pull-down bit uint32_t pd13 : 1; // 13 Port H pull-down bit uint32_t pd14 : 1; // 14 Port H pull-down bit uint32_t pd15 : 1; // 15 Port H pull-down bit uint32_t reserve0 : 16; // 16 Reserve } reg_pwr_pdcrh_t; typedef struct { uint32_t pu0 : 1; // 0 Port I pull-up bit uint32_t pu1 : 1; // 1 Port I pull-up bit uint32_t pu2 : 1; // 2 Port I pull-up bit uint32_t pu3 : 1; // 3 Port I pull-up bit uint32_t pu4 : 1; // 4 Port I pull-up bit uint32_t pu5 : 1; // 5 Port I pull-up bit uint32_t pu6 : 1; // 6 Port I pull-up bit uint32_t pu7 : 1; // 7 Port I pull-up bit uint32_t reserve0 : 24; // 8 Reserve } reg_pwr_pucri_t; typedef struct { uint32_t pd0 : 1; // 0 Port I pull-down bit uint32_t pd1 : 1; // 1 Port I pull-down bit uint32_t pd2 : 1; // 2 Port I pull-down bit uint32_t pd3 : 1; // 3 Port I pull-down bit uint32_t pd4 : 1; // 4 Port I pull-down bit uint32_t pd5 : 1; // 5 Port I pull-down bit uint32_t pd6 : 1; // 6 Port I pull-down bit uint32_t pd7 : 1; // 7 Port I pull-down bit uint32_t reserve0 : 24; // 8 Reserve } reg_pwr_pdcri_t; typedef struct { volatile reg_pwr_cr1_t cr1; volatile reg_pwr_cr2_t cr2; volatile reg_pwr_cr3_t cr3; volatile reg_pwr_vosr_t vosr; volatile reg_pwr_svmcr_t svmcr; volatile reg_pwr_wucr1_t wucr1; volatile reg_pwr_wucr2_t wucr2; volatile reg_pwr_wucr3_t wucr3; volatile reg_pwr_bdcr1_t bdcr1; volatile reg_pwr_bdcr2_t bdcr2; volatile reg_pwr_dbpr_t dbpr; volatile reg_pwr_ucpdr_t ucpdr; volatile reg_pwr_seccfgr_t seccfgr; volatile reg_pwr_privcfgr_t privcfgr; volatile reg_pwr_sr_t sr; volatile reg_pwr_svmsr_t svmsr; volatile reg_pwr_bdsr_t bdsr; volatile reg_pwr_wusr_t wusr; volatile reg_pwr_wuscr_t wuscr; volatile reg_pwr_apcr_t apcr; volatile reg_pwr_pucra_t pucra; volatile reg_pwr_pdcra_t pdcra; volatile reg_pwr_pucrb_t pucrb; volatile reg_pwr_pdcrb_t pdcrb; volatile reg_pwr_pucrc_t pucrc; volatile reg_pwr_pdcrc_t pdcrc; volatile reg_pwr_pucrd_t pucrd; volatile reg_pwr_pdcrd_t pdcrd; volatile reg_pwr_pucre_t pucre; volatile reg_pwr_pdcre_t pdcre; volatile reg_pwr_pucrf_t pucrf; volatile reg_pwr_pdcrf_t pdcrf; volatile reg_pwr_pucrg_t pucrg; volatile reg_pwr_pdcrg_t pdcrg; volatile reg_pwr_pucrh_t pucrh; volatile reg_pwr_pdcrh_t pdcrh; volatile reg_pwr_pucri_t pucri; volatile reg_pwr_pdcri_t pdcri; } reg_pwr_t;