#include typedef struct { uint32_t lck : 1; // 0 lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx registers until next reset uint32_t reserve0 : 31; // 1 Reserve } reg_gtzc2_tzsc_tzsc_cr_t; typedef struct { uint32_t spi3sec : 1; // 0 secure access mode for SPI3 uint32_t lpuart1sec: 1; // 1 secure access mode for LPUART1 uint32_t i2c3sec : 1; // 2 secure access mode for I2C3 uint32_t lptim1sec : 1; // 3 secure access mode for LPTIM1 uint32_t lptim3sec : 1; // 4 secure access mode for LPTIM3 uint32_t lptim4sec : 1; // 5 secure access mode for LPTIM4 uint32_t opampsec : 1; // 6 secure access mode for OPAMP uint32_t compsec : 1; // 7 secure access mode for COMP uint32_t adc4sec : 1; // 8 secure access mode for ADC4 uint32_t vrefbufsec: 1; // 9 secure access mode for VREFBUF uint32_t reserve0 : 1; // 10 Reserve uint32_t dac1sec : 1; // 11 secure access mode for DAC1 uint32_t adf1sec : 1; // 12 secure access mode for ADF1 uint32_t reserve1 : 19; // 13 Reserve } reg_gtzc2_tzsc_tzsc_seccfgr1_t; typedef struct { uint32_t spi3priv : 1; // 0 privileged access mode for SPI3 uint32_t lpuart1priv: 1; // 1 privileged access mode for LPUART1 uint32_t i2c3priv : 1; // 2 privileged access mode for I2C3 uint32_t lptim1priv: 1; // 3 privileged access mode for LPTIM1 uint32_t lptim3priv: 1; // 4 privileged access mode for LPTIM3 uint32_t lptim4priv: 1; // 5 privileged access mode for LPTIM4 uint32_t opamppriv : 1; // 6 privileged access mode for OPAMP uint32_t comppriv : 1; // 7 privileged access mode for COMP uint32_t adc4priv : 1; // 8 privileged access mode for ADC4 uint32_t vrefbufpriv: 1; // 9 privileged access mode for VREFBUF uint32_t reserve0 : 1; // 10 Reserve uint32_t dac1priv : 1; // 11 privileged access mode for DAC1 uint32_t adf1priv : 1; // 12 privileged access mode for ADF1 uint32_t reserve1 : 19; // 13 Reserve } reg_gtzc2_tzsc_tzsc_privcfgr1_t; typedef struct { volatile reg_gtzc2_tzsc_tzsc_cr_t tzsc_cr; volatile uint32_t reserve0[3]; volatile reg_gtzc2_tzsc_tzsc_seccfgr1_t tzsc_seccfgr1; volatile uint32_t reserve1[3]; volatile reg_gtzc2_tzsc_tzsc_privcfgr1_t tzsc_privcfgr1; } reg_gtzc2_tzsc_t;