#include typedef struct { uint32_t dev_id : 12; // 0 Device dentification uint32_t reserve0 : 4; // 12 Reserve uint32_t rev_id : 16; // 16 Revision } reg_dbgmcu_idcode_t; typedef struct { uint32_t reserve0 : 1; // 0 Reserve uint32_t dbg_stop : 1; // 1 Debug Stop mode uint32_t dbg_standby: 1; // 2 Debug Standby mode uint32_t reserve1 : 1; // 3 Reserve uint32_t trace_ioen: 1; // 4 Trace pin assignment control uint32_t trace_en : 1; // 5 trace port and clock enable uint32_t trace_mode: 2; // 6 Trace pin assignment control uint32_t reserve2 : 24; // 8 Reserve } reg_dbgmcu_cr_t; typedef struct { uint32_t dbg_tim2_stop: 1; // 0 TIM2 stop in debug uint32_t dbg_tim3_stop: 1; // 1 TIM3 stop in debug uint32_t dbg_tim4_stop: 1; // 2 TIM4 stop in debug uint32_t dbg_tim5_stop: 1; // 3 TIM5 stop in debug uint32_t dbg_tim6_stop: 1; // 4 TIM6 stop in debug uint32_t dbg_tim7_stop: 1; // 5 TIM7 stop in debug uint32_t reserve0 : 5; // 6 Reserve uint32_t dbg_wwdg_stop: 1; // 11 Window watchdog counter stop in debug uint32_t dbg_iwdg_stop: 1; // 12 Independent watchdog counter stop in debug uint32_t reserve1 : 8; // 13 Reserve uint32_t dbg_i2c1_stop: 1; // 21 I2C1 SMBUS timeout stop in debug uint32_t dbg_i2c2_stop: 1; // 22 I2C2 SMBUS timeout stop in debug uint32_t reserve2 : 9; // 23 Reserve } reg_dbgmcu_apb1lfzr_t; typedef struct { uint32_t reserve0 : 1; // 0 Reserve uint32_t dbg_i2c4_stop: 1; // 1 I2C4 stop in debug uint32_t reserve1 : 3; // 2 Reserve uint32_t dbg_lptim2_stop: 1; // 5 LPTIM2 stop in debug uint32_t reserve2 : 26; // 6 Reserve } reg_dbgmcu_apb1hfzr_t; typedef struct { uint32_t reserve0 : 11; // 0 Reserve uint32_t dbg_tim1_stop: 1; // 11 TIM1 counter stopped when core is halted uint32_t reserve1 : 1; // 12 Reserve uint32_t dbg_tim8_stop: 1; // 13 TIM8 stop in debug uint32_t reserve2 : 2; // 14 Reserve uint32_t dbg_tim15_stop: 1; // 16 TIM15 counter stopped when core is halted uint32_t dbg_tim16_stop: 1; // 17 TIM16 counter stopped when core is halted uint32_t dbg_tim17_stop: 1; // 18 DBG_TIM17_STOP uint32_t reserve3 : 13; // 19 Reserve } reg_dbgmcu_apb2fzr_t; typedef struct { uint32_t reserve0 : 10; // 0 Reserve uint32_t dbg_i2c3_stop: 1; // 10 I2C3 stop in debug uint32_t reserve1 : 6; // 11 Reserve uint32_t dbg_lptim1_stop: 1; // 17 LPTIM1 stop in debug uint32_t dbg_lptim3_stop: 1; // 18 LPTIM3 stop in debug uint32_t dbg_lptim4_stop: 1; // 19 LPTIM4 stop in debug uint32_t reserve2 : 10; // 20 Reserve uint32_t dbg_rtc_stop: 1; // 30 RTC stop in debug uint32_t reserve3 : 1; // 31 Reserve } reg_dbgmcu_apb3fzr_t; typedef struct { uint32_t dbg_gpdma0_stop: 1; // 0 GPDMA channel 0 stop in debug uint32_t dbg_gpdma1_stop: 1; // 1 GPDMA channel 1 stop in debug uint32_t dbg_gpdma2_stop: 1; // 2 GPDMA channel 2 stop in debug uint32_t dbg_gpdma3_stop: 1; // 3 GPDMA channel 3 stop in debug uint32_t dbg_gpdma4_stop: 1; // 4 GPDMA channel 4 stop in debug uint32_t dbg_gpdma5_stop: 1; // 5 GPDMA channel 5 stop in debug uint32_t dbg_gpdma6_stop: 1; // 6 GPDMA channel 6 stop in debug uint32_t dbg_gpdma7_stop: 1; // 7 GPDMA channel 7 stop in debug uint32_t dbg_gpdma8_stop: 1; // 8 GPDMA channel 8 stop in debug uint32_t dbg_gpdma9_stop: 1; // 9 GPDMA channel 9 stop in debug uint32_t dbg_gpdma10_stop: 1; // 10 GPDMA channel 10 stop in debug uint32_t dbg_gpdma11_stop: 1; // 11 GPDMA channel 11 stop in debug uint32_t dbg_gpdma12_stop: 1; // 12 GPDMA channel 12 stop in debug uint32_t dbg_gpdma13_stop: 1; // 13 GPDMA channel 13 stop in debug uint32_t dbg_gpdma14_stop: 1; // 14 GPDMA channel 14 stop in debug uint32_t dbg_gpdma15_stop: 1; // 15 GPDMA channel 15 stop in debug uint32_t reserve0 : 16; // 16 Reserve } reg_dbgmcu_ahb1fzr_t; typedef struct { uint32_t dbg_lpdma0_stop: 1; // 0 LPDMA channel 0 stop in debug uint32_t dbg_lpdma1_stop: 1; // 1 LPDMA channel 1 stop in debug uint32_t dbg_lpdma2_stop: 1; // 2 LPDMA channel 2 stop in debug uint32_t dbg_lpdma3_stop: 1; // 3 LPDMA channel 3 stop in debug uint32_t reserve0 : 28; // 4 Reserve } reg_dbgmcu_ahb3fzr_t; typedef struct { uint32_t ap_present: 8; // 0 Bit n identifies whether access port AP n is present in device Bit n = 0: APn absent Bit n = 1: APn present uint32_t ap_locked : 8; // 8 DECLARATION TO BE CONFIRMED by PRODUCT OWNER! Bit n identifies whether access port AP n is open (can be accessed via the debug port) or locked (debug access to the AP is blocked) Bit n = 0: APn locked Bit n = 1: APn enabled uint32_t reserve0 : 16; // 16 Reserve } reg_dbgmcu_sr_t; typedef struct { uint32_t auth_key : 32; // 0 Device authentication key The device specific 64-bit authentication key (OEM key) must be written to this register (in two successive 32-bit writes, least significant word first) to permit RDP regression. Writing a wrong key locks access to the device and prevent code execution from the Flash memory. } reg_dbgmcu_dbg_auth_host_t; typedef struct { uint32_t auth_id : 32; // 0 Device specific ID Device specific ID used for RDP regression. } reg_dbgmcu_dbg_auth_device_t; typedef struct { uint32_t jep106con : 4; // 0 JEP106 continuation code uint32_t kcount_4 : 4; // 4 register file size uint32_t reserve0 : 24; // 8 Reserve } reg_dbgmcu_pidr4_t; typedef struct { uint32_t partnum : 8; // 0 part number bits [7:0] uint32_t reserve0 : 24; // 8 Reserve } reg_dbgmcu_pidr0_t; typedef struct { uint32_t partnum : 4; // 0 part number bits [11:8] uint32_t jep106id : 4; // 4 JEP106 identity code bits [3:0] uint32_t reserve0 : 24; // 8 Reserve } reg_dbgmcu_pidr1_t; typedef struct { uint32_t jep106id : 3; // 0 JEP106 identity code bits [6:4] uint32_t jedec : 1; // 3 JEDEC assigned value uint32_t revision : 4; // 4 component revision number uint32_t reserve0 : 24; // 8 Reserve } reg_dbgmcu_pidr2_t; typedef struct { uint32_t cmod : 4; // 0 customer modified uint32_t revand : 4; // 4 metal fix version uint32_t reserve0 : 24; // 8 Reserve } reg_dbgmcu_pidr3_t; typedef struct { uint32_t preamble : 8; // 0 component identification bits [7:0] uint32_t reserve0 : 24; // 8 Reserve } reg_dbgmcu_cidr0_t; typedef struct { uint32_t preamble : 4; // 0 component identification bits [11:8] uint32_t class : 4; // 4 component identification bits [15:12] - component class uint32_t reserve0 : 24; // 8 Reserve } reg_dbgmcu_cidr1_t; typedef struct { uint32_t preamble : 8; // 0 component identification bits [23:16] uint32_t reserve0 : 24; // 8 Reserve } reg_dbgmcu_cidr2_t; typedef struct { uint32_t preamble : 8; // 0 component identification bits [31:24] uint32_t reserve0 : 24; // 8 Reserve } reg_dbgmcu_cidr3_t; typedef struct { volatile reg_dbgmcu_idcode_t idcode; volatile reg_dbgmcu_cr_t cr; volatile reg_dbgmcu_apb1lfzr_t apb1lfzr; volatile reg_dbgmcu_apb1hfzr_t apb1hfzr; volatile reg_dbgmcu_apb2fzr_t apb2fzr; volatile reg_dbgmcu_apb3fzr_t apb3fzr; volatile uint32_t reserve0[2]; volatile reg_dbgmcu_ahb1fzr_t ahb1fzr; volatile uint32_t reserve1[1]; volatile reg_dbgmcu_ahb3fzr_t ahb3fzr; volatile uint32_t reserve2[52]; volatile reg_dbgmcu_sr_t sr; volatile reg_dbgmcu_dbg_auth_host_t dbg_auth_host; volatile reg_dbgmcu_dbg_auth_device_t dbg_auth_device; volatile uint32_t reserve3[946]; volatile reg_dbgmcu_pidr4_t pidr4; volatile uint32_t reserve4[3]; volatile reg_dbgmcu_pidr0_t pidr0; volatile reg_dbgmcu_pidr1_t pidr1; volatile reg_dbgmcu_pidr2_t pidr2; volatile reg_dbgmcu_pidr3_t pidr3; volatile reg_dbgmcu_cidr0_t cidr0; volatile reg_dbgmcu_cidr1_t cidr1; volatile reg_dbgmcu_cidr2_t cidr2; volatile reg_dbgmcu_cidr3_t cidr3; } reg_dbgmcu_t;