1696 lines
38 KiB
YAML
1696 lines
38 KiB
YAML
---
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block/ADC1:
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description: Analog-to-Digital Converter
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items:
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- name: ISR
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description: interrupt and status register
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byte_offset: 0
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fieldset: ISR
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- name: IER
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description: interrupt enable register
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byte_offset: 4
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fieldset: IER
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- name: CR
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description: control register
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byte_offset: 8
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fieldset: CR
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- name: CFGR
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description: configuration register
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byte_offset: 12
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fieldset: CFGR
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- name: SMPR1
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description: sample time register 1
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byte_offset: 20
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fieldset: SMPR1
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- name: SMPR2
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description: sample time register 2
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byte_offset: 24
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fieldset: SMPR2
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- name: TR1
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description: watchdog threshold register 1
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byte_offset: 32
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fieldset: TR1
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- name: TR2
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description: watchdog threshold register
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byte_offset: 36
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fieldset: TR2
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- name: TR3
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description: watchdog threshold register 3
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byte_offset: 40
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fieldset: TR3
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- name: SQR1
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description: regular sequence register 1
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byte_offset: 48
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fieldset: SQR1
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- name: SQR2
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description: regular sequence register 2
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byte_offset: 52
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fieldset: SQR2
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- name: SQR3
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description: regular sequence register 3
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byte_offset: 56
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fieldset: SQR3
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- name: SQR4
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description: regular sequence register 4
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byte_offset: 60
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fieldset: SQR4
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- name: DR
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description: regular Data Register
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byte_offset: 64
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access: Read
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fieldset: DR
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- name: JSQR
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description: injected sequence register
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byte_offset: 76
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fieldset: JSQR
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- name: OFR1
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description: offset register 1
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byte_offset: 96
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fieldset: OFR1
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- name: OFR2
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description: offset register 2
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byte_offset: 100
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fieldset: OFR2
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- name: OFR3
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description: offset register 3
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byte_offset: 104
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fieldset: OFR3
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- name: OFR4
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description: offset register 4
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byte_offset: 108
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fieldset: OFR4
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- name: JDR1
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description: injected data register 1
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byte_offset: 128
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access: Read
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fieldset: JDR1
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- name: JDR2
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description: injected data register 2
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byte_offset: 132
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access: Read
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fieldset: JDR2
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- name: JDR3
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description: injected data register 3
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byte_offset: 136
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access: Read
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fieldset: JDR3
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- name: JDR4
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description: injected data register 4
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byte_offset: 140
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access: Read
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fieldset: JDR4
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- name: AWD2CR
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description: "Analog Watchdog 2 Configuration\r Register"
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byte_offset: 160
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fieldset: AWD2CR
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- name: AWD3CR
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description: "Analog Watchdog 3 Configuration\r Register"
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byte_offset: 164
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fieldset: AWD3CR
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- name: DIFSEL
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description: "Differential Mode Selection Register\r 2"
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byte_offset: 176
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fieldset: DIFSEL
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- name: CALFACT
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description: Calibration Factors
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byte_offset: 180
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fieldset: CALFACT
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fieldset/AWD2CR:
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description: "Analog Watchdog 2 Configuration\r Register"
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fields:
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- name: AWD2CH0
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description: AWD2CH
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bit_offset: 1
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bit_size: 1
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enum: AWD2CH0
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- name: AWD2CH1
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description: AWD2CH
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bit_offset: 2
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bit_size: 1
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enum: AWD2CH0
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- name: AWD2CH2
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description: AWD2CH
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bit_offset: 3
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bit_size: 1
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enum: AWD2CH0
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- name: AWD2CH3
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description: AWD2CH
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bit_offset: 4
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bit_size: 1
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enum: AWD2CH0
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- name: AWD2CH4
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description: AWD2CH
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bit_offset: 5
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bit_size: 1
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enum: AWD2CH0
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- name: AWD2CH5
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description: AWD2CH
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bit_offset: 6
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bit_size: 1
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enum: AWD2CH0
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- name: AWD2CH6
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description: AWD2CH
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bit_offset: 7
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bit_size: 1
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enum: AWD2CH0
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- name: AWD2CH7
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description: AWD2CH
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bit_offset: 8
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bit_size: 1
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enum: AWD2CH0
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- name: AWD2CH8
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description: AWD2CH
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bit_offset: 9
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bit_size: 1
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enum: AWD2CH0
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- name: AWD2CH9
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description: AWD2CH
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bit_offset: 10
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bit_size: 1
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enum: AWD2CH0
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- name: AWD2CH10
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description: AWD2CH
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bit_offset: 11
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bit_size: 1
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enum: AWD2CH0
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- name: AWD2CH11
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description: AWD2CH
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bit_offset: 12
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bit_size: 1
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enum: AWD2CH0
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- name: AWD2CH12
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description: AWD2CH
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bit_offset: 13
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bit_size: 1
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enum: AWD2CH0
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- name: AWD2CH13
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description: AWD2CH
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bit_offset: 14
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bit_size: 1
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enum: AWD2CH0
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- name: AWD2CH14
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description: AWD2CH
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bit_offset: 15
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bit_size: 1
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enum: AWD2CH0
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- name: AWD2CH15
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description: AWD2CH
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bit_offset: 16
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bit_size: 1
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enum: AWD2CH0
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- name: AWD2CH16
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description: AWD2CH
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bit_offset: 17
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bit_size: 1
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enum: AWD2CH0
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- name: AWD2CH17
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description: AWD2CH
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bit_offset: 18
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bit_size: 1
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enum: AWD2CH0
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fieldset/AWD3CR:
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description: "Analog Watchdog 3 Configuration\r Register"
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fields:
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- name: AWD3CH0
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description: AWD3CH
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bit_offset: 1
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bit_size: 1
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enum: AWD3CH0
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- name: AWD3CH1
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description: AWD3CH
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bit_offset: 2
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bit_size: 1
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enum: AWD3CH0
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- name: AWD3CH2
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description: AWD3CH
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bit_offset: 3
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bit_size: 1
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enum: AWD3CH0
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- name: AWD3CH3
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description: AWD3CH
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bit_offset: 4
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bit_size: 1
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enum: AWD3CH0
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- name: AWD3CH4
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description: AWD3CH
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bit_offset: 5
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bit_size: 1
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enum: AWD3CH0
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- name: AWD3CH5
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description: AWD3CH
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bit_offset: 6
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bit_size: 1
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enum: AWD3CH0
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- name: AWD3CH6
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description: AWD3CH
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bit_offset: 7
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bit_size: 1
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enum: AWD3CH0
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- name: AWD3CH7
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description: AWD3CH
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bit_offset: 8
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bit_size: 1
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enum: AWD3CH0
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- name: AWD3CH8
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description: AWD3CH
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bit_offset: 9
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bit_size: 1
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enum: AWD3CH0
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- name: AWD3CH9
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description: AWD3CH
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bit_offset: 10
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bit_size: 1
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enum: AWD3CH0
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- name: AWD3CH10
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description: AWD3CH
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bit_offset: 11
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bit_size: 1
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enum: AWD3CH0
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- name: AWD3CH11
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description: AWD3CH
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bit_offset: 12
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bit_size: 1
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enum: AWD3CH0
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- name: AWD3CH12
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description: AWD3CH
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bit_offset: 13
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bit_size: 1
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enum: AWD3CH0
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- name: AWD3CH13
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description: AWD3CH
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bit_offset: 14
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bit_size: 1
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enum: AWD3CH0
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- name: AWD3CH14
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description: AWD3CH
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bit_offset: 15
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bit_size: 1
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enum: AWD3CH0
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- name: AWD3CH15
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description: AWD3CH
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bit_offset: 16
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bit_size: 1
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enum: AWD3CH0
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- name: AWD3CH16
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description: AWD3CH
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bit_offset: 17
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bit_size: 1
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enum: AWD3CH0
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- name: AWD3CH17
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description: AWD3CH
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bit_offset: 18
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bit_size: 1
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enum: AWD3CH0
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fieldset/CALFACT:
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description: Calibration Factors
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fields:
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- name: CALFACT_S
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description: CALFACT_S
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bit_offset: 0
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bit_size: 7
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- name: CALFACT_D
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description: CALFACT_D
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bit_offset: 16
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bit_size: 7
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fieldset/CFGR:
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description: configuration register
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fields:
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- name: DMAEN
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description: DMAEN
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bit_offset: 0
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bit_size: 1
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enum: DMAEN
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- name: DMACFG
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description: DMACFG
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bit_offset: 1
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bit_size: 1
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enum: DMACFG
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- name: RES
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description: RES
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bit_offset: 3
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bit_size: 2
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enum: RES
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- name: ALIGN
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description: ALIGN
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bit_offset: 5
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bit_size: 1
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enum: ALIGN
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- name: EXTSEL
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description: EXTSEL
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bit_offset: 6
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bit_size: 4
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enum: EXTSEL
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- name: EXTEN
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description: EXTEN
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bit_offset: 10
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bit_size: 2
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enum: EXTEN
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- name: OVRMOD
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description: OVRMOD
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bit_offset: 12
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bit_size: 1
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enum: OVRMOD
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- name: CONT
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description: CONT
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bit_offset: 13
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bit_size: 1
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enum: CONT
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- name: AUTDLY
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description: AUTDLY
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bit_offset: 14
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bit_size: 1
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enum: AUTDLY
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- name: DISCEN
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description: DISCEN
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bit_offset: 16
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bit_size: 1
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enum: DISCEN
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- name: DISCNUM
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description: DISCNUM
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bit_offset: 17
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bit_size: 3
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- name: JDISCEN
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description: JDISCEN
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bit_offset: 20
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bit_size: 1
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enum: JDISCEN
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- name: JQM
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description: JQM
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bit_offset: 21
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bit_size: 1
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enum: JQM
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- name: AWD1SGL
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description: AWD1SGL
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bit_offset: 22
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bit_size: 1
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enum: AWD1SGL
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- name: AWD1EN
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description: AWD1EN
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bit_offset: 23
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bit_size: 1
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enum: AWD1EN
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- name: JAWD1EN
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description: JAWD1EN
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bit_offset: 24
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bit_size: 1
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enum: JAWD1EN
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- name: JAUTO
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description: JAUTO
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bit_offset: 25
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bit_size: 1
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enum: JAUTO
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- name: AWD1CH
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description: AWDCH1CH
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bit_offset: 26
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bit_size: 5
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fieldset/CR:
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description: control register
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fields:
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- name: ADEN
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description: ADEN
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bit_offset: 0
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bit_size: 1
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enum_read: ADENR
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enum_write: ADENW
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- name: ADDIS
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description: ADDIS
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bit_offset: 1
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bit_size: 1
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enum_read: ADDISR
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enum_write: ADDISW
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- name: ADSTART
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description: ADSTART
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bit_offset: 2
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bit_size: 1
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enum_read: ADSTARTR
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enum_write: ADSTARTW
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- name: JADSTART
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description: JADSTART
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bit_offset: 3
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bit_size: 1
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enum_read: ADSTARTR
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enum_write: ADSTARTW
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- name: ADSTP
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description: ADSTP
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bit_offset: 4
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bit_size: 1
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enum_read: ADSTPR
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enum_write: ADSTPW
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- name: JADSTP
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description: JADSTP
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bit_offset: 5
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bit_size: 1
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enum_read: ADSTPR
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enum_write: ADSTPW
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- name: ADVREGEN
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description: ADVREGEN
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bit_offset: 28
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bit_size: 2
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enum: ADVREGEN
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- name: ADCALDIF
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description: ADCALDIF
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bit_offset: 30
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bit_size: 1
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enum: ADCALDIF
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- name: ADCAL
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description: ADCAL
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bit_offset: 31
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bit_size: 1
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enum: ADCAL
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fieldset/DIFSEL:
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description: "Differential Mode Selection Register\r 2"
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fields:
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- name: DIFSEL_10
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 1
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_11
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 2
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_12
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 3
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_13
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 4
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_14
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 5
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_15
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 6
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_16
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 7
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_17
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 8
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_18
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 9
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_19
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 10
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_110
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 11
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_111
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 12
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_112
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 13
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_113
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 14
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_114
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description: "Differential mode for channels 15 to\r 1"
|
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bit_offset: 15
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_115
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 16
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_116
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 17
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bit_size: 1
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enum: DIFSEL_10
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- name: DIFSEL_117
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description: "Differential mode for channels 15 to\r 1"
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bit_offset: 18
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bit_size: 1
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enum: DIFSEL_10
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fieldset/DR:
|
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description: regular Data Register
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fields:
|
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- name: RDATA
|
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description: Regular data
|
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bit_offset: 0
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bit_size: 16
|
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fieldset/IER:
|
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description: interrupt enable register
|
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fields:
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- name: ADRDYIE
|
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description: ADRDYIE
|
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bit_offset: 0
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bit_size: 1
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enum: ADRDYIE
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- name: EOSMPIE
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description: EOSMPIE
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bit_offset: 1
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bit_size: 1
|
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enum: EOSMPIE
|
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- name: EOCIE
|
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description: EOCIE
|
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bit_offset: 2
|
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bit_size: 1
|
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enum: EOCIE
|
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- name: EOSIE
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description: EOSIE
|
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bit_offset: 3
|
|
bit_size: 1
|
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enum: EOSIE
|
|
- name: OVRIE
|
|
description: OVRIE
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: OVRIE
|
|
- name: JEOCIE
|
|
description: JEOCIE
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: JEOCIE
|
|
- name: JEOSIE
|
|
description: JEOSIE
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: JEOSIE
|
|
- name: AWD1IE
|
|
description: AWD1IE
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: AWD1IE
|
|
- name: AWD2IE
|
|
description: AWD2IE
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: AWD1IE
|
|
- name: AWD3IE
|
|
description: AWD3IE
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: AWD1IE
|
|
- name: JQOVFIE
|
|
description: JQOVFIE
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: JQOVFIE
|
|
fieldset/ISR:
|
|
description: interrupt and status register
|
|
fields:
|
|
- name: ADRDY
|
|
description: ADRDY
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum_read: ADRDYR
|
|
enum_write: ADRDYW
|
|
- name: EOSMP
|
|
description: EOSMP
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum_read: EOSMPR
|
|
enum_write: EOSMPW
|
|
- name: EOC
|
|
description: EOC
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum_read: EOCR
|
|
enum_write: EOCW
|
|
- name: EOS
|
|
description: EOS
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum_read: EOSR
|
|
enum_write: EOSW
|
|
- name: OVR
|
|
description: OVR
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum_read: OVRR
|
|
enum_write: OVRW
|
|
- name: JEOC
|
|
description: JEOC
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum_read: JEOCR
|
|
enum_write: JEOCW
|
|
- name: JEOS
|
|
description: JEOS
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum_read: JEOSR
|
|
enum_write: JEOSW
|
|
- name: AWD1
|
|
description: AWD1
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum_read: AWD1R
|
|
enum_write: AWD1W
|
|
- name: AWD2
|
|
description: AWD2
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum_read: AWD1R
|
|
enum_write: AWD1W
|
|
- name: AWD3
|
|
description: AWD3
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum_read: AWD1R
|
|
enum_write: AWD1W
|
|
- name: JQOVF
|
|
description: JQOVF
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum_read: JQOVFR
|
|
enum_write: JQOVFW
|
|
fieldset/JDR1:
|
|
description: injected data register 1
|
|
fields:
|
|
- name: JDATA1
|
|
description: JDATA1
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/JDR2:
|
|
description: injected data register 2
|
|
fields:
|
|
- name: JDATA2
|
|
description: JDATA2
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/JDR3:
|
|
description: injected data register 3
|
|
fields:
|
|
- name: JDATA3
|
|
description: JDATA3
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/JDR4:
|
|
description: injected data register 4
|
|
fields:
|
|
- name: JDATA4
|
|
description: JDATA4
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/JSQR:
|
|
description: injected sequence register
|
|
fields:
|
|
- name: JL
|
|
description: JL
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: JEXTSEL
|
|
description: JEXTSEL
|
|
bit_offset: 2
|
|
bit_size: 4
|
|
enum: JEXTSEL
|
|
- name: JEXTEN
|
|
description: JEXTEN
|
|
bit_offset: 6
|
|
bit_size: 2
|
|
enum: JEXTEN
|
|
- name: JSQ1
|
|
description: JSQ1
|
|
bit_offset: 8
|
|
bit_size: 5
|
|
- name: JSQ2
|
|
description: JSQ2
|
|
bit_offset: 14
|
|
bit_size: 5
|
|
- name: JSQ3
|
|
description: JSQ3
|
|
bit_offset: 20
|
|
bit_size: 5
|
|
- name: JSQ4
|
|
description: JSQ4
|
|
bit_offset: 26
|
|
bit_size: 5
|
|
fieldset/OFR1:
|
|
description: offset register 1
|
|
fields:
|
|
- name: OFFSET1
|
|
description: OFFSET1
|
|
bit_offset: 0
|
|
bit_size: 12
|
|
- name: OFFSET1_CH
|
|
description: OFFSET1_CH
|
|
bit_offset: 26
|
|
bit_size: 5
|
|
- name: OFFSET1_EN
|
|
description: OFFSET1_EN
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: OFFSET1_EN
|
|
fieldset/OFR2:
|
|
description: offset register 2
|
|
fields:
|
|
- name: OFFSET2
|
|
description: OFFSET2
|
|
bit_offset: 0
|
|
bit_size: 12
|
|
- name: OFFSET2_CH
|
|
description: OFFSET2_CH
|
|
bit_offset: 26
|
|
bit_size: 5
|
|
- name: OFFSET2_EN
|
|
description: OFFSET2_EN
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: OFFSET2_EN
|
|
fieldset/OFR3:
|
|
description: offset register 3
|
|
fields:
|
|
- name: OFFSET3
|
|
description: OFFSET3
|
|
bit_offset: 0
|
|
bit_size: 12
|
|
- name: OFFSET3_CH
|
|
description: OFFSET3_CH
|
|
bit_offset: 26
|
|
bit_size: 5
|
|
- name: OFFSET3_EN
|
|
description: OFFSET3_EN
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: OFFSET3_EN
|
|
fieldset/OFR4:
|
|
description: offset register 4
|
|
fields:
|
|
- name: OFFSET4
|
|
description: OFFSET4
|
|
bit_offset: 0
|
|
bit_size: 12
|
|
- name: OFFSET4_CH
|
|
description: OFFSET4_CH
|
|
bit_offset: 26
|
|
bit_size: 5
|
|
- name: OFFSET4_EN
|
|
description: OFFSET4_EN
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: OFFSET4_EN
|
|
fieldset/SMPR1:
|
|
description: sample time register 1
|
|
fields:
|
|
- name: SMP1
|
|
description: SMP1
|
|
bit_offset: 3
|
|
bit_size: 3
|
|
enum: SMP1
|
|
- name: SMP2
|
|
description: SMP2
|
|
bit_offset: 6
|
|
bit_size: 3
|
|
enum: SMP1
|
|
- name: SMP3
|
|
description: SMP3
|
|
bit_offset: 9
|
|
bit_size: 3
|
|
enum: SMP1
|
|
- name: SMP4
|
|
description: SMP4
|
|
bit_offset: 12
|
|
bit_size: 3
|
|
enum: SMP1
|
|
- name: SMP5
|
|
description: SMP5
|
|
bit_offset: 15
|
|
bit_size: 3
|
|
enum: SMP1
|
|
- name: SMP6
|
|
description: SMP6
|
|
bit_offset: 18
|
|
bit_size: 3
|
|
enum: SMP1
|
|
- name: SMP7
|
|
description: SMP7
|
|
bit_offset: 21
|
|
bit_size: 3
|
|
enum: SMP1
|
|
- name: SMP8
|
|
description: SMP8
|
|
bit_offset: 24
|
|
bit_size: 3
|
|
enum: SMP1
|
|
- name: SMP9
|
|
description: SMP9
|
|
bit_offset: 27
|
|
bit_size: 3
|
|
enum: SMP1
|
|
fieldset/SMPR2:
|
|
description: sample time register 2
|
|
fields:
|
|
- name: SMP10
|
|
description: SMP10
|
|
bit_offset: 0
|
|
bit_size: 3
|
|
enum: SMP10
|
|
- name: SMP11
|
|
description: SMP11
|
|
bit_offset: 3
|
|
bit_size: 3
|
|
enum: SMP10
|
|
- name: SMP12
|
|
description: SMP12
|
|
bit_offset: 6
|
|
bit_size: 3
|
|
enum: SMP10
|
|
- name: SMP13
|
|
description: SMP13
|
|
bit_offset: 9
|
|
bit_size: 3
|
|
enum: SMP10
|
|
- name: SMP14
|
|
description: SMP14
|
|
bit_offset: 12
|
|
bit_size: 3
|
|
enum: SMP10
|
|
- name: SMP15
|
|
description: SMP15
|
|
bit_offset: 15
|
|
bit_size: 3
|
|
enum: SMP10
|
|
- name: SMP16
|
|
description: SMP16
|
|
bit_offset: 18
|
|
bit_size: 3
|
|
enum: SMP10
|
|
- name: SMP17
|
|
description: SMP17
|
|
bit_offset: 21
|
|
bit_size: 3
|
|
enum: SMP10
|
|
- name: SMP18
|
|
description: SMP18
|
|
bit_offset: 24
|
|
bit_size: 3
|
|
enum: SMP10
|
|
fieldset/SQR1:
|
|
description: regular sequence register 1
|
|
fields:
|
|
- name: L
|
|
description: L3
|
|
bit_offset: 0
|
|
bit_size: 4
|
|
- name: SQ1
|
|
description: SQ1
|
|
bit_offset: 6
|
|
bit_size: 5
|
|
- name: SQ2
|
|
description: SQ2
|
|
bit_offset: 12
|
|
bit_size: 5
|
|
- name: SQ3
|
|
description: SQ3
|
|
bit_offset: 18
|
|
bit_size: 5
|
|
- name: SQ4
|
|
description: SQ4
|
|
bit_offset: 24
|
|
bit_size: 5
|
|
fieldset/SQR2:
|
|
description: regular sequence register 2
|
|
fields:
|
|
- name: SQ5
|
|
description: SQ5
|
|
bit_offset: 0
|
|
bit_size: 5
|
|
- name: SQ6
|
|
description: SQ6
|
|
bit_offset: 6
|
|
bit_size: 5
|
|
- name: SQ7
|
|
description: SQ7
|
|
bit_offset: 12
|
|
bit_size: 5
|
|
- name: SQ8
|
|
description: SQ8
|
|
bit_offset: 18
|
|
bit_size: 5
|
|
- name: SQ9
|
|
description: SQ9
|
|
bit_offset: 24
|
|
bit_size: 5
|
|
fieldset/SQR3:
|
|
description: regular sequence register 3
|
|
fields:
|
|
- name: SQ10
|
|
description: SQ10
|
|
bit_offset: 0
|
|
bit_size: 5
|
|
- name: SQ11
|
|
description: SQ11
|
|
bit_offset: 6
|
|
bit_size: 5
|
|
- name: SQ12
|
|
description: SQ12
|
|
bit_offset: 12
|
|
bit_size: 5
|
|
- name: SQ13
|
|
description: SQ13
|
|
bit_offset: 18
|
|
bit_size: 5
|
|
- name: SQ14
|
|
description: SQ14
|
|
bit_offset: 24
|
|
bit_size: 5
|
|
fieldset/SQR4:
|
|
description: regular sequence register 4
|
|
fields:
|
|
- name: SQ15
|
|
description: SQ15
|
|
bit_offset: 0
|
|
bit_size: 5
|
|
- name: SQ16
|
|
description: SQ16
|
|
bit_offset: 6
|
|
bit_size: 5
|
|
fieldset/TR1:
|
|
description: watchdog threshold register 1
|
|
fields:
|
|
- name: LT1
|
|
description: LT1
|
|
bit_offset: 0
|
|
bit_size: 12
|
|
- name: HT1
|
|
description: HT1
|
|
bit_offset: 16
|
|
bit_size: 12
|
|
fieldset/TR2:
|
|
description: watchdog threshold register
|
|
fields:
|
|
- name: LT2
|
|
description: LT2
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
- name: HT2
|
|
description: HT2
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
fieldset/TR3:
|
|
description: watchdog threshold register 3
|
|
fields:
|
|
- name: LT3
|
|
description: LT3
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
- name: HT3
|
|
description: HT3
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
enum/ADCAL:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Complete
|
|
description: Calibration complete
|
|
value: 0
|
|
- name: Calibration
|
|
description: Start the calibration of the ADC
|
|
value: 1
|
|
enum/ADCALDIF:
|
|
bit_size: 1
|
|
variants:
|
|
- name: SingleEnded
|
|
description: Calibration for single-ended mode
|
|
value: 0
|
|
- name: Differential
|
|
description: Calibration for differential mode
|
|
value: 1
|
|
enum/ADDISR:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotDisabling
|
|
description: No disable command active
|
|
value: 0
|
|
- name: Disabling
|
|
description: ADC disabling
|
|
value: 1
|
|
enum/ADDISW:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disable
|
|
description: Disable the ADC
|
|
value: 1
|
|
enum/ADENR:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: ADC disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: ADC enabled
|
|
value: 1
|
|
enum/ADENW:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Enabled
|
|
description: Enable the ADC
|
|
value: 1
|
|
enum/ADRDYIE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: ADC ready interrupt disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: ADC ready interrupt enabled
|
|
value: 1
|
|
enum/ADRDYR:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotReady
|
|
description: ADC is not ready to start conversion
|
|
value: 0
|
|
- name: Ready
|
|
description: ADC is ready to start conversion
|
|
value: 1
|
|
enum/ADRDYW:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Clear
|
|
description: Clear ADC is ready to start conversion flag
|
|
value: 1
|
|
enum/ADSTARTR:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotActive
|
|
description: No conversion ongoing
|
|
value: 0
|
|
- name: Active
|
|
description: ADC operating and may be converting
|
|
value: 1
|
|
enum/ADSTARTW:
|
|
bit_size: 1
|
|
variants:
|
|
- name: StartConversion
|
|
description: Start the ADC conversion (may be delayed for hardware triggers)
|
|
value: 1
|
|
enum/ADSTPR:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotStopping
|
|
description: No stop command active
|
|
value: 0
|
|
- name: Stopping
|
|
description: ADC stopping conversion
|
|
value: 1
|
|
enum/ADSTPW:
|
|
bit_size: 1
|
|
variants:
|
|
- name: StopConversion
|
|
description: Stop the active conversion
|
|
value: 1
|
|
enum/ADVREGEN:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Intermediate
|
|
description: Intermediate state required when moving the ADC voltage regulator between states
|
|
value: 0
|
|
- name: Enabled
|
|
description: ADC voltage regulator enabled
|
|
value: 1
|
|
- name: Disabled
|
|
description: ADC voltage regulator disabled
|
|
value: 2
|
|
enum/ALIGN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Right
|
|
description: Right alignment
|
|
value: 0
|
|
- name: Left
|
|
description: Left alignment
|
|
value: 1
|
|
enum/AUTDLY:
|
|
bit_size: 1
|
|
variants:
|
|
- name: "Off"
|
|
description: Auto delayed conversion mode off
|
|
value: 0
|
|
- name: "On"
|
|
description: Auto delayed conversion mode on
|
|
value: 1
|
|
enum/AWD1EN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Analog watchdog 1 disabled on regular channels
|
|
value: 0
|
|
- name: Enabled
|
|
description: Analog watchdog 1 enabled on regular channels
|
|
value: 1
|
|
enum/AWD1IE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Analog watchdog interrupt disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: Analog watchdog interrupt enabled
|
|
value: 1
|
|
enum/AWD1R:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEvent
|
|
description: No analog watchdog event occurred
|
|
value: 0
|
|
- name: Event
|
|
description: Analog watchdog event occurred
|
|
value: 1
|
|
enum/AWD1SGL:
|
|
bit_size: 1
|
|
variants:
|
|
- name: All
|
|
description: Analog watchdog 1 enabled on all channels
|
|
value: 0
|
|
- name: Single
|
|
description: Analog watchdog 1 enabled on single channel selected in AWD1CH
|
|
value: 1
|
|
enum/AWD1W:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Clear
|
|
description: Clear analog watchdog event occurred flag
|
|
value: 1
|
|
enum/AWD2CH0:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotMonitored
|
|
description: Input channel not monitored by AWDx
|
|
value: 0
|
|
- name: Monitored
|
|
description: Input channel monitored by AWDx
|
|
value: 1
|
|
enum/AWD3CH0:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotMonitored
|
|
description: Input channel not monitored by AWDx
|
|
value: 0
|
|
- name: Monitored
|
|
description: Input channel monitored by AWDx
|
|
value: 1
|
|
enum/CONT:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Single
|
|
description: Single conversion mode
|
|
value: 0
|
|
- name: Continuous
|
|
description: Continuous conversion mode
|
|
value: 1
|
|
enum/DIFSEL_10:
|
|
bit_size: 1
|
|
variants:
|
|
- name: SingleEnded
|
|
description: Input channel is configured in single-ended mode
|
|
value: 0
|
|
- name: Differential
|
|
description: Input channel is configured in differential mode
|
|
value: 1
|
|
enum/DISCEN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Discontinuous mode on regular channels disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: Discontinuous mode on regular channels enabled
|
|
value: 1
|
|
enum/DMACFG:
|
|
bit_size: 1
|
|
variants:
|
|
- name: OneShot
|
|
description: DMA One Shot Mode selected
|
|
value: 0
|
|
- name: Circular
|
|
description: DMA circular mode selected
|
|
value: 1
|
|
enum/DMAEN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: DMA disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: DMA enabled
|
|
value: 1
|
|
enum/EOCIE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: End of regular conversion interrupt disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: End of regular conversion interrupt enabled
|
|
value: 1
|
|
enum/EOCR:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotComplete
|
|
description: Regular conversion is not complete
|
|
value: 0
|
|
- name: Complete
|
|
description: Regular conversion complete
|
|
value: 1
|
|
enum/EOCW:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Clear
|
|
description: Clear regular conversion complete flag
|
|
value: 1
|
|
enum/EOSIE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: End of regular sequence interrupt disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: End of regular sequence interrupt enabled
|
|
value: 1
|
|
enum/EOSMPIE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: End of regular conversion sampling phase interrupt disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: End of regular conversion sampling phase interrupt enabled
|
|
value: 1
|
|
enum/EOSMPR:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotEnded
|
|
description: End of sampling phase no yet reached
|
|
value: 0
|
|
- name: Ended
|
|
description: End of sampling phase reached
|
|
value: 1
|
|
enum/EOSMPW:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Clear
|
|
description: Clear end of sampling phase reached flag
|
|
value: 1
|
|
enum/EOSR:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotComplete
|
|
description: Regular sequence is not complete
|
|
value: 0
|
|
- name: Complete
|
|
description: Regular sequence complete
|
|
value: 1
|
|
enum/EOSW:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Clear
|
|
description: Clear regular sequence complete flag
|
|
value: 1
|
|
enum/EXTEN:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Disabled
|
|
description: Trigger detection disabled
|
|
value: 0
|
|
- name: RisingEdge
|
|
description: Trigger detection on the rising edge
|
|
value: 1
|
|
- name: FallingEdge
|
|
description: Trigger detection on the falling edge
|
|
value: 2
|
|
- name: BothEdges
|
|
description: Trigger detection on both the rising and falling edges
|
|
value: 3
|
|
enum/EXTSEL:
|
|
bit_size: 4
|
|
variants:
|
|
- name: TIM1_CC1
|
|
description: Timer 1 CC1 event
|
|
value: 0
|
|
- name: TIM1_CC2
|
|
description: Timer 1 CC2 event
|
|
value: 1
|
|
- name: TIM1_CC3
|
|
description: Timer 1 CC3 event
|
|
value: 2
|
|
- name: TIM2_CC2
|
|
description: Timer 2 CC2 event
|
|
value: 3
|
|
- name: TIM3_TRGO
|
|
description: Timer 3 TRGO event
|
|
value: 4
|
|
- name: EXTI11
|
|
description: EXTI line 11
|
|
value: 6
|
|
- name: HRTIM_ADCTRG1
|
|
description: HRTIM_ADCTRG1 event
|
|
value: 7
|
|
- name: HRTIM_ADCTRG3
|
|
description: HRTIM_ADCTRG3 event
|
|
value: 8
|
|
- name: TIM1_TRGO
|
|
description: Timer 1 TRGO event
|
|
value: 9
|
|
- name: TIM1_TRGO2
|
|
description: Timer 1 TRGO2 event
|
|
value: 10
|
|
- name: TIM2_TRGO
|
|
description: Timer 2 TRGO event
|
|
value: 11
|
|
- name: TIM6_TRGO
|
|
description: Timer 6 TRGO event
|
|
value: 13
|
|
- name: TIM15_TRGO
|
|
description: Timer 15 TRGO event
|
|
value: 14
|
|
- name: TIM3_CC4
|
|
description: Timer 3 CC4 event
|
|
value: 15
|
|
enum/JAUTO:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Automatic injected group conversion disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: Automatic injected group conversion enabled
|
|
value: 1
|
|
enum/JAWD1EN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Analog watchdog 1 disabled on injected channels
|
|
value: 0
|
|
- name: Enabled
|
|
description: Analog watchdog 1 enabled on injected channels
|
|
value: 1
|
|
enum/JDISCEN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Discontinuous mode on injected channels disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: Discontinuous mode on injected channels enabled
|
|
value: 1
|
|
enum/JEOCIE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: End of injected conversion interrupt disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: End of injected conversion interrupt enabled
|
|
value: 1
|
|
enum/JEOCR:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotComplete
|
|
description: Injected conversion is not complete
|
|
value: 0
|
|
- name: Complete
|
|
description: Injected conversion complete
|
|
value: 1
|
|
enum/JEOCW:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Clear
|
|
description: Clear injected conversion complete flag
|
|
value: 1
|
|
enum/JEOSIE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: End of injected sequence interrupt disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: End of injected sequence interrupt enabled
|
|
value: 1
|
|
enum/JEOSR:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotComplete
|
|
description: Injected sequence is not complete
|
|
value: 0
|
|
- name: Complete
|
|
description: Injected sequence complete
|
|
value: 1
|
|
enum/JEOSW:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Clear
|
|
description: Clear Injected sequence complete flag
|
|
value: 1
|
|
enum/JEXTEN:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Disabled
|
|
description: Trigger detection disabled
|
|
value: 0
|
|
- name: RisingEdge
|
|
description: Trigger detection on the rising edge
|
|
value: 1
|
|
- name: FallingEdge
|
|
description: Trigger detection on the falling edge
|
|
value: 2
|
|
- name: BothEdges
|
|
description: Trigger detection on both the rising and falling edges
|
|
value: 3
|
|
enum/JEXTSEL:
|
|
bit_size: 4
|
|
variants:
|
|
- name: TIM1_TRGO
|
|
description: Timer 1 TRGO event
|
|
value: 0
|
|
- name: TIM1_CC4
|
|
description: Timer 1 CC4 event
|
|
value: 1
|
|
- name: TIM2_TRGO
|
|
description: Timer 2 TRGO event
|
|
value: 2
|
|
- name: TIM2_CC1
|
|
description: Timer 2 CC1 event
|
|
value: 3
|
|
- name: TIM3_CC4
|
|
description: Timer 3 CC4 event
|
|
value: 4
|
|
- name: EXTI15
|
|
description: EXTI line 15
|
|
value: 6
|
|
- name: TIM1_TRGO2
|
|
description: Timer 1 TRGO2 event
|
|
value: 8
|
|
- name: HRTIM_ADCTRG2
|
|
description: HRTIM_ADCTRG2 event
|
|
value: 9
|
|
- name: HRTIM_ADCTRG4
|
|
description: HRTIM_ADCTRG4 event
|
|
value: 10
|
|
- name: TIM3_CC3
|
|
description: Timer 3 CC3 event
|
|
value: 11
|
|
- name: TIM3_TRGO
|
|
description: Timer 3 TRGO event
|
|
value: 12
|
|
- name: TIM3_CC1
|
|
description: Timer 3 CC1 event
|
|
value: 13
|
|
- name: TIM6_TRGO
|
|
description: Timer 6 TRGO event
|
|
value: 14
|
|
- name: TIM15_TRGO
|
|
description: Timer 15 TRGO event
|
|
value: 15
|
|
enum/JQM:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Mode0
|
|
description: "JSQR Mode 0: Queue maintains the last written configuration into JSQR"
|
|
value: 0
|
|
- name: Mode1
|
|
description: "JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence"
|
|
value: 1
|
|
enum/JQOVFIE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Injected context queue overflow interrupt disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: Injected context queue overflow interrupt enabled
|
|
value: 1
|
|
enum/JQOVFR:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoOverflow
|
|
description: No injected context queue overflow has occurred
|
|
value: 0
|
|
- name: Overflow
|
|
description: Injected context queue overflow has occurred
|
|
value: 1
|
|
enum/JQOVFW:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Clear
|
|
description: Clear injected context queue overflow flag
|
|
value: 1
|
|
enum/OFFSET1_EN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Offset disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: Offset enabled
|
|
value: 1
|
|
enum/OFFSET2_EN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Offset disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: Offset enabled
|
|
value: 1
|
|
enum/OFFSET3_EN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Offset disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: Offset enabled
|
|
value: 1
|
|
enum/OFFSET4_EN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Offset disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: Offset enabled
|
|
value: 1
|
|
enum/OVRIE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Overrun interrupt disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: Overrun interrupt enabled
|
|
value: 1
|
|
enum/OVRMOD:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Preserve
|
|
description: Preserve DR register when an overrun is detected
|
|
value: 0
|
|
- name: Overwrite
|
|
description: Overwrite DR register when an overrun is detected
|
|
value: 1
|
|
enum/OVRR:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoOverrun
|
|
description: No overrun occurred
|
|
value: 0
|
|
- name: Overrun
|
|
description: Overrun occurred
|
|
value: 1
|
|
enum/OVRW:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Clear
|
|
description: Clear overrun occurred flag
|
|
value: 1
|
|
enum/RES:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Bits12
|
|
description: 12-bit
|
|
value: 0
|
|
- name: Bits10
|
|
description: 10-bit
|
|
value: 1
|
|
- name: Bits8
|
|
description: 8-bit
|
|
value: 2
|
|
- name: Bits6
|
|
description: 6-bit
|
|
value: 3
|
|
enum/SMP1:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Cycles1_5
|
|
description: 1.5 ADC clock cycles
|
|
value: 0
|
|
- name: Cycles2_5
|
|
description: 2.5 ADC clock cycles
|
|
value: 1
|
|
- name: Cycles4_5
|
|
description: 4.5 ADC clock cycles
|
|
value: 2
|
|
- name: Cycles7_5
|
|
description: 7.5 ADC clock cycles
|
|
value: 3
|
|
- name: Cycles19_5
|
|
description: 19.5 ADC clock cycles
|
|
value: 4
|
|
- name: Cycles61_5
|
|
description: 61.5 ADC clock cycles
|
|
value: 5
|
|
- name: Cycles181_5
|
|
description: 181.5 ADC clock cycles
|
|
value: 6
|
|
- name: Cycles601_5
|
|
description: 601.5 ADC clock cycles
|
|
value: 7
|
|
enum/SMP10:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Cycles1_5
|
|
description: 1.5 ADC clock cycles
|
|
value: 0
|
|
- name: Cycles2_5
|
|
description: 2.5 ADC clock cycles
|
|
value: 1
|
|
- name: Cycles4_5
|
|
description: 4.5 ADC clock cycles
|
|
value: 2
|
|
- name: Cycles7_5
|
|
description: 7.5 ADC clock cycles
|
|
value: 3
|
|
- name: Cycles19_5
|
|
description: 19.5 ADC clock cycles
|
|
value: 4
|
|
- name: Cycles61_5
|
|
description: 61.5 ADC clock cycles
|
|
value: 5
|
|
- name: Cycles181_5
|
|
description: 181.5 ADC clock cycles
|
|
value: 6
|
|
- name: Cycles601_5
|
|
description: 601.5 ADC clock cycles
|
|
value: 7
|