197 lines
9.7 KiB
YAML
197 lines
9.7 KiB
YAML
block/SYSCFG:
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description: System configuration controller
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items:
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- name: SECCFGR
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description: secure configuration register
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byte_offset: 0
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fieldset: SECCFGR
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- name: CFGR1
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description: configuration register 1
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byte_offset: 4
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fieldset: CFGR1
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- name: FPUIMR
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description: FPU interrupt mask register
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byte_offset: 8
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fieldset: FPUIMR
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- name: CNSLCKR
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description: CPU non-secure lock register
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byte_offset: 12
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fieldset: CNSLCKR
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- name: CSLOCKR
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description: CPU secure lock register
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byte_offset: 16
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fieldset: CSLOCKR
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- name: CFGR2
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description: configuration register 2
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byte_offset: 20
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fieldset: CFGR2
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- name: MESR
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description: memory erase status register
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byte_offset: 24
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fieldset: MESR
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- name: CCCSR
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description: compensation cell control/status register
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byte_offset: 28
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fieldset: CCCSR
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- name: CCVR
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description: compensation cell value register
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byte_offset: 32
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fieldset: CCVR
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- name: CCCR
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description: compensation cell code register
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byte_offset: 36
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fieldset: CCCR
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- name: RSSCMDR
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description: RSS command register
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byte_offset: 44
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fieldset: RSSCMDR
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fieldset/CCCR:
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description: compensation cell code register
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fields:
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- name: NCC1
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description: "NMOS compensation code of the I/Os supplied by V<sub>DD</sub>\r These bits are written by software to define an I/Os compensation cell code for NMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the CCCSR is set."
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bit_offset: 0
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bit_size: 4
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- name: PCC1
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description: "PMOS compensation code of the I/Os supplied by V<sub>DD</sub>\r These bits are written by software to define an I/Os compensation cell code for PMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the CCCSR is set."
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bit_offset: 4
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bit_size: 4
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fieldset/CCCSR:
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description: compensation cell control/status register
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fields:
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- name: EN1
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description: "VDD I/Os compensation cell enable\r This bit enables the compensation cell of the I/Os supplied by V<sub>DD</sub>."
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bit_offset: 0
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bit_size: 1
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- name: CS1
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description: "VDD I/Os code selection\r This bit selects the code to be applied for the compensation cell of the I/Os supplied by V<sub>DD</sub>."
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bit_offset: 1
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bit_size: 1
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- name: RDY1
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description: "VDD I/Os compensation cell ready flag\r This bit provides the compensation cell status of the I/Os supplied by V<sub>DD</sub>.\r Note: The HSI clock is required for the compensation cell to work properly. The compensation cell ready bit (RDY1) is not set if the HSI clock is not enabled (HSION)."
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bit_offset: 8
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bit_size: 1
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fieldset/CCVR:
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description: compensation cell value register
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fields:
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- name: NCV1
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description: "NMOS compensation value of the I/Os supplied by V<sub>DD</sub>\r This value is provided by the cell and can be used by the CPU to compute an I/Os compensation cell code for NMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the CCCSR is reset."
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bit_offset: 0
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bit_size: 4
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- name: PCV1
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description: "PMOS compensation value of the I/Os supplied by V<sub>DD</sub>\r This value is provided by the cell and can be used by the CPU to compute an I/Os compensation cell code for PMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the CCCSR is reset."
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bit_offset: 4
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bit_size: 4
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fieldset/CFGR1:
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description: configuration register 1
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fields:
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- name: BOOSTEN
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description: "I/O analog switch voltage booster enable\r Access can be protected by GTZC_TZSC ADC4SEC.\r Note: Refer to Table<6C>121 for setting."
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bit_offset: 8
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bit_size: 1
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- name: ANASWVDD
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description: "GPIO analog switch control voltage selection\r Access can be protected by GTZC_TZSC ADC4SEC.\r Note: Refer to Table<6C>121 for setting."
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bit_offset: 9
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bit_size: 1
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- name: PA6_FMP
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description: "Fast-mode Plus drive capability activation on PA6\r This bit can be read and written only with secure access if PA6 is secure in GPIOA. This bit enables the Fast-mode Plus drive mode for PA6 when PA6 is not used by I2C peripheral. This can be used to dive a LED for instance.\r Access can be protected by GPIOA SEC6."
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bit_offset: 16
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bit_size: 1
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- name: PA7_FMP
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description: "Fast-mode Plus drive capability activation on PA7\r This bit can be read and written only with secure access if PA7 is secure in GPIOA. This bit enables the Fast-mode Plus drive mode for PA7 when PA7 is not used by I2C peripheral. This can be used to dive a LED for instance.\r Access can be protected by GPIOA SEC7."
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bit_offset: 17
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bit_size: 1
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- name: PA15_FMP
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description: "Fast-mode Plus drive capability activation on PA15\r This bit can be read and written only with secure access if PA15 is secure in GPIOA. This bit enables the Fast-mode Plus drive mode for PA15 when PA15 is not used by I2C peripheral. This can be used to dive a LED for instance.\r Access can be protected by GPIOA SEC15."
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bit_offset: 18
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bit_size: 1
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- name: PB3_FMP
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description: "Fast-mode Plus drive capability activation on PB3\r This bit can be read and written only with secure access if PB3 is secure in GPIOB. This bit enables the Fast-mode Plus drive mode for PB3 when PB3 is not used by I2C peripheral. This can be used to dive a LED for instance.\r Access can be protected by GPIOB SEC3."
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bit_offset: 19
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bit_size: 1
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fieldset/CFGR2:
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description: configuration register 2
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fields:
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- name: CLL
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description: "Cortex-M33 LOCKUP (hardfault) output enable\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the connection of Cortex-M33 LOCKUP (hardfault) output to TIM1/16/17 break input."
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bit_offset: 0
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bit_size: 1
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- name: SPL
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description: "SRAM2 parity lock bit\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/16/17 break inputs."
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bit_offset: 1
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bit_size: 1
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- name: PVDL
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description: "PVD lock enable bit\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection to TIM1/16/17 break input, as well as the PVDE and PVDLS[2:0] in the PWR register."
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bit_offset: 2
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bit_size: 1
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- name: ECCL
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description: "ECC lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the Flash ECC double error signal connection to TIM1/16/17 break input."
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bit_offset: 3
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bit_size: 1
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fieldset/CNSLCKR:
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description: CPU non-secure lock register
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fields:
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- name: LOCKNSVTOR
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description: "VTOR_NS register lock\r This bit is set by software and cleared only by a system reset."
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bit_offset: 0
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bit_size: 1
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- name: LOCKNSMPU
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description: "Non-secure MPU registers lock\r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to non-secure MPU_CTRL_NS, MPU_RNR_NS and MPU_RBAR_NS registers."
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bit_offset: 1
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bit_size: 1
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fieldset/CSLOCKR:
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description: CPU secure lock register
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fields:
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- name: LOCKSVTAIRCR
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description: "VTOR_S register and AIRCR register bits lock\r This bit is set by software and cleared only by a system reset. When set, it disables write access to VTOR_S register, PRIS and BFHFNMINS bits in the AIRCR register."
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bit_offset: 0
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bit_size: 1
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- name: LOCKSMPU
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description: "Secure MPU registers lock\r This bit is set by software and cleared only by a system reset. When set, it disables write access to secure MPU_CTRL, MPU_RNR and MPU_RBAR registers."
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bit_offset: 1
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bit_size: 1
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- name: LOCKSAU
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description: "SAU registers lock\r This bit is set by software and cleared only by a system reset. When set, it disables write access to SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers."
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bit_offset: 2
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bit_size: 1
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fieldset/FPUIMR:
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description: FPU interrupt mask register
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fields:
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- name: FPU_IE
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description: "Floating point unit interrupts enable bits\r FPU_IE[5]: Inexact interrupt enable (interrupt disable at reset)\r FPU_IE[4]: Input abnormal interrupt enable\r FPU_IE[3]: Overflow interrupt enable\r FPU_IE[2]: Underflow interrupt enable\r FPU_IE[1]: Divide-by-zero interrupt enable\r FPU_IE[0]: Invalid operation Interrupt enable"
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bit_offset: 0
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bit_size: 6
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fieldset/MESR:
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description: memory erase status register
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fields:
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- name: MCLR
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description: "Device memories erase status\r This bit is set by hardware when SRAM2, ICACHE, PKA SRAM erase is completed after power-on reset or tamper detection (refer to Section<6F>75: Tamper and backup registers (TAMP) for more details). This bit is not reset by system reset and is cleared by software by writing 1 to it."
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bit_offset: 0
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bit_size: 1
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- name: IPMEE
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description: "ICACHE and PKA SRAM erase status\r This bit is set by hardware when ICACHE and PKA SRAM erase is completed after potential tamper detection (refer to Section<6F>75: Tamper and backup registers (TAMP) for more details). This bit is cleared by software by writing 1 to it."
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bit_offset: 16
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bit_size: 1
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fieldset/RSSCMDR:
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description: RSS command register
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fields:
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- name: RSSCMD
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description: "RSS commands\r This field defines a command to be executed by the RSS."
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bit_offset: 0
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bit_size: 16
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fieldset/SECCFGR:
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description: secure configuration register
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fields:
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- name: SYSCFGSEC
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description: clock control, memory erase status and compensation cell registers security
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bit_offset: 0
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bit_size: 1
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- name: CLASSBSEC
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description: Class B security
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bit_offset: 1
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bit_size: 1
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- name: FPUSEC
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description: FPU security
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bit_offset: 3
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bit_size: 1
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