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stm32-data/data/registers/rcc_u5.yaml
Dario Nieuwenhuis ee64389697 Rename HSI16 -> HSI
2023-10-22 22:32:08 +02:00

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block/RCC:
description: Reset and clock control
items:
- name: CR
description: RCC clock control register
byte_offset: 0
fieldset: CR
- name: ICSCR1
description: RCC internal clock sources calibration register 1
byte_offset: 8
fieldset: ICSCR1
- name: ICSCR2
description: RCC internal clock sources calibration register 2
byte_offset: 12
fieldset: ICSCR2
- name: ICSCR3
description: RCC internal clock sources calibration register 3
byte_offset: 16
fieldset: ICSCR3
- name: CRRCR
description: RCC clock recovery RC register
byte_offset: 20
fieldset: CRRCR
- name: CFGR1
description: RCC clock configuration register 1
byte_offset: 28
fieldset: CFGR1
- name: CFGR2
description: RCC clock configuration register 2
byte_offset: 32
fieldset: CFGR2
- name: CFGR3
description: RCC clock configuration register 3
byte_offset: 36
fieldset: CFGR3
- name: PLL1CFGR
description: RCC PLL1 configuration register
byte_offset: 40
fieldset: PLL1CFGR
- name: PLL2CFGR
description: RCC PLL2 configuration register
byte_offset: 44
fieldset: PLL23CFGR
- name: PLL3CFGR
description: RCC PLL3 configuration register
byte_offset: 48
fieldset: PLL23CFGR
- name: PLL1DIVR
description: RCC PLL1 dividers register
byte_offset: 52
fieldset: PLLDIVR
- name: PLL1FRACR
description: RCC PLL1 fractional divider register
byte_offset: 56
fieldset: PLLFRACR
- name: PLL2DIVR
description: RCC PLL2 dividers configuration register
byte_offset: 60
fieldset: PLLDIVR
- name: PLL2FRACR
description: RCC PLL2 fractional divider register
byte_offset: 64
fieldset: PLLFRACR
- name: PLL3DIVR
description: RCC PLL3 dividers configuration register
byte_offset: 68
fieldset: PLLDIVR
- name: PLL3FRACR
description: RCC PLL3 fractional divider register
byte_offset: 72
fieldset: PLLFRACR
- name: CIER
description: RCC clock interrupt enable register
byte_offset: 80
fieldset: CIER
- name: CIFR
description: RCC clock interrupt flag register
byte_offset: 84
fieldset: CIFR
- name: CICR
description: RCC clock interrupt clear register
byte_offset: 88
fieldset: CICR
- name: AHB1RSTR
description: RCC AHB1 peripheral reset register
byte_offset: 96
fieldset: AHB1RSTR
- name: AHB2RSTR1
description: RCC AHB2 peripheral reset register 1
byte_offset: 100
fieldset: AHB2RSTR1
- name: AHB2RSTR2
description: RCC AHB2 peripheral reset register 2
byte_offset: 104
fieldset: AHB2RSTR2
- name: AHB3RSTR
description: RCC AHB3 peripheral reset register
byte_offset: 108
fieldset: AHB3RSTR
- name: APB1RSTR1
description: RCC APB1 peripheral reset register 1
byte_offset: 116
fieldset: APB1RSTR1
- name: APB1RSTR2
description: RCC APB1 peripheral reset register 2
byte_offset: 120
fieldset: APB1RSTR2
- name: APB2RSTR
description: RCC APB2 peripheral reset register
byte_offset: 124
fieldset: APB2RSTR
- name: APB3RSTR
description: RCC APB3 peripheral reset register
byte_offset: 128
fieldset: APB3RSTR
- name: AHB1ENR
description: RCC AHB1 peripheral clock enable register
byte_offset: 136
fieldset: AHB1ENR
- name: AHB2ENR1
description: RCC AHB2 peripheral clock enable register 1
byte_offset: 140
fieldset: AHB2ENR1
- name: AHB2ENR2
description: RCC AHB2 peripheral clock enable register 2
byte_offset: 144
fieldset: AHB2ENR2
- name: AHB3ENR
description: RCC AHB3 peripheral clock enable register
byte_offset: 148
fieldset: AHB3ENR
- name: APB1ENR1
description: RCC APB1 peripheral clock enable register 1
byte_offset: 156
fieldset: APB1ENR1
- name: APB1ENR2
description: RCC APB1 peripheral clock enable register 2
byte_offset: 160
fieldset: APB1ENR2
- name: APB2ENR
description: RCC APB2 peripheral clock enable register
byte_offset: 164
fieldset: APB2ENR
- name: APB3ENR
description: RCC APB3 peripheral clock enable register
byte_offset: 168
fieldset: APB3ENR
- name: AHB1SMENR
description: RCC AHB1 peripheral clocks enable in Sleep and Stop modes register
byte_offset: 176
fieldset: AHB1SMENR
- name: AHB2SMENR1
description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 1"
byte_offset: 180
fieldset: AHB2SMENR1
- name: AHB2SMENR2
description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 2"
byte_offset: 184
fieldset: AHB2SMENR2
- name: AHB3SMENR
description: RCC AHB3 peripheral clocks enable in Sleep and Stop modes register
byte_offset: 188
fieldset: AHB3SMENR
- name: APB1SMENR1
description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes\tregister 1"
byte_offset: 196
fieldset: APB1SMENR1
- name: APB1SMENR2
description: "RCC APB1 peripheral clocks enable in Sleep and\tStop modes register 2"
byte_offset: 200
fieldset: APB1SMENR2
- name: APB2SMENR
description: RCC APB2 peripheral clocks enable in Sleep and Stop modes register
byte_offset: 204
fieldset: APB2SMENR
- name: APB3SMENR
description: RCC APB3 peripheral clock enable in Sleep and Stop modes register
byte_offset: 208
fieldset: APB3SMENR
- name: SRDAMR
description: RCC SmartRun domain peripheral autonomous mode register
byte_offset: 216
fieldset: SRDAMR
- name: CCIPR1
description: RCC peripherals independent clock configuration register 1
byte_offset: 224
fieldset: CCIPR1
- name: CCIPR2
description: RCC peripherals independent clock configuration register 2
byte_offset: 228
fieldset: CCIPR2
- name: CCIPR3
description: RCC peripherals independent clock configuration register 3
byte_offset: 232
fieldset: CCIPR3
- name: BDCR
description: RCC Backup domain control register
byte_offset: 240
fieldset: BDCR
- name: CSR
description: RCC control/status register
byte_offset: 244
fieldset: CSR
- name: SECCFGR
description: RCC secure configuration register
byte_offset: 272
fieldset: SECCFGR
- name: PRIVCFGR
description: RCC privilege configuration register
byte_offset: 276
fieldset: PRIVCFGR
fieldset/AHB1ENR:
description: RCC AHB1 peripheral clock enable register
fields:
- name: GPDMA1EN
description: "GPDMA1 clock enable\r Set and cleared by software."
bit_offset: 0
bit_size: 1
- name: CORDICEN
description: "CORDIC clock enable\r Set and cleared by software."
bit_offset: 1
bit_size: 1
- name: FMACEN
description: "FMAC clock enable\r Set and reset by software."
bit_offset: 2
bit_size: 1
- name: MDF1EN
description: "MDF1 clock enable\r Set and reset by software."
bit_offset: 3
bit_size: 1
- name: FLASHEN
description: "FLASH clock enable\r Set and cleared by software. This bit can be disabled only when the Flash memory is in power down mode."
bit_offset: 8
bit_size: 1
- name: CRCEN
description: "CRC clock enable\r Set and cleared by software."
bit_offset: 12
bit_size: 1
- name: JPEGEN
description: "JPEG clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 15
bit_size: 1
- name: TSCEN
description: "Touch sensing controller clock enable\r Set and cleared by software."
bit_offset: 16
bit_size: 1
- name: RAMCFGEN
description: "RAMCFG clock enable\r Set and cleared by software."
bit_offset: 17
bit_size: 1
- name: DMA2DEN
description: "DMA2D clock enable\r Set and cleared by software."
bit_offset: 18
bit_size: 1
- name: GFXMMUEN
description: "GFXMMU clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 19
bit_size: 1
- name: GPU2DEN
description: "GPU2D clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 20
bit_size: 1
- name: DCACHE2EN
description: "DCACHE2 clock enable \r This bit is set and reset by software.\r Note: DCACHE2 clock must be enabled to access memories, even if the DCACHE2 is bypassed.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 21
bit_size: 1
- name: GTZC1EN
description: "GTZC1 clock enable\r Set and reset by software."
bit_offset: 24
bit_size: 1
- name: BKPSRAMEN
description: "BKPSRAM clock enable\r Set and reset by software."
bit_offset: 28
bit_size: 1
- name: DCACHE1EN
description: "DCACHE1 clock enable\r Set and reset by software.\r Note: DCACHE1 clock must be enabled when external memories are accessed through OCTOSPI1, OCTOSPI2 or FSMC, even if the DCACHE1 is bypassed."
bit_offset: 30
bit_size: 1
- name: SRAM1EN
description: "SRAM1 clock enable\r Set and reset by software."
bit_offset: 31
bit_size: 1
fieldset/AHB1RSTR:
description: RCC AHB1 peripheral reset register
fields:
- name: GPDMA1RST
description: "GPDMA1 reset\r Set and cleared by software."
bit_offset: 0
bit_size: 1
- name: CORDICRST
description: "CORDIC reset\r Set and cleared by software."
bit_offset: 1
bit_size: 1
- name: FMACRST
description: "FMAC reset\r Set and cleared by software."
bit_offset: 2
bit_size: 1
- name: MDF1RST
description: "MDF1 reset\r Set and cleared by software."
bit_offset: 3
bit_size: 1
- name: CRCRST
description: "CRC reset\r Set and cleared by software."
bit_offset: 12
bit_size: 1
- name: JPEGRST
description: "JPEG reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 15
bit_size: 1
- name: TSCRST
description: "TSC reset\r Set and cleared by software."
bit_offset: 16
bit_size: 1
- name: RAMCFGRST
description: "RAMCFG reset\r Set and cleared by software."
bit_offset: 17
bit_size: 1
- name: DMA2DRST
description: "DMA2D reset\r Set and cleared by software."
bit_offset: 18
bit_size: 1
- name: GFXMMURST
description: "GFXMMU reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 19
bit_size: 1
- name: GPU2DRST
description: "GPU2D reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 20
bit_size: 1
fieldset/AHB1SMENR:
description: RCC AHB1 peripheral clocks enable in Sleep and Stop modes register
fields:
- name: GPDMA1SMEN
description: "GPDMA1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 0
bit_size: 1
- name: CORDICSMEN
description: "CORDIC clocks enable during Sleep and Stop modes\r Set and cleared by software during Sleep mode."
bit_offset: 1
bit_size: 1
- name: FMACSMEN
description: "FMAC clocks enable during Sleep and Stop modes.\r Set and cleared by software."
bit_offset: 2
bit_size: 1
- name: MDF1SMEN
description: "MDF1 clocks enable during Sleep and Stop modes.\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 3
bit_size: 1
- name: FLASHSMEN
description: "FLASH clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 8
bit_size: 1
- name: CRCSMEN
description: "CRC clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 12
bit_size: 1
- name: JPEGSMEN
description: "JPEG clocks enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 15
bit_size: 1
- name: TSCSMEN
description: "TSC clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 16
bit_size: 1
- name: RAMCFGSMEN
description: "RAMCFG clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 17
bit_size: 1
- name: DMA2DSMEN
description: "DMA2D clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 18
bit_size: 1
- name: GFXMMUSMEN
description: "GFXMMU clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 19
bit_size: 1
- name: GPU2DSMEN
description: "GPU2D clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 20
bit_size: 1
- name: DCACHE2SMEN
description: "DCACHE2 clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 21
bit_size: 1
- name: GTZC1SMEN
description: "GTZC1 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 24
bit_size: 1
- name: BKPSRAMSMEN
description: "BKPSRAM clocks enable during Sleep and Stop modes\r Set and cleared by software"
bit_offset: 28
bit_size: 1
- name: ICACHESMEN
description: "ICACHE clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 29
bit_size: 1
- name: DCACHE1SMEN
description: "DCACHE1 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 30
bit_size: 1
- name: SRAM1SMEN
description: "SRAM1 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 31
bit_size: 1
fieldset/AHB2ENR1:
description: RCC AHB2 peripheral clock enable register 1
fields:
- name: GPIOAEN
description: "IO port A clock enable\r Set and cleared by software."
bit_offset: 0
bit_size: 1
- name: GPIOBEN
description: "IO port B clock enable\r Set and cleared by software."
bit_offset: 1
bit_size: 1
- name: GPIOCEN
description: "IO port C clock enable\r Set and cleared by software."
bit_offset: 2
bit_size: 1
- name: GPIODEN
description: "IO port D clock enable\r Set and cleared by software."
bit_offset: 3
bit_size: 1
- name: GPIOEEN
description: "IO port E clock enable\r Set and cleared by software."
bit_offset: 4
bit_size: 1
- name: GPIOFEN
description: "IO port F clock enable\r Set and cleared by software."
bit_offset: 5
bit_size: 1
- name: GPIOGEN
description: "IO port G clock enable\r Set and cleared by software."
bit_offset: 6
bit_size: 1
- name: GPIOHEN
description: "IO port H clock enable\r Set and cleared by software."
bit_offset: 7
bit_size: 1
- name: GPIOIEN
description: "IO port I clock enable\r Set and cleared by software."
bit_offset: 8
bit_size: 1
- name: GPIOJEN
description: "I/O port J clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 9
bit_size: 1
- name: ADC12EN
description: "ADC1 and ADC2 clock enable\r This bit is set and cleared by software.\r Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in<69>STM32U59x/5Ax/5Fx/5Gx."
bit_offset: 10
bit_size: 1
- name: DCMIEN
description: "DCMI and PSSI clock enable\r Set and cleared by software."
bit_offset: 12
bit_size: 1
- name: USB_OTG_FSEN
description: "OTG_FS clock enable\r Set and cleared by software."
bit_offset: 14
bit_size: 1
- name: USB_OTG_HSEN
description: "OTG_HS clock enable\r Set and cleared by software."
bit_offset: 14
bit_size: 1
- name: USB_OTG_HS_PHYEN
description: "OTG_HS PHY clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 15
bit_size: 1
- name: AESEN
description: "AES clock enable\r Set and cleared by software."
bit_offset: 16
bit_size: 1
- name: HASHEN
description: "HASH clock enable\r Set and cleared by software"
bit_offset: 17
bit_size: 1
- name: RNGEN
description: "RNG clock enable\r Set and cleared by software."
bit_offset: 18
bit_size: 1
- name: PKAEN
description: "PKA clock enable\r Set and cleared by software."
bit_offset: 19
bit_size: 1
- name: SAESEN
description: "SAES clock enable\r Set and cleared by software."
bit_offset: 20
bit_size: 1
- name: OCTOSPIMEN
description: "OCTOSPIM clock enable\r Set and cleared by software."
bit_offset: 21
bit_size: 1
- name: OTFDEC1EN
description: "OTFDEC1 clock enable\r Set and cleared by software."
bit_offset: 23
bit_size: 1
- name: OTFDEC2EN
description: "OTFDEC2 clock enable\r Set and cleared by software."
bit_offset: 24
bit_size: 1
- name: SDMMC1EN
description: "SDMMC1 clock enable\r Set and cleared by software."
bit_offset: 27
bit_size: 1
- name: SDMMC2EN
description: "SDMMC2 clock enable\r Set and cleared by software."
bit_offset: 28
bit_size: 1
- name: SRAM2EN
description: "SRAM2 clock enable\r Set and reset by software."
bit_offset: 30
bit_size: 1
- name: SRAM3EN
description: "SRAM3 clock enable\r Set and reset by software."
bit_offset: 31
bit_size: 1
fieldset/AHB2ENR2:
description: RCC AHB2 peripheral clock enable register 2
fields:
- name: FSMCEN
description: "FSMC clock enable\r Set and cleared by software."
bit_offset: 0
bit_size: 1
- name: OCTOSPI1EN
description: "OCTOSPI1 clock enable\r Set and cleared by software."
bit_offset: 4
bit_size: 1
- name: OCTOSPI2EN
description: "OCTOSPI2 clock enable\r Set and cleared by software."
bit_offset: 8
bit_size: 1
- name: HSPI1EN
description: "HSPI1 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 12
bit_size: 1
- name: SRAM6EN
description: "SRAM6 clock enable \r This bit is set and reset by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 30
bit_size: 1
- name: SRAM5EN
description: "SRAM5 clock enable \r This bit is set and reset by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 31
bit_size: 1
fieldset/AHB2RSTR1:
description: RCC AHB2 peripheral reset register 1
fields:
- name: GPIOARST
description: "IO port A reset\r Set and cleared by software."
bit_offset: 0
bit_size: 1
- name: GPIOBRST
description: "IO port B reset\r Set and cleared by software."
bit_offset: 1
bit_size: 1
- name: GPIOCRST
description: "IO port C reset\r Set and cleared by software."
bit_offset: 2
bit_size: 1
- name: GPIODRST
description: "IO port D reset\r Set and cleared by software."
bit_offset: 3
bit_size: 1
- name: GPIOERST
description: "IO port E reset\r Set and cleared by software."
bit_offset: 4
bit_size: 1
- name: GPIOFRST
description: "IO port F reset\r Set and cleared by software."
bit_offset: 5
bit_size: 1
- name: GPIOGRST
description: "IO port G reset\r Set and cleared by software."
bit_offset: 6
bit_size: 1
- name: GPIOHRST
description: "IO port H reset\r Set and cleared by software."
bit_offset: 7
bit_size: 1
- name: GPIOIRST
description: "IO port I reset\r Set and cleared by software."
bit_offset: 8
bit_size: 1
- name: GPIOJRST
description: "I/O port J reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 9
bit_size: 1
- name: ADC12RST
description: "ADC1 and ADC2 reset\r This bit is set and cleared by software.\r Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in<69>STM32U59x/5Ax/5Fx/5Gx."
bit_offset: 10
bit_size: 1
- name: DCMIRST
description: "DCMI and PSSI reset\r Set and cleared by software."
bit_offset: 12
bit_size: 1
- name: USB_OTG_FSRST
description: "OTG_FS reset\r Set and cleared by software."
bit_offset: 14
bit_size: 1
- name: USB_OTG_HSRST
description: "OTG_HS reset\r Set and cleared by software."
bit_offset: 14
bit_size: 1
- name: AESRST
description: "AES hardware accelerator reset\r Set and cleared by software."
bit_offset: 16
bit_size: 1
- name: HASHRST
description: "Hash reset\r Set and cleared by software."
bit_offset: 17
bit_size: 1
- name: RNGRST
description: "Random number generator reset\r Set and cleared by software."
bit_offset: 18
bit_size: 1
- name: PKARST
description: "PKA reset\r Set and cleared by software."
bit_offset: 19
bit_size: 1
- name: SAESRST
description: "SAES hardware accelerator reset\r Set and cleared by software."
bit_offset: 20
bit_size: 1
- name: OCTOSPIMRST
description: "OCTOSPIM reset\r Set and cleared by software."
bit_offset: 21
bit_size: 1
- name: OTFDEC1RST
description: "OTFDEC1 reset\r Set and cleared by software."
bit_offset: 23
bit_size: 1
- name: OTFDEC2RST
description: "OTFDEC2 reset\r Set and cleared by software."
bit_offset: 24
bit_size: 1
- name: SDMMC1RST
description: "SDMMC1 reset\r Set and cleared by software."
bit_offset: 27
bit_size: 1
- name: SDMMC2RST
description: "SDMMC2 reset\r Set and cleared by software."
bit_offset: 28
bit_size: 1
fieldset/AHB2RSTR2:
description: RCC AHB2 peripheral reset register 2
fields:
- name: FSMCRST
description: "Flexible memory controller reset\r Set and cleared by software."
bit_offset: 0
bit_size: 1
- name: OCTOSPI1RST
description: "OCTOSPI1 reset\r Set and cleared by software."
bit_offset: 4
bit_size: 1
- name: OCTOSPI2RST
description: "OCTOSPI2 reset\r Set and cleared by software."
bit_offset: 8
bit_size: 1
- name: HSPI1RST
description: "HSPI1 reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 12
bit_size: 1
fieldset/AHB2SMENR1:
description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 1"
fields:
- name: GPIOASMEN
description: "IO port A clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 0
bit_size: 1
- name: GPIOBSMEN
description: "IO port B clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 1
bit_size: 1
- name: GPIOCSMEN
description: "IO port C clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 2
bit_size: 1
- name: GPIODSMEN
description: "IO port D clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 3
bit_size: 1
- name: GPIOESMEN
description: "IO port E clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 4
bit_size: 1
- name: GPIOFSMEN
description: "IO port F clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 5
bit_size: 1
- name: GPIOGSMEN
description: "IO port G clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 6
bit_size: 1
- name: GPIOHSMEN
description: "IO port H clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 7
bit_size: 1
- name: GPIOISMEN
description: "IO port I clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 8
bit_size: 1
- name: GPIOJSMEN
description: "I/O port J clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 9
bit_size: 1
- name: ADC12SMEN
description: "ADC1 and ADC2 clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit impacts ADC1 in STM32U535/545/575/585 and ADC1/ADC2 in<69>STM32U59x/5Ax/5Fx/5Gx."
bit_offset: 10
bit_size: 1
- name: DCMISMEN
description: "DCMI and PSSI clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 12
bit_size: 1
- name: USB_OTG_FSSMEN
description: "OTG_FS clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 14
bit_size: 1
- name: USB_OTG_HSSMEN
description: "OTG_HS clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 14
bit_size: 1
- name: USB_OTG_HS_PHYSMEN
description: "OTG_HS PHY clock enable during Sleep and Stop modes\r This bit is set and cleared by software\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 15
bit_size: 1
- name: AESSMEN
description: "AES clock enable during Sleep and Stop modes\r Set and cleared by software"
bit_offset: 16
bit_size: 1
- name: HASHSMEN
description: "HASH clock enable during Sleep and Stop modes\r Set and cleared by software"
bit_offset: 17
bit_size: 1
- name: RNGSMEN
description: "Random number generator (RNG) clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 18
bit_size: 1
- name: PKASMEN
description: "PKA clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 19
bit_size: 1
- name: SAESSMEN
description: "SAES accelerator clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 20
bit_size: 1
- name: OCTOSPIMSMEN
description: "OCTOSPIM clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 21
bit_size: 1
- name: OTFDEC1SMEN
description: "OTFDEC1 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 23
bit_size: 1
- name: OTFDEC2SMEN
description: "OTFDEC2 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 24
bit_size: 1
- name: SDMMC1SMEN
description: "SDMMC1 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 27
bit_size: 1
- name: SDMMC2SMEN
description: "SDMMC2 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 28
bit_size: 1
- name: SRAM2SMEN
description: "SRAM2 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 30
bit_size: 1
- name: SRAM3SMEN
description: "SRAM3 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 31
bit_size: 1
fieldset/AHB2SMENR2:
description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 2"
fields:
- name: FSMCSMEN
description: "FSMC clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 0
bit_size: 1
- name: OCTOSPI1SMEN
description: "OCTOSPI1 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 4
bit_size: 1
- name: OCTOSPI2SMEN
description: "OCTOSPI2 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 8
bit_size: 1
- name: HSPI1SMEN
description: "HSPI1 clock enable during Sleep and Stop modes \r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 12
bit_size: 1
- name: SRAM6SMEN
description: "SRAM6 clock enable during Sleep and Stop modes \r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 30
bit_size: 1
- name: SRAM5SMEN
description: "SRAM5 clock enable during Sleep and Stop modes \r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 31
bit_size: 1
fieldset/AHB3ENR:
description: RCC AHB3 peripheral clock enable register
fields:
- name: LPGPIO1EN
description: "LPGPIO1 enable\r Set and cleared by software."
bit_offset: 0
bit_size: 1
- name: PWREN
description: "PWR clock enable\r Set and cleared by software."
bit_offset: 2
bit_size: 1
- name: ADC4EN
description: "ADC4 clock enable\r Set and cleared by software."
bit_offset: 5
bit_size: 1
- name: DAC1EN
description: "DAC1 clock enable\r Set and cleared by software."
bit_offset: 6
bit_size: 1
- name: LPDMA1EN
description: "LPDMA1 clock enable\r Set and cleared by software."
bit_offset: 9
bit_size: 1
- name: ADF1EN
description: "ADF1 clock enable\r Set and cleared by software."
bit_offset: 10
bit_size: 1
- name: GTZC2EN
description: "GTZC2 clock enable\r Set and cleared by software."
bit_offset: 12
bit_size: 1
- name: SRAM4EN
description: "SRAM4 clock enable\r Set and reset by software."
bit_offset: 31
bit_size: 1
fieldset/AHB3RSTR:
description: RCC AHB3 peripheral reset register
fields:
- name: LPGPIO1RST
description: "LPGPIO1 reset\r Set and cleared by software."
bit_offset: 0
bit_size: 1
- name: ADC4RST
description: "ADC4 reset\r Set and cleared by software."
bit_offset: 5
bit_size: 1
- name: DAC1RST
description: "DAC1 reset\r Set and cleared by software."
bit_offset: 6
bit_size: 1
- name: LPDMA1RST
description: "LPDMA1 reset\r Set and cleared by software."
bit_offset: 9
bit_size: 1
- name: ADF1RST
description: "ADF1 reset\r Set and cleared by software."
bit_offset: 10
bit_size: 1
fieldset/AHB3SMENR:
description: RCC AHB3 peripheral clocks enable in Sleep and Stop modes register
fields:
- name: LPGPIO1SMEN
description: "LPGPIO1 enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 0
bit_size: 1
- name: PWRSMEN
description: "PWR clock enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 2
bit_size: 1
- name: ADC4SMEN
description: "ADC4 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 5
bit_size: 1
- name: DAC1SMEN
description: "DAC1 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 6
bit_size: 1
- name: LPDMA1SMEN
description: "LPDMA1 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 9
bit_size: 1
- name: ADF1SMEN
description: "ADF1 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 10
bit_size: 1
- name: GTZC2SMEN
description: "GTZC2 clock enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 12
bit_size: 1
- name: SRAM4SMEN
description: "SRAM4 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 31
bit_size: 1
fieldset/APB1ENR1:
description: RCC APB1 peripheral clock enable register 1
fields:
- name: TIM2EN
description: "TIM2 clock enable\r Set and cleared by software."
bit_offset: 0
bit_size: 1
- name: TIM3EN
description: "TIM3 clock enable\r Set and cleared by software."
bit_offset: 1
bit_size: 1
- name: TIM4EN
description: "TIM4 clock enable\r Set and cleared by software."
bit_offset: 2
bit_size: 1
- name: TIM5EN
description: "TIM5 clock enable\r Set and cleared by software."
bit_offset: 3
bit_size: 1
- name: TIM6EN
description: "TIM6 clock enable\r Set and cleared by software."
bit_offset: 4
bit_size: 1
- name: TIM7EN
description: "TIM7 clock enable\r Set and cleared by software."
bit_offset: 5
bit_size: 1
- name: WWDGEN
description: "WWDG clock enable\r Set by software to enable the window watchdog clock. Reset by hardware system reset.\r This bit can also be set by hardware if the WWDG_SW option bit is reset."
bit_offset: 11
bit_size: 1
- name: SPI2EN
description: "SPI2 clock enable\r Set and cleared by software."
bit_offset: 14
bit_size: 1
- name: USART2EN
description: "USART2 clock enable\r Set and cleared by software."
bit_offset: 17
bit_size: 1
- name: USART3EN
description: "USART3 clock enable\r Set and cleared by software."
bit_offset: 18
bit_size: 1
- name: UART4EN
description: "UART4 clock enable\r Set and cleared by software."
bit_offset: 19
bit_size: 1
- name: UART5EN
description: "UART5 clock enable\r Set and cleared by software."
bit_offset: 20
bit_size: 1
- name: I2C1EN
description: "I2C1 clock enable\r Set and cleared by software."
bit_offset: 21
bit_size: 1
- name: I2C2EN
description: "I2C2 clock enable\r Set and cleared by software."
bit_offset: 22
bit_size: 1
- name: CRSEN
description: "CRS clock enable\r Set and cleared by software."
bit_offset: 24
bit_size: 1
- name: USART6EN
description: "USART6 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 25
bit_size: 1
fieldset/APB1ENR2:
description: RCC APB1 peripheral clock enable register 2
fields:
- name: I2C4EN
description: "I2C4 clock enable\r Set and cleared by software"
bit_offset: 1
bit_size: 1
- name: LPTIM2EN
description: "LPTIM2 clock enable\r Set and cleared by software."
bit_offset: 5
bit_size: 1
- name: I2C5EN
description: "I2C5 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 6
bit_size: 1
- name: I2C6EN
description: "I2C6 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 7
bit_size: 1
- name: FDCAN1EN
description: "FDCAN1 clock enable\r Set and cleared by software."
bit_offset: 9
bit_size: 1
- name: UCPD1EN
description: "UCPD1 clock enable\r Set and cleared by software."
bit_offset: 23
bit_size: 1
fieldset/APB1RSTR1:
description: RCC APB1 peripheral reset register 1
fields:
- name: TIM2RST
description: "TIM2 reset\r Set and cleared by software."
bit_offset: 0
bit_size: 1
- name: TIM3RST
description: "TIM3 reset\r Set and cleared by software."
bit_offset: 1
bit_size: 1
- name: TIM4RST
description: "TIM4 reset\r Set and cleared by software."
bit_offset: 2
bit_size: 1
- name: TIM5RST
description: "TIM5 reset\r Set and cleared by software."
bit_offset: 3
bit_size: 1
- name: TIM6RST
description: "TIM6 reset\r Set and cleared by software."
bit_offset: 4
bit_size: 1
- name: TIM7RST
description: "TIM7 reset\r Set and cleared by software."
bit_offset: 5
bit_size: 1
- name: SPI2RST
description: "SPI2 reset\r Set and cleared by software."
bit_offset: 14
bit_size: 1
- name: USART2RST
description: "USART2 reset\r Set and cleared by software."
bit_offset: 17
bit_size: 1
- name: USART3RST
description: "USART3 reset\r Set and cleared by software."
bit_offset: 18
bit_size: 1
- name: UART4RST
description: "UART4 reset\r Set and cleared by software."
bit_offset: 19
bit_size: 1
- name: UART5RST
description: "UART5 reset\r Set and cleared by software."
bit_offset: 20
bit_size: 1
- name: I2C1RST
description: "I2C1 reset\r Set and cleared by software."
bit_offset: 21
bit_size: 1
- name: I2C2RST
description: "I2C2 reset\r Set and cleared by software."
bit_offset: 22
bit_size: 1
- name: CRSRST
description: "CRS reset\r Set and cleared by software."
bit_offset: 24
bit_size: 1
- name: USART6RST
description: "USART6 reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 25
bit_size: 1
fieldset/APB1RSTR2:
description: RCC APB1 peripheral reset register 2
fields:
- name: I2C4RST
description: "I2C4 reset\r Set and cleared by software"
bit_offset: 1
bit_size: 1
- name: LPTIM2RST
description: "LPTIM2 reset\r Set and cleared by software."
bit_offset: 5
bit_size: 1
- name: I2C5RST
description: "I2C5 reset\r This bit is set and cleared by software\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 6
bit_size: 1
- name: I2C6RST
description: "I2C6 reset\r This bit is set and cleared by software\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 7
bit_size: 1
- name: FDCAN1RST
description: "FDCAN1 reset\r Set and cleared by software."
bit_offset: 9
bit_size: 1
- name: UCPD1RST
description: "UCPD1 reset\r Set and cleared by software."
bit_offset: 23
bit_size: 1
fieldset/APB1SMENR1:
description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes\tregister 1"
fields:
- name: TIM2SMEN
description: "TIM2 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 0
bit_size: 1
- name: TIM3SMEN
description: "TIM3 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 1
bit_size: 1
- name: TIM4SMEN
description: "TIM4 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 2
bit_size: 1
- name: TIM5SMEN
description: "TIM5 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 3
bit_size: 1
- name: TIM6SMEN
description: "TIM6 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 4
bit_size: 1
- name: TIM7SMEN
description: "TIM7 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 5
bit_size: 1
- name: WWDGSMEN
description: "Window watchdog clocks enable during Sleep and Stop modes\r Set and cleared by software. This bit is forced to 1 by hardware when the hardware WWDG option is activated."
bit_offset: 11
bit_size: 1
- name: SPI2SMEN
description: "SPI2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 14
bit_size: 1
- name: USART2SMEN
description: "USART2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 17
bit_size: 1
- name: USART3SMEN
description: "USART3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 18
bit_size: 1
- name: UART4SMEN
description: "UART4 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 19
bit_size: 1
- name: UART5SMEN
description: "UART5 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 20
bit_size: 1
- name: I2C1SMEN
description: "I2C1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 21
bit_size: 1
- name: I2C2SMEN
description: "I2C2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 22
bit_size: 1
- name: CRSSMEN
description: "CRS clock enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 24
bit_size: 1
- name: USART6SMEN
description: "USART6 clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 25
bit_size: 1
fieldset/APB1SMENR2:
description: "RCC APB1 peripheral clocks enable in Sleep and\tStop modes register 2"
fields:
- name: I2C4SMEN
description: "I2C4 clocks enable during Sleep and Stop modes\r Set and cleared by software\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 1
bit_size: 1
- name: LPTIM2SMEN
description: "LPTIM2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 5
bit_size: 1
- name: I2C5SMEN
description: "I2C5 clock enable during Sleep and Stop modes\r This bit is set and cleared by software\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 6
bit_size: 1
- name: I2C6SMEN
description: "I2C6 clock enable during Sleep and Stop modes\r This bit is set and cleared by software\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 7
bit_size: 1
- name: FDCAN1SMEN
description: "FDCAN1 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 9
bit_size: 1
- name: UCPD1SMEN
description: "UCPD1 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 23
bit_size: 1
fieldset/APB2ENR:
description: RCC APB2 peripheral clock enable register
fields:
- name: TIM1EN
description: "TIM1 clock enable\r Set and cleared by software."
bit_offset: 11
bit_size: 1
- name: SPI1EN
description: "SPI1 clock enable\r Set and cleared by software."
bit_offset: 12
bit_size: 1
- name: TIM8EN
description: "TIM8 clock enable\r Set and cleared by software."
bit_offset: 13
bit_size: 1
- name: USART1EN
description: "USART1clock enable\r Set and cleared by software."
bit_offset: 14
bit_size: 1
- name: TIM15EN
description: "TIM15 clock enable\r Set and cleared by software."
bit_offset: 16
bit_size: 1
- name: TIM16EN
description: "TIM16 clock enable\r Set and cleared by software."
bit_offset: 17
bit_size: 1
- name: TIM17EN
description: "TIM17 clock enable\r Set and cleared by software."
bit_offset: 18
bit_size: 1
- name: SAI1EN
description: "SAI1 clock enable\r Set and cleared by software."
bit_offset: 21
bit_size: 1
- name: SAI2EN
description: "SAI2 clock enable\r Set and cleared by software."
bit_offset: 22
bit_size: 1
- name: USBEN
description: "USB clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 24
bit_size: 1
- name: GFXTIMEN
description: "GFXTIM clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 25
bit_size: 1
- name: LTDCEN
description: "LTDC clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 26
bit_size: 1
- name: DSIEN
description: "DSI clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 27
bit_size: 1
fieldset/APB2RSTR:
description: RCC APB2 peripheral reset register
fields:
- name: TIM1RST
description: "TIM1 reset\r Set and cleared by software."
bit_offset: 11
bit_size: 1
- name: SPI1RST
description: "SPI1 reset\r Set and cleared by software."
bit_offset: 12
bit_size: 1
- name: TIM8RST
description: "TIM8 reset\r Set and cleared by software."
bit_offset: 13
bit_size: 1
- name: USART1RST
description: "USART1 reset\r Set and cleared by software."
bit_offset: 14
bit_size: 1
- name: TIM15RST
description: "TIM15 reset\r Set and cleared by software."
bit_offset: 16
bit_size: 1
- name: TIM16RST
description: "TIM16 reset\r Set and cleared by software."
bit_offset: 17
bit_size: 1
- name: TIM17RST
description: "TIM17 reset\r Set and cleared by software."
bit_offset: 18
bit_size: 1
- name: SAI1RST
description: "SAI1 reset\r Set and cleared by software."
bit_offset: 21
bit_size: 1
- name: SAI2RST
description: "SAI2 reset\r Set and cleared by software."
bit_offset: 22
bit_size: 1
- name: USBRST
description: "USB reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 24
bit_size: 1
- name: GFXTIMRST
description: "GFXTIM reset\r This bit is set and cleared by software.\r Note: .This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 25
bit_size: 1
- name: LTDCRST
description: "LTDC reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 26
bit_size: 1
- name: DSIRST
description: "DSI reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 27
bit_size: 1
fieldset/APB2SMENR:
description: RCC APB2 peripheral clocks enable in Sleep and Stop modes register
fields:
- name: TIM1SMEN
description: "TIM1 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 11
bit_size: 1
- name: SPI1SMEN
description: "SPI1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 12
bit_size: 1
- name: TIM8SMEN
description: "TIM8 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 13
bit_size: 1
- name: USART1SMEN
description: "USART1clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 14
bit_size: 1
- name: TIM15SMEN
description: "TIM15 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 16
bit_size: 1
- name: TIM16SMEN
description: "TIM16 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 17
bit_size: 1
- name: TIM17SMEN
description: "TIM17 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 18
bit_size: 1
- name: SAI1SMEN
description: "SAI1 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 21
bit_size: 1
- name: SAI2SMEN
description: "SAI2 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 22
bit_size: 1
- name: USBSMEN
description: "USB clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 24
bit_size: 1
- name: GFXTIMSMEN
description: "GFXTIM clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 25
bit_size: 1
- name: LTDCSMEN
description: "LTDC clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 26
bit_size: 1
- name: DSISMEN
description: "DSI clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 27
bit_size: 1
fieldset/APB3ENR:
description: RCC APB3 peripheral clock enable register
fields:
- name: SYSCFGEN
description: "SYSCFG clock enable\r Set and cleared by software."
bit_offset: 1
bit_size: 1
- name: SPI3EN
description: "SPI3 clock enable\r Set and cleared by software."
bit_offset: 5
bit_size: 1
- name: LPUART1EN
description: "LPUART1 clock enable\r Set and cleared by software."
bit_offset: 6
bit_size: 1
- name: I2C3EN
description: "I2C3 clock enable\r Set and cleared by software."
bit_offset: 7
bit_size: 1
- name: LPTIM1EN
description: "LPTIM1 clock enable\r Set and cleared by software."
bit_offset: 11
bit_size: 1
- name: LPTIM3EN
description: "LPTIM3 clock enable\r Set and cleared by software."
bit_offset: 12
bit_size: 1
- name: LPTIM4EN
description: "LPTIM4 clock enable\r Set and cleared by software."
bit_offset: 13
bit_size: 1
- name: OPAMPEN
description: "OPAMP clock enable\r Set and cleared by software."
bit_offset: 14
bit_size: 1
- name: COMPEN
description: "COMP clock enable\r Set and cleared by software."
bit_offset: 15
bit_size: 1
- name: VREFEN
description: "VREFBUF clock enable\r Set and cleared by software."
bit_offset: 20
bit_size: 1
- name: RTCAPBEN
description: "RTC and TAMP APB clock enable\r Set and cleared by software."
bit_offset: 21
bit_size: 1
fieldset/APB3RSTR:
description: RCC APB3 peripheral reset register
fields:
- name: SYSCFGRST
description: "SYSCFG reset\r Set and cleared by software."
bit_offset: 1
bit_size: 1
- name: SPI3RST
description: "SPI3 reset\r Set and cleared by software."
bit_offset: 5
bit_size: 1
- name: LPUART1RST
description: "LPUART1 reset\r Set and cleared by software."
bit_offset: 6
bit_size: 1
- name: I2C3RST
description: "I2C3 reset\r Set and cleared by software."
bit_offset: 7
bit_size: 1
- name: LPTIM1RST
description: "LPTIM1 reset\r Set and cleared by software."
bit_offset: 11
bit_size: 1
- name: LPTIM3RST
description: "LPTIM3 reset\r Set and cleared by software."
bit_offset: 12
bit_size: 1
- name: LPTIM4RST
description: "LPTIM4 reset\r Set and cleared by software."
bit_offset: 13
bit_size: 1
- name: OPAMPRST
description: "OPAMP reset\r Set and cleared by software."
bit_offset: 14
bit_size: 1
- name: COMPRST
description: "COMP reset\r Set and cleared by software."
bit_offset: 15
bit_size: 1
- name: VREFRST
description: "VREFBUF reset\r Set and cleared by software."
bit_offset: 20
bit_size: 1
fieldset/APB3SMENR:
description: RCC APB3 peripheral clock enable in Sleep and Stop modes register
fields:
- name: SYSCFGSMEN
description: "SYSCFG clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 1
bit_size: 1
- name: SPI3SMEN
description: "SPI3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 5
bit_size: 1
- name: LPUART1SMEN
description: "LPUART1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 6
bit_size: 1
- name: I2C3SMEN
description: "I2C3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 7
bit_size: 1
- name: LPTIM1SMEN
description: "LPTIM1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 11
bit_size: 1
- name: LPTIM3SMEN
description: "LPTIM3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 12
bit_size: 1
- name: LPTIM4SMEN
description: "LPTIM4 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 13
bit_size: 1
- name: OPAMPSMEN
description: "OPAMP clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 14
bit_size: 1
- name: COMPSMEN
description: "COMP clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 15
bit_size: 1
- name: VREFSMEN
description: "VREFBUF clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 20
bit_size: 1
- name: RTCAPBSMEN
description: "RTC and TAMP APB clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 21
bit_size: 1
fieldset/BDCR:
description: RCC Backup domain control register
fields:
- name: LSEON
description: "LSE oscillator enable\r Set and cleared by software."
bit_offset: 0
bit_size: 1
- name: LSERDY
description: "LSE oscillator ready\r Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles."
bit_offset: 1
bit_size: 1
- name: LSEBYP
description: "LSE oscillator bypass\r Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0)."
bit_offset: 2
bit_size: 1
- name: LSEDRV
description: "LSE oscillator drive capability\r Set by software to modulate the drive capability of the LSE oscillator. This field can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0).\r Note: The oscillator is in 'Xtal mode when it is not in bypass mode."
bit_offset: 3
bit_size: 2
enum: LSEDRV
- name: LSECSSON
description: "CSS on LSE enable\r Set by software to enable the CSS on LSE. LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected.\r Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case, the software must disable the LSECSSON bit."
bit_offset: 5
bit_size: 1
- name: LSECSSD
description: "CSS on LSE failure Detection\r Set by hardware to indicate when a failure is detected by the CCS on the external 32 kHz oscillator (LSE)."
bit_offset: 6
bit_size: 1
- name: LSESYSEN
description: "LSE system clock (LSESYS) enable\r Set by software to enable always the LSE system clock generated by RCC. This clock can be used by any peripheral when its source clock is the LSE or at system level in case of one of the LSCOSEL, MCO, MSI PLL mode or CSS on LSE is needed.\r The LSESYS clock can be generated even if LSESYSEN= 0 if the LSE clock is requested by the CSS on LSE, by a peripheral or any other source clock using LSE."
bit_offset: 7
bit_size: 1
- name: RTCSEL
description: "RTC and TAMP clock source selection\r Set by software to select the clock source for the RTC and TAMP . Once the RTC and TAMP clock source has been selected, it cannot be changed anymore unless the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them."
bit_offset: 8
bit_size: 2
enum: RTCSEL
- name: LSESYSRDY
description: "LSE system clock (LSESYS) ready\r Set and cleared by hardware to indicate when the LSE system clock is stable.When the LSESYSEN bit is set, the LSESYSRDY flag is set after two LSE clock cycles.\r The LSE clock must be already enabled and stable (LSEON and LSERDY are set).\r When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles."
bit_offset: 11
bit_size: 1
- name: LSEGFON
description: "LSE clock glitch filter enable\r Set and cleared by hardware to enable the LSE glitch filter. This bit can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0)"
bit_offset: 12
bit_size: 1
- name: RTCEN
description: "RTC and TAMP clock enable\r Set and cleared by software."
bit_offset: 15
bit_size: 1
- name: BDRST
description: "Backup domain software reset\r Set and cleared by software."
bit_offset: 16
bit_size: 1
- name: LSCOEN
description: "Low-speed clock output (LSCO) enable\r Set and cleared by software."
bit_offset: 24
bit_size: 1
- name: LSCOSEL
description: "Low-speed clock output selection\r Set and cleared by software."
bit_offset: 25
bit_size: 1
enum: LSCOSEL
- name: LSION
description: "LSI oscillator enable\r Set and cleared by software."
bit_offset: 26
bit_size: 1
- name: LSIRDY
description: "LSI oscillator ready\r Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0."
bit_offset: 27
bit_size: 1
- name: LSIPREDIV
description: "Low-speed clock divider configuration\r Set and cleared by software to enable the LSI division. This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). If the LSI was previously enabled, it is necessary to wait for at least 60 μs after clearing LSION bit (synchronization time for LSI to be really disabled), before writing LSIPREDIV. The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC."
bit_offset: 28
bit_size: 1
enum: LSIPREDIV
fieldset/CCIPR1:
description: RCC peripherals independent clock configuration register 1
fields:
- name: USART1SEL
description: "USART1 kernel clock source selection\r This bits are used to select the USART1 kernel clock source.\r Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE."
bit_offset: 0
bit_size: 2
enum: USARTSEL
- name: USART2SEL
description: "USART2 kernel clock source selection\r This bits are used to select the USART2 kernel clock source.\r Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE."
bit_offset: 2
bit_size: 2
enum: USARTSEL
- name: USART3SEL
description: "USART3 kernel clock source selection\r This bits are used to select the USART3 kernel clock source.\r Note: The USART3 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE."
bit_offset: 4
bit_size: 2
enum: USARTSEL
- name: UART4SEL
description: "UART4 kernel clock source selection\r This bits are used to select the UART4 kernel clock source.\r Note: The UART4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE."
bit_offset: 6
bit_size: 2
enum: UARTSEL
- name: UART5SEL
description: "UART5 kernel clock source selection\r These bits are used to select the UART5 kernel clock source.\r Note: The UART5 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE."
bit_offset: 8
bit_size: 2
enum: UARTSEL
- name: I2C1SEL
description: "I2C1 kernel clock source selection\r These bits are used to select the I2C1 kernel clock source.\r Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK."
bit_offset: 10
bit_size: 2
enum: ICSEL
- name: I2C2SEL
description: "I2C2 kernel clock source selection\r These bits are used to select the I2C2 kernel clock source.\r Note: The I2C2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK."
bit_offset: 12
bit_size: 2
enum: ICSEL
- name: I2C4SEL
description: "I2C4 kernel clock source selection\r These bits are used to select the I2C4 kernel clock source.\r Note: The I2C4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK."
bit_offset: 14
bit_size: 2
enum: ICSEL
- name: SPI2SEL
description: "SPI2 kernel clock source selection\r These bits are used to select the SPI2 kernel clock source.\r Note: The SPI2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK."
bit_offset: 16
bit_size: 2
enum: SPISEL
- name: LPTIM2SEL
description: "Low-power timer 2 kernel clock source selection\r These bits are used to select the LPTIM2 kernel clock source.\r Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI if HSIKERON = 1."
bit_offset: 18
bit_size: 2
enum: LPTIMSEL
- name: SPI1SEL
description: "SPI1 kernel clock source selection\r These bits are used to select the SPI1 kernel clock source.\r Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK."
bit_offset: 20
bit_size: 2
enum: SPISEL
- name: SYSTICKSEL
description: "SysTick clock source selection\r These bits are used to select the SysTick clock source.\r Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one HCLK cycle is introduced, due to the LSE or LSI sampling with HCLK in the SysTick circuitry."
bit_offset: 22
bit_size: 2
enum: SYSTICKSEL
- name: FDCAN1SEL
description: "FDCAN1 kernel clock source selection\r These bits are used to select the FDCAN1 kernel clock source."
bit_offset: 24
bit_size: 2
enum: FDCANSEL
- name: ICLKSEL
description: "intermediate clock source selection\r These bits are used to select the clock source used by OTG_FS and SDMMC."
bit_offset: 26
bit_size: 2
enum: ICLKSEL
- name: TIMICSEL
description: "Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture\r When the TIMICSEL2 bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected either to HSI/256, MSI/4 or MSI/1024. Depending on TIMICSEL[1:0] value, MSI is either MSIK or MSIS.\r When TIMICSEL2 is cleared, the HSI, MSIK and MSIS clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture.\r 0xx: HSI, MSIK and MSIS dividers disabled\r Note: The clock division must be disabled (TIMICSEL configured to 0xx) before selecting or changing a clock sources division."
bit_offset: 29
bit_size: 3
enum: TIMICSEL
fieldset/CCIPR2:
description: RCC peripherals independent clock configuration register 2
fields:
- name: MDF1SEL
description: "MDF1 kernel clock source selection\r These bits are used to select the MDF1 kernel clock source.\r others: reserved"
bit_offset: 0
bit_size: 3
enum: MDFSEL
- name: SAI1SEL
description: "SAI1 kernel clock source selection\r These bits are used to select the SAI1 kernel clock source.\r others: reserved\r Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible."
bit_offset: 5
bit_size: 3
enum: SAISEL
- name: SAI2SEL
description: "SAI2 kernel clock source selection\r These bits are used to select the SAI2 kernel clock source.\r others: reserved\r Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible."
bit_offset: 8
bit_size: 3
enum: SAISEL
- name: SAESSEL
description: "SAES kernel clock source selection\r This bit is used to select the SAES kernel clock source."
bit_offset: 11
bit_size: 1
enum: SAESSEL
- name: RNGSEL
description: "RNGSEL kernel clock source selection\r These bits are used to select the RNG kernel clock source."
bit_offset: 12
bit_size: 2
enum: RNGSEL
- name: SDMMCSEL
description: "SDMMC1 and SDMMC2 kernel clock source selection\r This bit is used to select the SDMMC kernel clock source. It is recommended to change this bit only after reset and before enabling the SDMMC."
bit_offset: 14
bit_size: 1
enum: SDMMCSEL
- name: DSISEL
description: "DSI kernel clock source selection\r This bit is used to select the DSI kernel clock source.\r This bit is only available on some devices in the STM32U5 Series. \r Refer to the device datasheet for availability of its associated peripheral. \r Note: If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 15
bit_size: 1
enum: DSISEL
- name: USART6SEL
description: "USART6 kernel clock source selection\r These bits are used to select the USART6 kernel clock source.\r The USART6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI or LSE.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."
bit_offset: 16
bit_size: 2
enum: USARTSEL
- name: LTDCSEL
description: "LTDC kernel clock source selection\r This bit is used to select the LTDC kernel clock source.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
bit_offset: 18
bit_size: 1
enum: LTDCSEL
- name: OCTOSPISEL
description: "OCTOSPI1 and OCTOSPI2 kernel clock source selection\r These bits are used to select the OCTOSPI1 and OCTOSPI2 kernel clock source."
bit_offset: 20
bit_size: 2
enum: OCTOSPISEL
- name: HSPI1SEL
description: "HSPI1 kernel clock source selection\r These bits are used to select the HSPI1 kernel clock source.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."
bit_offset: 22
bit_size: 2
enum: HSPISEL
- name: I2C5SEL
description: "I2C5 kernel clock source selection\r These bits are used to select the I2C5 kernel clock source.\r The I2C5 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI<53>or MSIK.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."
bit_offset: 24
bit_size: 2
enum: ICSEL
- name: I2C6SEL
description: "I2C6 kernel clock source selection\r These bits are used to select the I2C6 kernel clock source.\r The I2C6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI<53>or MSIK.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."
bit_offset: 26
bit_size: 2
enum: ICSEL
- name: OTGHSSEL
description: "OTG_HS PHY kernel clock source selection\r These bits are used to select the OTG_HS PHY kernel clock source.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."
bit_offset: 30
bit_size: 2
enum: OTGHSSEL
fieldset/CCIPR3:
description: RCC peripherals independent clock configuration register 3
fields:
- name: LPUART1SEL
description: "LPUART1 kernel clock source selection\r These bits are used to select the LPUART1 kernel clock source.\r others: reserved\r Note: The LPUART1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI, LSE or MSIK."
bit_offset: 0
bit_size: 3
enum: LPUARTSEL
- name: SPI3SEL
description: "SPI3 kernel clock source selection\r These bits are used to select the SPI3 kernel clock source.\r Note: The SPI3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK."
bit_offset: 3
bit_size: 2
enum: SPISEL
- name: I2C3SEL
description: "I2C3 kernel clock source selection\r These bits are used to select the I2C3 kernel clock source.\r Note: The I2C3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK."
bit_offset: 6
bit_size: 2
enum: ICSEL
- name: LPTIM34SEL
description: "LPTIM3 and LPTIM4 kernel clock source selection\r These bits are used to select the LPTIM3 and LPTIM4 kernel clock source.\r Note: The LPTIM3 and LPTIM4 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI with HSIKERON = 1 or MSIK with MSIKERON = 1."
bit_offset: 8
bit_size: 2
enum: LPTIMSEL
- name: LPTIM1SEL
description: "LPTIM1 kernel clock source selection\r These bits are used to select the LPTIM1 kernel clock source.\r Note: The LPTIM1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI with HSIKERON = 1 or MSIK with MSIKERON = 1."
bit_offset: 10
bit_size: 2
enum: LPTIMSEL
- name: ADCDACSEL
description: "ADC1, ADC4 and DAC1 kernel clock source selection\r These bits are used to select the ADC1, ADC4 and DAC1 kernel clock source.\r others: reserved\r Note: The ADC1, ADC4 and DAC1 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK (only ADC4 and DAC1 are functional in Stop 2 mode)."
bit_offset: 12
bit_size: 3
enum: ADCDACSEL
- name: DAC1SEL
description: "DAC1 sample and hold clock source selection\r This bit is used to select the DAC1 sample and hold clock source."
bit_offset: 15
bit_size: 1
enum: DACSEL
- name: ADF1SEL
description: "ADF1 kernel clock source selection\r These bits are used to select the ADF1 kernel clock source.\r others: reserved\r Note: The ADF1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is AUDIOCLK or MSIK."
bit_offset: 16
bit_size: 3
enum: ADFSEL
fieldset/CFGR1:
description: RCC clock configuration register 1
fields:
- name: SW
description: "system clock switch\r Set and cleared by software to select system clock source (SYSCLK).\r Configured by hardware to force MSIS oscillator selection when exiting Standby or Shutdown mode. Configured by hardware to force MSIS or HSI oscillator selection when exiting Stop mode or in case of HSE oscillator failure, depending on STOPWUCK value."
bit_offset: 0
bit_size: 2
enum: SW
- name: SWS
description: "system clock switch status\r Set and cleared by hardware to indicate which clock source is used as system clock."
bit_offset: 2
bit_size: 2
enum: SW
- name: STOPWUCK
description: "wakeup from Stop and CSS backup clock selection\r Set and cleared by software to select the system clock used when exiting Stop mode.\r The selected clock is also used as emergency clock for the clock security system on HSE. Warning: STOPWUCK must not be modified when the CSS is enabled by HSECSSON bit in RCC_CR and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW = 10)."
bit_offset: 4
bit_size: 1
enum: STOPWUCK
- name: STOPKERWUCK
description: "wakeup from Stop kernel clock automatic enable selection\r Set and cleared by software to enable automatically another oscillator when exiting Stop mode. This oscillator can be used as independent kernel clock by peripherals."
bit_offset: 5
bit_size: 1
enum: STOPKERWUCK
- name: MCOSEL
description: "microcontroller clock output\r Set and cleared by software.\r Others: reserved\r Note: This clock output may have some truncated cycles at startup or during MCO clock source switching."
bit_offset: 24
bit_size: 4
enum: MCOSEL
- name: MCOPRE
description: "microcontroller clock output prescaler\r Set and cleared by software.\r It is highly recommended to change this prescaler before MCO output is enabled.\r Others: not allowed"
bit_offset: 28
bit_size: 3
enum: MCOPRE
fieldset/CFGR2:
description: RCC clock configuration register 2
fields:
- name: HPRE
description: "AHB prescaler\r Set and cleared by software to control the division factor of the AHB clock (HCLK).\r Depending on the device voltage range, the software must set these bits correctly to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to ). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account.\r 0xxx: SYSCLK not divided"
bit_offset: 0
bit_size: 4
enum: HPRE
- name: PPRE1
description: "APB1 prescaler\r Set and cleared by software to control the division factor of the APB1 clock (PCLK1).\r 0xx: HCLK not divided"
bit_offset: 4
bit_size: 3
enum: PPRE
- name: PPRE2
description: "APB2 prescaler\r Set and cleared by software to control the division factor of the APB2 clock (PCLK2).\r 0xx: HCLK not divided"
bit_offset: 8
bit_size: 3
enum: PPRE
- name: DPRE
description: "DSI PHY prescaler\r This bitfiled is set and cleared by software to control the division factor of DSI PHY bus clock (DCLK).\r 0xx: DCLK not divided\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."
bit_offset: 12
bit_size: 3
enum: DPRE
- name: AHB1DIS
description: "AHB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals (except those listed hereafter) are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks are off, except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1."
bit_offset: 16
bit_size: 1
- name: AHB2DIS1
description: "AHB2_1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR1 (except SRAM2 and SRAM3) are used and when their clocks are disabled in RCC_AHB2ENR1. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR1 are off, except for SRAM2 and SRAM3."
bit_offset: 17
bit_size: 1
- name: AHB2DIS2
description: "AHB2_2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR2 are used and when their clocks are disabled in RCC_AHB2ENR2. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2EBNR2 are off."
bit_offset: 18
bit_size: 1
- name: APB1DIS
description: "APB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG."
bit_offset: 19
bit_size: 1
- name: APB2DIS
description: "APB2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all the APB2 peripherals clocks are off."
bit_offset: 20
bit_size: 1
fieldset/CFGR3:
description: RCC clock configuration register 3
fields:
- name: PPRE3
description: "APB3 prescaler\r Set and cleared by software to control the division factor of the APB3 clock (PCLK3).\r 0xx: HCLK not divided"
bit_offset: 4
bit_size: 3
enum: PPRE
- name: AHB3DIS
description: "AHB3 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB3 peripherals (except SRAM4) are used and when their clocks are disabled in RCC_AHB3ENR. When this bit is set, all the AHB3 peripherals clocks are off, except for SRAM4."
bit_offset: 16
bit_size: 1
- name: APB3DIS
description: "APB3 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals from RCC_APB3ENR are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off."
bit_offset: 17
bit_size: 1
fieldset/CICR:
description: RCC clock interrupt clear register
fields:
- name: LSIRDYC
description: "LSI ready interrupt clear\r Writing this bit to 1 clears the LSIRDYF flag. Writing 0 has no effect."
bit_offset: 0
bit_size: 1
- name: LSERDYC
description: "LSE ready interrupt clear\r Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect."
bit_offset: 1
bit_size: 1
- name: MSISRDYC
description: "MSIS ready interrupt clear\r Writing this bit to 1 clears the MSISRDYF flag. Writing 0 has no effect."
bit_offset: 2
bit_size: 1
- name: HSIRDYC
description: "HSI ready interrupt clear\r Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect."
bit_offset: 3
bit_size: 1
- name: HSERDYC
description: "HSE ready interrupt clear\r Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect."
bit_offset: 4
bit_size: 1
- name: HSI48RDYC
description: "HSI48 ready interrupt clear\r Writing this bit to 1 clears the HSI48RDYF flag. Writing 0 has no effect."
bit_offset: 5
bit_size: 1
- name: PLLRDYC
description: "PLL1 ready interrupt clear\r Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect."
bit_offset: 6
bit_size: 1
array:
len: 3
stride: 1
- name: CSSC
description: "Clock security system interrupt clear\r Writing this bit to 1 clears the CSSF flag. Writing 0 has no effect."
bit_offset: 10
bit_size: 1
- name: MSIKRDYC
description: "MSIK oscillator ready interrupt clear\r Writing this bit to 1 clears the MSIKRDYF flag. Writing 0 has no effect."
bit_offset: 11
bit_size: 1
- name: SHSIRDYC
description: "SHSI oscillator ready interrupt clear\r Writing this bit to 1 clears the SHSIRDYF flag. Writing 0 has no effect."
bit_offset: 12
bit_size: 1
fieldset/CIER:
description: RCC clock interrupt enable register
fields:
- name: LSIRDYIE
description: "LSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization."
bit_offset: 0
bit_size: 1
- name: LSERDYIE
description: "LSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization."
bit_offset: 1
bit_size: 1
- name: MSISRDYIE
description: "MSIS ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the MSIS oscillator stabilization."
bit_offset: 2
bit_size: 1
- name: HSIRDYIE
description: "HSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization."
bit_offset: 3
bit_size: 1
- name: HSERDYIE
description: "HSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization."
bit_offset: 4
bit_size: 1
- name: HSI48RDYIE
description: "HSI48 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI48 oscillator stabilization."
bit_offset: 5
bit_size: 1
- name: PLLRDYIE
description: "PLL ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by PLL1 lock."
bit_offset: 6
bit_size: 1
array:
len: 3
stride: 1
- name: MSIKRDYIE
description: "MSIK ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the MSIK oscillator stabilization."
bit_offset: 11
bit_size: 1
- name: SHSIRDYIE
description: "SHSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the SHSI oscillator stabilization."
bit_offset: 12
bit_size: 1
fieldset/CIFR:
description: RCC clock interrupt flag register
fields:
- name: LSIRDYF
description: "LSI ready interrupt flag\r Set by hardware when the LSI clock becomes stable and LSIRDYIE is set.\r Cleared by software setting the LSIRDYC bit."
bit_offset: 0
bit_size: 1
- name: LSERDYF
description: "LSE ready interrupt flag\r Set by hardware when the LSE clock becomes stable and LSERDYIE is set.\r Cleared by software setting the LSERDYC bit."
bit_offset: 1
bit_size: 1
- name: MSISRDYF
description: "MSIS ready interrupt flag\r Set by hardware when the MSIS clock becomes stable and MSISRDYIE is set.\r Cleared by software setting the MSISRDYC bit."
bit_offset: 2
bit_size: 1
- name: HSIRDYF
description: "HSI ready interrupt flag\r Set by hardware when the HSI clock becomes stable and HSIRDYIE is set in a response to setting the HSION (see RCC_CR). When HSION is not set but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.\r Cleared by software setting the HSIRDYC bit."
bit_offset: 3
bit_size: 1
- name: HSERDYF
description: "HSE ready interrupt flag\r Set by hardware when the HSE clock becomes stable and HSERDYIE is set.\r Cleared by software setting the HSERDYC bit."
bit_offset: 4
bit_size: 1
- name: HSI48RDYF
description: "HSI48 ready interrupt flag\r Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set.\r Cleared by software setting the HSI48RDYC bit."
bit_offset: 5
bit_size: 1
- name: PLLRDYF
description: "PLL1 ready interrupt flag\r Set by hardware when the PLL1 locks and PLL1RDYIE is set.\r Cleared by software setting the PLL1RDYC bit."
bit_offset: 6
bit_size: 1
array:
len: 3
stride: 1
- name: CSSF
description: "Clock security system interrupt flag\r Set by hardware when a failure is detected in the HSE oscillator.\r Cleared by software setting the CSSC bit."
bit_offset: 10
bit_size: 1
- name: MSIKRDYF
description: "MSIK ready interrupt flag\r Set by hardware when the MSIK clock becomes stable and MSIKRDYIE is set.\r Cleared by software setting the MSIKRDYC bit."
bit_offset: 11
bit_size: 1
- name: SHSIRDYF
description: "SHSI ready interrupt flag\r Set by hardware when the SHSI clock becomes stable and SHSIRDYIE is set.\r Cleared by software setting the SHSIRDYC bit."
bit_offset: 12
bit_size: 1
fieldset/CR:
description: RCC clock control register
fields:
- name: MSISON
description: "MSIS clock enable\r Set and cleared by software.\r Cleared by hardware to stop the MSIS oscillator when entering Stop, Standby or Shutdown mode.\r Set by hardware to force the MSIS oscillator ON when exiting Standby or Shutdown mode.\r Set by hardware to force the MSIS oscillator ON when STOPWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator.\r Set by hardware when used directly or indirectly as system clock."
bit_offset: 0
bit_size: 1
- name: MSIKERON
description: "MSI enable for some peripheral kernels\r Set and cleared by software to force MSI ON even in Stop modes. Keeping the MSI ON in Stop mode allows the communication speed not to be reduced by the MSI startup time. This bit has no effect on MSISON and MSIKON values (see autonomous mode for more details).\r The MSIKERON must be configured at 0 before entering Stop 3 mode."
bit_offset: 1
bit_size: 1
- name: MSISRDY
description: "MSIS clock ready flag\r Set by hardware to indicate that the MSIS oscillator is stable. This bit is set only when MSIS is enabled by software by setting MSISON.\r Note: Once the MSISON bit is cleared, MSISRDY goes low after six MSIS clock cycles."
bit_offset: 2
bit_size: 1
- name: MSIPLLEN
description: "MSI clock PLL-mode enable\r Set and cleared by software to enable/disable the PLL part of the MSI clock source.\r MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware). A hardware protection prevents from enabling MSIPLLEN if LSE is not ready.\r This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the CSS on LSE detects a LSE failure (see RCC_CSR)."
bit_offset: 3
bit_size: 1
- name: MSIKON
description: "MSIK clock enable\r Set and cleared by software.\r Cleared by hardware to stop the MSIK when entering Stop, Standby or Shutdown mode.\r Set by hardware to force the MSIK oscillator ON when exiting Standby or Shutdown mode.\r Set by hardware to force the MSIK oscillator ON when STOPWUCK = 0 or STOPKERWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator."
bit_offset: 4
bit_size: 1
- name: MSIKRDY
description: "MSIK clock ready flag\r Set by hardware to indicate that the MSIK is stable. This bit is set only when MSI kernel oscillator is enabled by software by setting MSIKON.\r Note: Once the MSIKON bit is cleared, MSIKRDY goes low after six MSIK oscillator clock cycles."
bit_offset: 5
bit_size: 1
- name: MSIPLLSEL
description: "MSI clock with PLL mode selection\r Set and cleared by software to select which MSI output clock uses the PLL mode. This bit can be written only when the MSI PLL mode is disabled (MSIPLLEN = 0).\r Note: If the MSI kernel clock output uses the same oscillator source than the MSI system clock output, then the PLL mode is applied to the both clocks outputs."
bit_offset: 6
bit_size: 1
enum: MSIPLLSEL
- name: MSIPLLFAST
description: "MSI PLL mode fast startup\r Set and reset by software to enable/disable the fast PLL mode start-up of the MSI clock\r source. This bit is used only if PLL mode is selected (MSIPLLEN = 1).\r The fast start-up feature is not active the first time the PLL mode is selected. The fast start-up is active when the MSI in PLL mode returns from switch off."
bit_offset: 7
bit_size: 1
enum: MSIPLLFAST
- name: HSION
description: "HSI clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSI oscillator when entering Stop, Standby or Shutdown mode.\r Set by hardware to force the HSI oscillator ON when STOPWUCK = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator.\r This bit is set by hardware if the HSI is used directly or indirectly as system clock."
bit_offset: 8
bit_size: 1
- name: HSIKERON
description: "HSI enable for some peripheral kernels\r Set and cleared by software to force HSI ON even in Stop modes. Keeping the HSI ON in Stop mode allows the communication speed not to be reduced by the HSI startup time. This bit has no effect on HSION value.\r Refer to for more details.\r The HSIKERON must be configured at 0 before entering Stop 3 mode."
bit_offset: 9
bit_size: 1
- name: HSIRDY
description: "HSI clock ready flag\r Set by hardware to indicate that HSI oscillator is stable. This bit is set only when HSI is enabled by software by setting HSION.\r Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI clock cycles."
bit_offset: 10
bit_size: 1
- name: HSI48ON
description: "HSI48 clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes."
bit_offset: 12
bit_size: 1
- name: HSI48RDY
description: "HSI48 clock ready flag\r Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON."
bit_offset: 13
bit_size: 1
- name: SHSION
description: "SHSI clock enable\r Set and cleared by software.\r Cleared by hardware to stop the SHSI when entering in Stop, Standby or Shutdown modes."
bit_offset: 14
bit_size: 1
- name: SHSIRDY
description: "SHSI clock ready flag\r Set by hardware to indicate that the SHSI oscillator is stable. This bit is set only when SHSI is enabled by software by setting SHSION.\r Note: Once the SHSION bit is cleared, SHSIRDY goes low after six SHSI clock cycles."
bit_offset: 15
bit_size: 1
- name: HSEON
description: "HSE clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock."
bit_offset: 16
bit_size: 1
- name: HSERDY
description: "HSE clock ready flag\r Set by hardware to indicate that the HSE oscillator is stable.\r Note: Once the HSEON bit is cleared, HSERDY goes low after six HSE clock cycles."
bit_offset: 17
bit_size: 1
- name: HSEBYP
description: "HSE crystal oscillator bypass\r Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled."
bit_offset: 18
bit_size: 1
- name: CSSON
description: "Clock security system enable\r Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset."
bit_offset: 19
bit_size: 1
- name: HSEEXT
description: "HSE external clock bypass mode\r Set and reset by software to select the external clock mode in bypass mode. External clock mode must be configured with HSEON bit to be used by the device. This bit can be written only if the HSE oscillator is disabled. This bit is active only if the HSE bypass mode is enabled."
bit_offset: 20
bit_size: 1
enum: HSEEXT
- name: PLLON
description: "PLL1 enable\r Set and cleared by software to enable the main PLL.\r Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL1 clock is used as the system clock."
bit_offset: 24
bit_size: 1
array:
len: 3
stride: 2
- name: PLLRDY
description: "PLL1 clock ready flag\r Set by hardware to indicate that the PLL1 is locked."
bit_offset: 25
bit_size: 1
array:
len: 3
stride: 2
fieldset/CRRCR:
description: RCC clock recovery RC register
fields:
- name: HSI48CAL
description: "HSI48 clock calibration\r These bits are initialized at startup with the factory-programmed HSI48 calibration trim value."
bit_offset: 0
bit_size: 9
fieldset/CSR:
description: RCC control/status register
fields:
- name: MSIKSRANGE
description: "MSIK range after Standby mode\r Set by software to chose the MSIK frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSIKSRANGE can be written only when MSIRGSEL = 1.\r others: reserved\r Note: Changing the MSIKSRANGE does not change the current MSIK frequency."
bit_offset: 8
bit_size: 4
enum: MSIXSRANGE
- name: MSISSRANGE
description: "MSIS range after Standby mode\r Set by software to chose the MSIS frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSISSRANGE can be written only when MSIRGSEL = 1.\r others: reserved\r Note: Changing the MSISSRANGE does not change the current MSIS frequency."
bit_offset: 12
bit_size: 4
enum: MSIXSRANGE
- name: RMVF
description: "Remove reset flag\r Set by software to clear the reset flags."
bit_offset: 23
bit_size: 1
- name: OBLRSTF
description: "Option byte loader reset flag\r Set by hardware when a reset from the option byte loading occurs.\r Cleared by writing to the RMVF bit."
bit_offset: 25
bit_size: 1
- name: PINRSTF
description: "NRST pin reset flag\r Set by hardware when a reset from the NRST pin occurs.\r Cleared by writing to the RMVF bit."
bit_offset: 26
bit_size: 1
- name: BORRSTF
description: "BOR flag\r Set by hardware when a BOR occurs.\r Cleared by writing to the RMVF bit."
bit_offset: 27
bit_size: 1
- name: SFTRSTF
description: "Software reset flag\r Set by hardware when a software reset occurs.\r Cleared by writing to the RMVF bit."
bit_offset: 28
bit_size: 1
- name: IWDGRSTF
description: "Independent watchdog reset flag\r Set by hardware when an independent watchdog reset domain occurs.\r Cleared by writing to the RMVF bit."
bit_offset: 29
bit_size: 1
- name: WWDGRSTF
description: "Window watchdog reset flag\r Set by hardware when a window watchdog reset occurs.\r Cleared by writing to the RMVF bit."
bit_offset: 30
bit_size: 1
- name: LPWRRSTF
description: "Low-power reset flag\r Set by hardware when a reset occurs due to Stop, Standby or Shutdown mode entry, whereas the corresponding nRST_STOP, nRST_STBY or nRST_SHDW option bit is cleared.\r Cleared by writing to the RMVF bit."
bit_offset: 31
bit_size: 1
fieldset/ICSCR1:
description: RCC internal clock sources calibration register 1
fields:
- name: MSICAL3
description: "MSIRC3 clock calibration for MSI ranges 12 to 15\r These bits are initialized at startup with the factory-programmed MSIRC3 calibration trim value for ranges 12 to 15. When MSITRIM3 is written, MSICAL3 is updated with the sum of MSITRIM3[4:0] and the factory calibration trim value MSIRC2[4:0].\r There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level."
bit_offset: 0
bit_size: 5
- name: MSICAL2
description: "MSIRC2 clock calibration for MSI ranges 8 to 11\r These bits are initialized at startup with the factory-programmed MSIRC2 calibration trim value for ranges 8 to 11. When MSITRIM2 is written, MSICAL2 is updated with the sum of MSITRIM2[4:0] and the factory calibration trim value MSIRC2[4:0].\r There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level."
bit_offset: 5
bit_size: 5
- name: MSICAL1
description: "MSIRC1 clock calibration for MSI ranges 4 to 7\r These bits are initialized at startup with the factory-programmed MSIRC1 calibration trim value for ranges 4 to 7. When MSITRIM1 is written, MSICAL1 is updated with the sum of MSITRIM1[4:0] and the factory calibration trim value MSIRC1[4:0].\r There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level."
bit_offset: 10
bit_size: 5
- name: MSICAL0
description: "MSIRC0 clock calibration for MSI ranges 0 to 3\r These bits are initialized at startup with the factory-programmed MSIRC0 calibration trim value for ranges 0 to 3. When MSITRIM0 is written, MSICAL0 is updated with the sum of MSITRIM0[4:0] and the factory-programmed calibration trim value MSIRC0[4:0]."
bit_offset: 15
bit_size: 5
- name: MSIBIAS
description: "MSI bias mode selection\r Set by software to select the MSI bias mode. By default, the MSI bias is in continuous mode in order to maintain the output clocks accuracy. Setting this bit reduces the MSI consumption under range 4 but decrease its accuracy."
bit_offset: 22
bit_size: 1
enum: MSIBIAS
- name: MSIRGSEL
description: "MSI clock range selection\r Set by software to select the MSIS and MSIK clocks range with MSISRANGE[3:0] and MSIKRANGE[3:0]. Write 0 has no effect.\r After exiting Standby or Shutdown mode, or after a reset, this bit is at 0 and the MSIS and MSIK ranges are provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR."
bit_offset: 23
bit_size: 1
enum: MSIRGSEL
- name: MSIKRANGE
description: "MSIK clock ranges\r These bits are configured by software to choose the frequency range of MSIK oscillator when MSIRGSEL is set. 16 frequency ranges are available:\r Note: MSIKRANGE can be modified when MSIK is OFF (MSISON = 0) or when MSIK is ready (MSIKRDY = 1). MSIKRANGE must NOT be modified when MSIK is ON and NOT ready (MSIKON = 1 and MSIKRDY = 0)\r MSIKRANGE is kept when the device wakes up from Stop mode, except when the MSIK range is above 24 MHz. In this case MSIKRANGE is changed by hardware into Range 2 (24 MHz)."
bit_offset: 24
bit_size: 4
enum: MSIRANGE
- name: MSISRANGE
description: "MSIS clock ranges\r These bits are configured by software to choose the frequency range of MSIS oscillator when MSIRGSEL is set. 16 frequency ranges are available:\r Note: MSISRANGE can be modified when MSIS is OFF (MSISON = 0) or when MSIS is ready (MSISRDY = 1). MSISRANGE must NOT be modified when MSIS is ON and NOT ready (MSISON = 1 and MSISRDY = 0)\r MSISRANGE is kept when the device wakes up from Stop mode, except when the MSIS range is above 24 MHz. In this case MSISRANGE is changed by hardware into Range 2 (24 MHz)."
bit_offset: 28
bit_size: 4
enum: MSIRANGE
fieldset/ICSCR2:
description: RCC internal clock sources calibration register 2
fields:
- name: MSITRIM3
description: "MSI clock trimming for ranges 12 to 15\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC3[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI."
bit_offset: 0
bit_size: 5
- name: MSITRIM2
description: "MSI clock trimming for ranges 8 to 11\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC2[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI."
bit_offset: 5
bit_size: 5
- name: MSITRIM1
description: "MSI clock trimming for ranges 4 to 7\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC1[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI."
bit_offset: 10
bit_size: 5
- name: MSITRIM0
description: "MSI clock trimming for ranges 0 to 3\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC0[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI."
bit_offset: 15
bit_size: 5
fieldset/ICSCR3:
description: RCC internal clock sources calibration register 3
fields:
- name: HSICAL
description: "HSI clock calibration\r These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value."
bit_offset: 0
bit_size: 12
- name: HSITRIM
description: "HSI clock trimming\r These bits provide an additional user-programmable trimming value that is added to the HSICAL[11:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI."
bit_offset: 16
bit_size: 5
fieldset/PLL1CFGR:
description: RCC PLL configuration register
fields:
- name: PLLSRC
description: "PLL entry clock source\r Set and cleared by software to select PLL clock source. These bits can be written only when the PLL is disabled.\r In order to save power, when no PLL is used, the value of PLLSRC must be 0."
bit_offset: 0
bit_size: 2
enum: PLLSRC
- name: PLLRGE
description: "PLL input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL.\r This bit must be written before enabling the PLL.\r 00-01-10: PLL input (ref1_ck) clock range frequency between 4 and 8 MHz"
bit_offset: 2
bit_size: 2
enum: PLLRGE
- name: PLLFRACEN
description: "PLL fractional latch enable\r Set and reset by software to latch the content of PLLFRACN into the ΣΠmodulator.\r In order to latch the PLLFRACN value into the ΣΠmodulator, PLLFRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLLFRACN into the modulator (see for details)."
bit_offset: 4
bit_size: 1
- name: PLLM
description: "Prescaler for PLL\r Set and cleared by software to configure the prescaler of the PLL. The VCO1 input frequency is PLL input clock frequency/PLLM.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0).\r ..."
bit_offset: 8
bit_size: 4
enum: PLLM
- name: PLLMBOOST
description: "Prescaler for EPOD booster input clock\r Set and cleared by software to configure the prescaler of the PLL, used for the EPOD booster. The EPOD booster input frequency is PLL input clock frequency/PLLMBOOST.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0) and EPOD Boost mode is disabled (see ).\r others: reserved"
bit_offset: 12
bit_size: 4
enum: PLLMBOOST
- name: PLLPEN
description: "PLL DIVP divider output enable\r Set and reset by software to enable the PLL_p_ck output of the PLL.\r To save power, PLLPEN and PLLP bits must be set to 0 when the PLL_p_ck is not used.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)."
bit_offset: 16
bit_size: 1
- name: PLLQEN
description: "PLL DIVQ divider output enable\r Set and reset by software to enable the PLL_q_ck output of the PLL.\r To save power, PLLQEN and PLLQ bits must be set to 0 when the PLL_q_ck is not used.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)."
bit_offset: 17
bit_size: 1
- name: PLLREN
description: "PLL DIVR divider output enable\r Set and reset by software to enable the PLL_r_ck output of the PLL.\r To save power, PLLRENPLL2REN and PLLR bits must be set to 0 when the PLL_r_ck is not used.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)."
bit_offset: 18
bit_size: 1
fieldset/PLL23CFGR:
description: RCC PLL configuration register
fields:
- name: PLLSRC
description: "PLL entry clock source\r Set and cleared by software to select PLL clock source. These bits can be written only when the PLL is disabled.\r In order to save power, when no PLL is used, the value of PLLSRC must be 0."
bit_offset: 0
bit_size: 2
enum: PLLSRC
- name: PLLRGE
description: "PLL input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL.\r This bit must be written before enabling the PLL.\r 00-01-10: PLL input (ref1_ck) clock range frequency between 4 and 8 MHz"
bit_offset: 2
bit_size: 2
enum: PLLRGE
- name: PLLFRACEN
description: "PLL fractional latch enable\r Set and reset by software to latch the content of PLLFRACN into the ΣΠmodulator.\r In order to latch the PLLFRACN value into the ΣΠmodulator, PLLFRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLLFRACN into the modulator (see for details)."
bit_offset: 4
bit_size: 1
- name: PLLM
description: "Prescaler for PLL\r Set and cleared by software to configure the prescaler of the PLL. The VCO1 input frequency is PLL input clock frequency/PLLM.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0).\r ..."
bit_offset: 8
bit_size: 4
enum: PLLM
- name: PLLPEN
description: "PLL DIVP divider output enable\r Set and reset by software to enable the PLL_p_ck output of the PLL.\r To save power, PLLPEN and PLLP bits must be set to 0 when the PLL_p_ck is not used.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)."
bit_offset: 16
bit_size: 1
- name: PLLQEN
description: "PLL DIVQ divider output enable\r Set and reset by software to enable the PLL_q_ck output of the PLL.\r To save power, PLLQEN and PLLQ bits must be set to 0 when the PLL_q_ck is not used.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)."
bit_offset: 17
bit_size: 1
- name: PLLREN
description: "PLL DIVR divider output enable\r Set and reset by software to enable the PLL_r_ck output of the PLL.\r To save power, PLLRENPLL2REN and PLLR bits must be set to 0 when the PLL_r_ck is not used.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)."
bit_offset: 18
bit_size: 1
fieldset/PLLDIVR:
description: RCC PLL1 dividers register
fields:
- name: PLLN
description: "Multiplication factor for PLL1 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ...\r ...\r Others: reserved\r VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded into PLL1FRACN, with:\r PLL1N between 4 and 512\r input frequency Fref1_ck between 4 and 16 MHz"
bit_offset: 0
bit_size: 9
enum: PLLN
- name: PLLP
description: "PLL1 DIVP division factor\r Set and reset by software to control the frequency of the pll1_p_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r Note that odd division factors are not allowed.\r ..."
bit_offset: 9
bit_size: 7
enum: PLLDIV
- name: PLLQ
description: "PLL1 DIVQ division factor\r Set and reset by software to control the frequency of the pll1_q_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..."
bit_offset: 16
bit_size: 7
enum: PLLDIV
- name: PLLR
description: "PLL1 DIVR division factor\r Set and reset by software to control the frequency of the pll1_r_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..."
bit_offset: 24
bit_size: 7
enum: PLLDIV
fieldset/PLLFRACR:
description: RCC PLL1 fractional divider register
fields:
- name: PLLFRACN
description: "Fractional part of the multiplication factor for PLL1 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.\r VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with:\r PLL1N must be between 4 and 512.\r PLL1FRACN can be between 0 and 213- 1.\r The input frequency Fref1_ck must be between 4 and 16 MHz.\r To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r Set the bit PLL1FRACEN to 0.\r Write the new fractional value into PLL1FRACN.\r Set the bit PLL1FRACEN to 1."
bit_offset: 3
bit_size: 13
fieldset/PRIVCFGR:
description: RCC privilege configuration register
fields:
- name: SPRIV
description: "RCC secure functions privilege configuration\r Set and reset by software. This bit can be written only by a secure privileged access."
bit_offset: 0
bit_size: 1
enum: PRIV
- name: NSPRIV
description: "RCC non-secure functions privilege configuration\r Set and reset by software. This bit can be written only by privileged access, secure or non-secure."
bit_offset: 1
bit_size: 1
enum: PRIV
fieldset/SECCFGR:
description: RCC secure configuration register
fields:
- name: HSISEC
description: "HSI clock configuration and status bits security\r Set and reset by software."
bit_offset: 0
bit_size: 1
enum: SECURITY
- name: HSESEC
description: "HSE clock configuration bits, status bits and HSE_CSS security\r Set and reset by software."
bit_offset: 1
bit_size: 1
enum: SECURITY
- name: MSISEC
description: "MSI clock configuration and status bits security\r Set and reset by software."
bit_offset: 2
bit_size: 1
enum: SECURITY
- name: LSISEC
description: "LSI clock configuration and status bits security\r Set and reset by software."
bit_offset: 3
bit_size: 1
enum: SECURITY
- name: LSESEC
description: "LSE clock configuration and status bits security\r Set and reset by software."
bit_offset: 4
bit_size: 1
enum: SECURITY
- name: SYSCLKSEC
description: "SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security\r Set and reset by software."
bit_offset: 5
bit_size: 1
enum: SECURITY
- name: PRESCSEC
description: "AHBx/APBx prescaler configuration bits security\r Set and reset by software."
bit_offset: 6
bit_size: 1
enum: SECURITY
- name: PLLSEC
description: "PLL1 clock configuration and status bits security\r Set and reset by software."
bit_offset: 7
bit_size: 1
array:
len: 3
stride: 1
enum: SECURITY
- name: ICLKSEC
description: "intermediate clock source selection security\r Set and reset by software."
bit_offset: 10
bit_size: 1
enum: SECURITY
- name: HSI48SEC
description: "HSI48 clock configuration and status bits security\r Set and reset by software."
bit_offset: 11
bit_size: 1
enum: SECURITY
- name: RMVFSEC
description: "Remove reset flag security\r Set and reset by software."
bit_offset: 12
bit_size: 1
enum: SECURITY
fieldset/SRDAMR:
description: RCC SmartRun domain peripheral autonomous mode register
fields:
- name: SPI3AMEN
description: "SPI3 autonomous mode enable in Stop 0,1, 2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 5
bit_size: 1
- name: LPUART1AMEN
description: "LPUART1 autonomous mode enable in Stop 0,1, 2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 6
bit_size: 1
- name: I2C3AMEN
description: "I2C3 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 7
bit_size: 1
- name: LPTIM1AMEN
description: "LPTIM1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 11
bit_size: 1
- name: LPTIM3AMEN
description: "LPTIM3 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 12
bit_size: 1
- name: LPTIM4AMEN
description: "LPTIM4 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 13
bit_size: 1
- name: OPAMPAMEN
description: "OPAMP autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software."
bit_offset: 14
bit_size: 1
- name: COMPAMEN
description: "COMP autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software."
bit_offset: 15
bit_size: 1
- name: VREFAMEN
description: "VREFBUF autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software."
bit_offset: 20
bit_size: 1
- name: RTCAPBAMEN
description: "RTC and TAMP autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 21
bit_size: 1
- name: ADC4AMEN
description: "ADC4 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 25
bit_size: 1
- name: LPGPIO1AMEN
description: "LPGPIO1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software."
bit_offset: 26
bit_size: 1
- name: DAC1AMEN
description: "DAC1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 27
bit_size: 1
- name: LPDMA1AMEN
description: "LPDMA1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 28
bit_size: 1
- name: ADF1AMEN
description: "ADF1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
bit_offset: 29
bit_size: 1
- name: SRAM4AMEN
description: "SRAM4 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software."
bit_offset: 31
bit_size: 1
enum/ADCDACSEL:
bit_size: 3
variants:
- name: HCLK1
description: HCLK clock selected
value: 0
- name: SYS
description: SYSCLK selected
value: 1
- name: PLL2_R
description: PLL2 R (pll2_r_ck) selected
value: 2
- name: HSE
description: HSE clock selected
value: 3
- name: HSI
description: HSI clock selected
value: 4
- name: MSIK
description: MSIK clock selected
value: 5
enum/ADFSEL:
bit_size: 3
variants:
- name: HCLK1
description: HCLK selected
value: 0
- name: PLL1_P
description: PLL1 P (pll1_p_ck) selected
value: 1
- name: PLL3_Q
description: PLL3 Q (pll3_q_ck) selected
value: 2
- name: AUDIOCLK
description: input pin AUDIOCLK selected
value: 3
- name: MSIK
description: MSIK clock selected
value: 4
enum/DACSEL:
bit_size: 1
variants:
- name: LSE
description: LSE selected
value: 0
- name: LSI
description: LSI selected
value: 1
enum/DPRE:
bit_size: 3
variants:
- name: Div1
description: DCLK not divided
value: 0
- name: Div2
description: DCLK divided by 2
value: 4
- name: Div4
description: DCLK divided by 4
value: 5
- name: Div8
description: DCLK divided by 8
value: 6
- name: Div16
description: DCLK divided by 16
value: 7
enum/DSISEL:
bit_size: 1
variants:
- name: PLL3_P
description: PLL3 “P” (pll3_p_ck) selected
value: 0
- name: DCLK
description: DSI PHY PLL output selected
value: 1
enum/FDCANSEL:
bit_size: 2
variants:
- name: HSE
description: HSE clock selected
value: 0
- name: PLL1_Q
description: PLL1 Q (pll1_q_ck) selected
value: 1
- name: PLL2_P
description: PLL2 P (pll2_p_ck) selected
value: 2
enum/HPRE:
bit_size: 4
variants:
- name: Div1
description: SYSCLK not divided
value: 0
- name: Div2
description: SYSCLK divided by 2
value: 8
- name: Div4
description: SYSCLK divided by 4
value: 9
- name: Div8
description: SYSCLK divided by 8
value: 10
- name: Div16
description: SYSCLK divided by 16
value: 11
- name: Div64
description: SYSCLK divided by 64
value: 12
- name: Div128
description: SYSCLK divided by 128
value: 13
- name: Div256
description: SYSCLK divided by 256
value: 14
- name: Div512
description: SYSCLK divided by 512
value: 15
enum/HSEEXT:
bit_size: 1
variants:
- name: ANALOG
description: external HSE clock analog mode
value: 0
- name: DIGITAL
description: external HSE clock digital mode (through I/O Schmitt trigger)
value: 1
enum/HSPISEL:
bit_size: 2
variants:
- name: SYS
description: SYSCLK selected
value: 0
- name: PLL1_Q
description: PLL1 “Q” (pll1_q_ck) selected, can be up to 200 MHz
value: 1
- name: PLL2_Q
description: PLL2 “Q” (pll2_q_ck) selected, can be up to 200 MHz
value: 2
- name: PLL3_R
description: PLL3 “R” (pll3_r_ck) selected, can be up to 200 MHz
value: 3
enum/ICLKSEL:
bit_size: 2
variants:
- name: HSI48
description: HSI48 clock selected
value: 0
- name: PLL2_Q
description: PLL2 Q (pll2_q_ck) selected
value: 1
- name: PLL1_Q
description: PLL1 Q (pll1_q_ck) selected
value: 2
- name: MSIK
description: MSIK clock selected
value: 3
enum/ICSEL:
bit_size: 2
variants:
- name: PCLK1
description: PCLK1 selected
value: 0
- name: SYS
description: SYSCLK selected
value: 1
- name: HSI
description: HSI selected
value: 2
- name: MSIK
description: MSIK selected
value: 3
enum/LPTIMSEL:
bit_size: 2
variants:
- name: PCLK1
description: PCLK1 selected
value: 0
- name: LSI
description: LSI selected
value: 1
- name: HSI
description: HSI selected
value: 2
- name: LSE
description: LSE selected
value: 3
enum/LPUARTSEL:
bit_size: 3
variants:
- name: PCLK3
description: PCLK3 selected
value: 0
- name: SYS
description: SYSCLK selected
value: 1
- name: HSI
description: HSI selected
value: 2
- name: LSE
description: LSE selected
value: 3
- name: MSIK
description: MSIK selected
value: 4
enum/LSCOSEL:
bit_size: 1
variants:
- name: LSI
description: LSI clock selected
value: 0
- name: LSE
description: LSE clock selected
value: 1
enum/LSEDRV:
bit_size: 2
variants:
- name: Low
description: Low driving capability
value: 0
- name: MediumLow
description: Medium low driving capability
value: 1
- name: MediumHigh
description: Medium high driving capability
value: 2
- name: High
description: High driving capability
value: 3
enum/LSIPREDIV:
bit_size: 1
variants:
- name: Div1
description: LSI not divided
value: 0
- name: Div128
description: LSI divided by 128
value: 1
enum/LTDCSEL:
bit_size: 1
variants:
- name: PLL3_R
description: PLL3 “R” (pll3_r_ck) selected
value: 0
- name: PLL2_R
description: PLL2 “R” (pll2_r_ck) selected
value: 1
enum/MCOPRE:
bit_size: 3
variants:
- name: Div1
description: MCO divided by 1
value: 0
- name: Div2
description: MCO divided by 2
value: 1
- name: Div4
description: MCO divided by 4
value: 2
- name: Div8
description: MCO divided by 8
value: 3
- name: Div16
description: MCO divided by 16
value: 4
enum/MCOSEL:
bit_size: 4
variants:
- name: DISABLE
description: MCO output disabled, no clock on MCO
value: 0
- name: SYS
description: SYSCLK system clock selected
value: 1
- name: MSIS
description: MSIS clock selected
value: 2
- name: HSI
description: HSI clock selected
value: 3
- name: HSE
description: HSE clock selected
value: 4
- name: PLL1_R
description: Main PLL clock pll1_r_ck selected
value: 5
- name: LSI
description: LSI clock selected
value: 6
- name: LSE
description: LSE clock selected
value: 7
- name: HSI48
description: Internal HSI48 clock selected
value: 8
- name: MSIK
description: MSIK clock selected
value: 9
enum/MDFSEL:
bit_size: 3
variants:
- name: HCLK1
description: HCLK selected
value: 0
- name: PLL1_P
description: PLL1 P (pll1_p_ck) selected
value: 1
- name: PLL3_Q
description: PLL3 Q (pll3_q_ck) selected
value: 2
- name: AUDIOCLK
description: input pin AUDIOCLK selected
value: 3
- name: MSIK
description: MSIK clock selected
value: 4
enum/MSIBIAS:
bit_size: 1
variants:
- name: CONTINUOUS
description: MSI bias continuous mode (clock accuracy fast settling time)
value: 0
- name: SAMPLING
description: MSI bias sampling mode (ultra-low-power mode)
value: 1
enum/MSIPLLFAST:
bit_size: 1
variants:
- name: NORMAL
description: MSI PLL normal start-up
value: 0
- name: FAST
description: MSI PLL fast start-up
value: 1
enum/MSIPLLSEL:
bit_size: 1
variants:
- name: MSIK
description: PLL mode applied to MSIK (MSI kernel) clock output
value: 0
- name: MSIS
description: PLL mode applied to MSIS (MSI system) clock output
value: 1
enum/MSIRANGE:
bit_size: 4
variants:
- name: RANGE_48MHZ
description: range 0 around 48 MHz
value: 0
- name: RANGE_24MHZ
description: range 1 around 24 MHz
value: 1
- name: RANGE_16MHZ
description: range 2 around 16 MHz
value: 2
- name: RANGE_12MHZ
description: range 3 around 12 MHz
value: 3
- name: RANGE_4MHZ
description: range 4 around 4 MHz (reset value)
value: 4
- name: RANGE_2MHZ
description: range 5 around 2 MHz
value: 5
- name: RANGE_1_33MHZ
description: range 6 around 1.33 MHz
value: 6
- name: RANGE_1MHZ
description: range 7 around 1 MHz
value: 7
- name: RANGE_3_072MHZ
description: range 8 around 3.072 MHz
value: 8
- name: RANGE_1_536MHZ
description: range 9 around 1.536 MHz
value: 9
- name: RANGE_1_024MHZ
description: range 10 around 1.024 MHz
value: 10
- name: RANGE_768KHZ
description: range 11 around 768 kHz
value: 11
- name: RANGE_400KHZ
description: range 12 around 400 kHz
value: 12
- name: RANGE_200KHZ
description: range 13 around 200 kHz
value: 13
- name: RANGE_133KHZ
description: range 14 around 133 kHz
value: 14
- name: RANGE_100KHZ
description: range 15 around 100 kHz
value: 15
enum/MSIRGSEL:
bit_size: 1
variants:
- name: RCC_CSR
description: MSIS/MSIK ranges provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR
value: 0
- name: RCC_ICSCR1
description: MSIS/MSIK ranges provided by MSISRANGE[3:0] and MSIKRANGE[3:0] in RCC_ICSCR1
value: 1
enum/MSIXSRANGE:
bit_size: 4
variants:
- name: RANGE_4MHZ
description: range 4 around 4M Hz (reset value)
value: 4
- name: RANGE_2MHZ
description: range 5 around 2 MHz
value: 5
- name: RANGE_1_5MHZ
description: range 6 around 1.5 MHz
value: 6
- name: RANGE_1MHZ
description: range 7 around 1 MHz
value: 7
- name: RANGE_3_072MHZ
description: range 8 around 3.072 MHz
value: 8
enum/OCTOSPISEL:
bit_size: 2
variants:
- name: SYS
description: SYSCLK selected
value: 0
- name: MSIK
description: MSIK selected
value: 1
- name: PLL1_Q
description: PLL1 Q (pll1_q_ck) selected, can be up to 200 MHz
value: 2
- name: PLL2_Q
description: PLL2 Q (pll2_q_ck) selected, can be up to 200 MHz
value: 3
enum/OTGHSSEL:
bit_size: 2
variants:
- name: HSE
description: HSE selected
value: 0
- name: PLL1_P
description: PLL1 “P” (pll1_q_ck) selected,
value: 1
- name: HSE_DIV_2
description: HSE/2 selected
value: 2
- name: PLL1_P_DIV_2
description: PLL1 “P” divided by 2 (pll1_p_ck/2) selected
value: 3
enum/PLLDIV:
bit_size: 7
variants:
- name: Div1
value: 0
- name: Div2
value: 1
- name: Div3
value: 2
- name: Div4
value: 3
- name: Div5
value: 4
- name: Div6
value: 5
- name: Div7
value: 6
- name: Div8
value: 7
- name: Div9
value: 8
- name: Div10
value: 9
- name: Div11
value: 10
- name: Div12
value: 11
- name: Div13
value: 12
- name: Div14
value: 13
- name: Div15
value: 14
- name: Div16
value: 15
- name: Div17
value: 16
- name: Div18
value: 17
- name: Div19
value: 18
- name: Div20
value: 19
- name: Div21
value: 20
- name: Div22
value: 21
- name: Div23
value: 22
- name: Div24
value: 23
- name: Div25
value: 24
- name: Div26
value: 25
- name: Div27
value: 26
- name: Div28
value: 27
- name: Div29
value: 28
- name: Div30
value: 29
- name: Div31
value: 30
- name: Div32
value: 31
- name: Div33
value: 32
- name: Div34
value: 33
- name: Div35
value: 34
- name: Div36
value: 35
- name: Div37
value: 36
- name: Div38
value: 37
- name: Div39
value: 38
- name: Div40
value: 39
- name: Div41
value: 40
- name: Div42
value: 41
- name: Div43
value: 42
- name: Div44
value: 43
- name: Div45
value: 44
- name: Div46
value: 45
- name: Div47
value: 46
- name: Div48
value: 47
- name: Div49
value: 48
- name: Div50
value: 49
- name: Div51
value: 50
- name: Div52
value: 51
- name: Div53
value: 52
- name: Div54
value: 53
- name: Div55
value: 54
- name: Div56
value: 55
- name: Div57
value: 56
- name: Div58
value: 57
- name: Div59
value: 58
- name: Div60
value: 59
- name: Div61
value: 60
- name: Div62
value: 61
- name: Div63
value: 62
- name: Div64
value: 63
- name: Div65
value: 64
- name: Div66
value: 65
- name: Div67
value: 66
- name: Div68
value: 67
- name: Div69
value: 68
- name: Div70
value: 69
- name: Div71
value: 70
- name: Div72
value: 71
- name: Div73
value: 72
- name: Div74
value: 73
- name: Div75
value: 74
- name: Div76
value: 75
- name: Div77
value: 76
- name: Div78
value: 77
- name: Div79
value: 78
- name: Div80
value: 79
- name: Div81
value: 80
- name: Div82
value: 81
- name: Div83
value: 82
- name: Div84
value: 83
- name: Div85
value: 84
- name: Div86
value: 85
- name: Div87
value: 86
- name: Div88
value: 87
- name: Div89
value: 88
- name: Div90
value: 89
- name: Div91
value: 90
- name: Div92
value: 91
- name: Div93
value: 92
- name: Div94
value: 93
- name: Div95
value: 94
- name: Div96
value: 95
- name: Div97
value: 96
- name: Div98
value: 97
- name: Div99
value: 98
- name: Div100
value: 99
- name: Div101
value: 100
- name: Div102
value: 101
- name: Div103
value: 102
- name: Div104
value: 103
- name: Div105
value: 104
- name: Div106
value: 105
- name: Div107
value: 106
- name: Div108
value: 107
- name: Div109
value: 108
- name: Div110
value: 109
- name: Div111
value: 110
- name: Div112
value: 111
- name: Div113
value: 112
- name: Div114
value: 113
- name: Div115
value: 114
- name: Div116
value: 115
- name: Div117
value: 116
- name: Div118
value: 117
- name: Div119
value: 118
- name: Div120
value: 119
- name: Div121
value: 120
- name: Div122
value: 121
- name: Div123
value: 122
- name: Div124
value: 123
- name: Div125
value: 124
- name: Div126
value: 125
- name: Div127
value: 126
- name: Div128
value: 127
enum/PLLM:
bit_size: 4
variants:
- name: Div1
value: 0
- name: Div2
value: 1
- name: Div3
value: 2
- name: Div4
value: 3
- name: Div5
value: 4
- name: Div6
value: 5
- name: Div7
value: 6
- name: Div8
value: 7
- name: Div9
value: 8
- name: Div10
value: 9
- name: Div11
value: 10
- name: Div12
value: 11
- name: Div13
value: 12
- name: Div14
value: 13
- name: Div15
value: 14
- name: Div16
value: 15
enum/PLLMBOOST:
bit_size: 4
variants:
- name: Div1
description: division by 1 (bypass)
value: 0
- name: Div2
description: division by 2
value: 1
- name: Div4
description: division by 4
value: 2
- name: Div6
description: division by 6
value: 3
- name: Div8
description: division by 8
value: 4
- name: Div10
description: division by 10
value: 5
- name: Div12
description: division by 12
value: 6
- name: Div14
description: division by 14
value: 7
- name: Div16
description: division by 16
value: 8
enum/PLLN:
bit_size: 9
variants:
- name: Mul4
value: 3
- name: Mul5
value: 4
- name: Mul6
value: 5
- name: Mul7
value: 6
- name: Mul8
value: 7
- name: Mul9
value: 8
- name: Mul10
value: 9
- name: Mul11
value: 10
- name: Mul12
value: 11
- name: Mul13
value: 12
- name: Mul14
value: 13
- name: Mul15
value: 14
- name: Mul16
value: 15
- name: Mul17
value: 16
- name: Mul18
value: 17
- name: Mul19
value: 18
- name: Mul20
value: 19
- name: Mul21
value: 20
- name: Mul22
value: 21
- name: Mul23
value: 22
- name: Mul24
value: 23
- name: Mul25
value: 24
- name: Mul26
value: 25
- name: Mul27
value: 26
- name: Mul28
value: 27
- name: Mul29
value: 28
- name: Mul30
value: 29
- name: Mul31
value: 30
- name: Mul32
value: 31
- name: Mul33
value: 32
- name: Mul34
value: 33
- name: Mul35
value: 34
- name: Mul36
value: 35
- name: Mul37
value: 36
- name: Mul38
value: 37
- name: Mul39
value: 38
- name: Mul40
value: 39
- name: Mul41
value: 40
- name: Mul42
value: 41
- name: Mul43
value: 42
- name: Mul44
value: 43
- name: Mul45
value: 44
- name: Mul46
value: 45
- name: Mul47
value: 46
- name: Mul48
value: 47
- name: Mul49
value: 48
- name: Mul50
value: 49
- name: Mul51
value: 50
- name: Mul52
value: 51
- name: Mul53
value: 52
- name: Mul54
value: 53
- name: Mul55
value: 54
- name: Mul56
value: 55
- name: Mul57
value: 56
- name: Mul58
value: 57
- name: Mul59
value: 58
- name: Mul60
value: 59
- name: Mul61
value: 60
- name: Mul62
value: 61
- name: Mul63
value: 62
- name: Mul64
value: 63
- name: Mul65
value: 64
- name: Mul66
value: 65
- name: Mul67
value: 66
- name: Mul68
value: 67
- name: Mul69
value: 68
- name: Mul70
value: 69
- name: Mul71
value: 70
- name: Mul72
value: 71
- name: Mul73
value: 72
- name: Mul74
value: 73
- name: Mul75
value: 74
- name: Mul76
value: 75
- name: Mul77
value: 76
- name: Mul78
value: 77
- name: Mul79
value: 78
- name: Mul80
value: 79
- name: Mul81
value: 80
- name: Mul82
value: 81
- name: Mul83
value: 82
- name: Mul84
value: 83
- name: Mul85
value: 84
- name: Mul86
value: 85
- name: Mul87
value: 86
- name: Mul88
value: 87
- name: Mul89
value: 88
- name: Mul90
value: 89
- name: Mul91
value: 90
- name: Mul92
value: 91
- name: Mul93
value: 92
- name: Mul94
value: 93
- name: Mul95
value: 94
- name: Mul96
value: 95
- name: Mul97
value: 96
- name: Mul98
value: 97
- name: Mul99
value: 98
- name: Mul100
value: 99
- name: Mul101
value: 100
- name: Mul102
value: 101
- name: Mul103
value: 102
- name: Mul104
value: 103
- name: Mul105
value: 104
- name: Mul106
value: 105
- name: Mul107
value: 106
- name: Mul108
value: 107
- name: Mul109
value: 108
- name: Mul110
value: 109
- name: Mul111
value: 110
- name: Mul112
value: 111
- name: Mul113
value: 112
- name: Mul114
value: 113
- name: Mul115
value: 114
- name: Mul116
value: 115
- name: Mul117
value: 116
- name: Mul118
value: 117
- name: Mul119
value: 118
- name: Mul120
value: 119
- name: Mul121
value: 120
- name: Mul122
value: 121
- name: Mul123
value: 122
- name: Mul124
value: 123
- name: Mul125
value: 124
- name: Mul126
value: 125
- name: Mul127
value: 126
- name: Mul128
value: 127
- name: Mul129
value: 128
- name: Mul130
value: 129
- name: Mul131
value: 130
- name: Mul132
value: 131
- name: Mul133
value: 132
- name: Mul134
value: 133
- name: Mul135
value: 134
- name: Mul136
value: 135
- name: Mul137
value: 136
- name: Mul138
value: 137
- name: Mul139
value: 138
- name: Mul140
value: 139
- name: Mul141
value: 140
- name: Mul142
value: 141
- name: Mul143
value: 142
- name: Mul144
value: 143
- name: Mul145
value: 144
- name: Mul146
value: 145
- name: Mul147
value: 146
- name: Mul148
value: 147
- name: Mul149
value: 148
- name: Mul150
value: 149
- name: Mul151
value: 150
- name: Mul152
value: 151
- name: Mul153
value: 152
- name: Mul154
value: 153
- name: Mul155
value: 154
- name: Mul156
value: 155
- name: Mul157
value: 156
- name: Mul158
value: 157
- name: Mul159
value: 158
- name: Mul160
value: 159
- name: Mul161
value: 160
- name: Mul162
value: 161
- name: Mul163
value: 162
- name: Mul164
value: 163
- name: Mul165
value: 164
- name: Mul166
value: 165
- name: Mul167
value: 166
- name: Mul168
value: 167
- name: Mul169
value: 168
- name: Mul170
value: 169
- name: Mul171
value: 170
- name: Mul172
value: 171
- name: Mul173
value: 172
- name: Mul174
value: 173
- name: Mul175
value: 174
- name: Mul176
value: 175
- name: Mul177
value: 176
- name: Mul178
value: 177
- name: Mul179
value: 178
- name: Mul180
value: 179
- name: Mul181
value: 180
- name: Mul182
value: 181
- name: Mul183
value: 182
- name: Mul184
value: 183
- name: Mul185
value: 184
- name: Mul186
value: 185
- name: Mul187
value: 186
- name: Mul188
value: 187
- name: Mul189
value: 188
- name: Mul190
value: 189
- name: Mul191
value: 190
- name: Mul192
value: 191
- name: Mul193
value: 192
- name: Mul194
value: 193
- name: Mul195
value: 194
- name: Mul196
value: 195
- name: Mul197
value: 196
- name: Mul198
value: 197
- name: Mul199
value: 198
- name: Mul200
value: 199
- name: Mul201
value: 200
- name: Mul202
value: 201
- name: Mul203
value: 202
- name: Mul204
value: 203
- name: Mul205
value: 204
- name: Mul206
value: 205
- name: Mul207
value: 206
- name: Mul208
value: 207
- name: Mul209
value: 208
- name: Mul210
value: 209
- name: Mul211
value: 210
- name: Mul212
value: 211
- name: Mul213
value: 212
- name: Mul214
value: 213
- name: Mul215
value: 214
- name: Mul216
value: 215
- name: Mul217
value: 216
- name: Mul218
value: 217
- name: Mul219
value: 218
- name: Mul220
value: 219
- name: Mul221
value: 220
- name: Mul222
value: 221
- name: Mul223
value: 222
- name: Mul224
value: 223
- name: Mul225
value: 224
- name: Mul226
value: 225
- name: Mul227
value: 226
- name: Mul228
value: 227
- name: Mul229
value: 228
- name: Mul230
value: 229
- name: Mul231
value: 230
- name: Mul232
value: 231
- name: Mul233
value: 232
- name: Mul234
value: 233
- name: Mul235
value: 234
- name: Mul236
value: 235
- name: Mul237
value: 236
- name: Mul238
value: 237
- name: Mul239
value: 238
- name: Mul240
value: 239
- name: Mul241
value: 240
- name: Mul242
value: 241
- name: Mul243
value: 242
- name: Mul244
value: 243
- name: Mul245
value: 244
- name: Mul246
value: 245
- name: Mul247
value: 246
- name: Mul248
value: 247
- name: Mul249
value: 248
- name: Mul250
value: 249
- name: Mul251
value: 250
- name: Mul252
value: 251
- name: Mul253
value: 252
- name: Mul254
value: 253
- name: Mul255
value: 254
- name: Mul256
value: 255
- name: Mul257
value: 256
- name: Mul258
value: 257
- name: Mul259
value: 258
- name: Mul260
value: 259
- name: Mul261
value: 260
- name: Mul262
value: 261
- name: Mul263
value: 262
- name: Mul264
value: 263
- name: Mul265
value: 264
- name: Mul266
value: 265
- name: Mul267
value: 266
- name: Mul268
value: 267
- name: Mul269
value: 268
- name: Mul270
value: 269
- name: Mul271
value: 270
- name: Mul272
value: 271
- name: Mul273
value: 272
- name: Mul274
value: 273
- name: Mul275
value: 274
- name: Mul276
value: 275
- name: Mul277
value: 276
- name: Mul278
value: 277
- name: Mul279
value: 278
- name: Mul280
value: 279
- name: Mul281
value: 280
- name: Mul282
value: 281
- name: Mul283
value: 282
- name: Mul284
value: 283
- name: Mul285
value: 284
- name: Mul286
value: 285
- name: Mul287
value: 286
- name: Mul288
value: 287
- name: Mul289
value: 288
- name: Mul290
value: 289
- name: Mul291
value: 290
- name: Mul292
value: 291
- name: Mul293
value: 292
- name: Mul294
value: 293
- name: Mul295
value: 294
- name: Mul296
value: 295
- name: Mul297
value: 296
- name: Mul298
value: 297
- name: Mul299
value: 298
- name: Mul300
value: 299
- name: Mul301
value: 300
- name: Mul302
value: 301
- name: Mul303
value: 302
- name: Mul304
value: 303
- name: Mul305
value: 304
- name: Mul306
value: 305
- name: Mul307
value: 306
- name: Mul308
value: 307
- name: Mul309
value: 308
- name: Mul310
value: 309
- name: Mul311
value: 310
- name: Mul312
value: 311
- name: Mul313
value: 312
- name: Mul314
value: 313
- name: Mul315
value: 314
- name: Mul316
value: 315
- name: Mul317
value: 316
- name: Mul318
value: 317
- name: Mul319
value: 318
- name: Mul320
value: 319
- name: Mul321
value: 320
- name: Mul322
value: 321
- name: Mul323
value: 322
- name: Mul324
value: 323
- name: Mul325
value: 324
- name: Mul326
value: 325
- name: Mul327
value: 326
- name: Mul328
value: 327
- name: Mul329
value: 328
- name: Mul330
value: 329
- name: Mul331
value: 330
- name: Mul332
value: 331
- name: Mul333
value: 332
- name: Mul334
value: 333
- name: Mul335
value: 334
- name: Mul336
value: 335
- name: Mul337
value: 336
- name: Mul338
value: 337
- name: Mul339
value: 338
- name: Mul340
value: 339
- name: Mul341
value: 340
- name: Mul342
value: 341
- name: Mul343
value: 342
- name: Mul344
value: 343
- name: Mul345
value: 344
- name: Mul346
value: 345
- name: Mul347
value: 346
- name: Mul348
value: 347
- name: Mul349
value: 348
- name: Mul350
value: 349
- name: Mul351
value: 350
- name: Mul352
value: 351
- name: Mul353
value: 352
- name: Mul354
value: 353
- name: Mul355
value: 354
- name: Mul356
value: 355
- name: Mul357
value: 356
- name: Mul358
value: 357
- name: Mul359
value: 358
- name: Mul360
value: 359
- name: Mul361
value: 360
- name: Mul362
value: 361
- name: Mul363
value: 362
- name: Mul364
value: 363
- name: Mul365
value: 364
- name: Mul366
value: 365
- name: Mul367
value: 366
- name: Mul368
value: 367
- name: Mul369
value: 368
- name: Mul370
value: 369
- name: Mul371
value: 370
- name: Mul372
value: 371
- name: Mul373
value: 372
- name: Mul374
value: 373
- name: Mul375
value: 374
- name: Mul376
value: 375
- name: Mul377
value: 376
- name: Mul378
value: 377
- name: Mul379
value: 378
- name: Mul380
value: 379
- name: Mul381
value: 380
- name: Mul382
value: 381
- name: Mul383
value: 382
- name: Mul384
value: 383
- name: Mul385
value: 384
- name: Mul386
value: 385
- name: Mul387
value: 386
- name: Mul388
value: 387
- name: Mul389
value: 388
- name: Mul390
value: 389
- name: Mul391
value: 390
- name: Mul392
value: 391
- name: Mul393
value: 392
- name: Mul394
value: 393
- name: Mul395
value: 394
- name: Mul396
value: 395
- name: Mul397
value: 396
- name: Mul398
value: 397
- name: Mul399
value: 398
- name: Mul400
value: 399
- name: Mul401
value: 400
- name: Mul402
value: 401
- name: Mul403
value: 402
- name: Mul404
value: 403
- name: Mul405
value: 404
- name: Mul406
value: 405
- name: Mul407
value: 406
- name: Mul408
value: 407
- name: Mul409
value: 408
- name: Mul410
value: 409
- name: Mul411
value: 410
- name: Mul412
value: 411
- name: Mul413
value: 412
- name: Mul414
value: 413
- name: Mul415
value: 414
- name: Mul416
value: 415
- name: Mul417
value: 416
- name: Mul418
value: 417
- name: Mul419
value: 418
- name: Mul420
value: 419
- name: Mul421
value: 420
- name: Mul422
value: 421
- name: Mul423
value: 422
- name: Mul424
value: 423
- name: Mul425
value: 424
- name: Mul426
value: 425
- name: Mul427
value: 426
- name: Mul428
value: 427
- name: Mul429
value: 428
- name: Mul430
value: 429
- name: Mul431
value: 430
- name: Mul432
value: 431
- name: Mul433
value: 432
- name: Mul434
value: 433
- name: Mul435
value: 434
- name: Mul436
value: 435
- name: Mul437
value: 436
- name: Mul438
value: 437
- name: Mul439
value: 438
- name: Mul440
value: 439
- name: Mul441
value: 440
- name: Mul442
value: 441
- name: Mul443
value: 442
- name: Mul444
value: 443
- name: Mul445
value: 444
- name: Mul446
value: 445
- name: Mul447
value: 446
- name: Mul448
value: 447
- name: Mul449
value: 448
- name: Mul450
value: 449
- name: Mul451
value: 450
- name: Mul452
value: 451
- name: Mul453
value: 452
- name: Mul454
value: 453
- name: Mul455
value: 454
- name: Mul456
value: 455
- name: Mul457
value: 456
- name: Mul458
value: 457
- name: Mul459
value: 458
- name: Mul460
value: 459
- name: Mul461
value: 460
- name: Mul462
value: 461
- name: Mul463
value: 462
- name: Mul464
value: 463
- name: Mul465
value: 464
- name: Mul466
value: 465
- name: Mul467
value: 466
- name: Mul468
value: 467
- name: Mul469
value: 468
- name: Mul470
value: 469
- name: Mul471
value: 470
- name: Mul472
value: 471
- name: Mul473
value: 472
- name: Mul474
value: 473
- name: Mul475
value: 474
- name: Mul476
value: 475
- name: Mul477
value: 476
- name: Mul478
value: 477
- name: Mul479
value: 478
- name: Mul480
value: 479
- name: Mul481
value: 480
- name: Mul482
value: 481
- name: Mul483
value: 482
- name: Mul484
value: 483
- name: Mul485
value: 484
- name: Mul486
value: 485
- name: Mul487
value: 486
- name: Mul488
value: 487
- name: Mul489
value: 488
- name: Mul490
value: 489
- name: Mul491
value: 490
- name: Mul492
value: 491
- name: Mul493
value: 492
- name: Mul494
value: 493
- name: Mul495
value: 494
- name: Mul496
value: 495
- name: Mul497
value: 496
- name: Mul498
value: 497
- name: Mul499
value: 498
- name: Mul500
value: 499
- name: Mul501
value: 500
- name: Mul502
value: 501
- name: Mul503
value: 502
- name: Mul504
value: 503
- name: Mul505
value: 504
- name: Mul506
value: 505
- name: Mul507
value: 506
- name: Mul508
value: 507
- name: Mul509
value: 508
- name: Mul510
value: 509
- name: Mul511
value: 510
- name: Mul512
value: 511
enum/PLLRGE:
bit_size: 2
variants:
- name: FREQ_4TO8MHZ
description: PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz
value: 0
- name: FREQ_8TO16MHZ
description: PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz
value: 3
enum/PLLSRC:
bit_size: 2
variants:
- name: DISABLE
description: No clock sent to PLL3
value: 0
- name: MSIS
description: MSIS clock selected as PLL3 clock entry
value: 1
- name: HSI
description: HSI clock selected as PLL3 clock entry
value: 2
- name: HSE
description: HSE clock selected as PLL3 clock entry
value: 3
enum/PPRE:
bit_size: 3
variants:
- name: Div1
description: HCLK not divided
value: 0
- name: Div2
description: HCLK divided by 2
value: 4
- name: Div4
description: HCLK divided by 4
value: 5
- name: Div8
description: HCLK divided by 8
value: 6
- name: Div16
description: HCLK divided by 16
value: 7
enum/PRIV:
bit_size: 1
variants:
- name: UNPRIVILEGED
description: Read and write to secure functions can be done by privileged or unprivileged access.
value: 0
- name: PRIVILEGED
description: Read and write to secure functions can be done by privileged access only.
value: 1
enum/RNGSEL:
bit_size: 2
variants:
- name: HSI48
description: HSI48 selected
value: 0
- name: HSI48_DIV_2
description: HSI48 / 2 selected, can be used in Range 4
value: 1
- name: HSI
description: HSI selected
value: 2
enum/RTCSEL:
bit_size: 2
variants:
- name: DISABLE
description: No clock selected
value: 0
- name: LSE
description: LSE oscillator clock selected
value: 1
- name: LSI
description: LSI oscillator clock selected
value: 2
- name: HSE
description: HSE oscillator clock divided by 32 selected
value: 3
enum/SAESSEL:
bit_size: 1
variants:
- name: SHSI
description: SHSI selected
value: 0
- name: SHSI_DIV_2
description: SHSI / 2 selected, can be used in Range 4
value: 1
enum/SAISEL:
bit_size: 3
variants:
- name: PLL2_P
description: PLL2 P (pll2_p_ck) selected
value: 0
- name: PLL3_P
description: PLL3 P (pll3_p_ck) selected
value: 1
- name: PLL1_P
description: PLL1 P (pll1_p_ck) selected
value: 2
- name: AUDIOCLK
description: input pin AUDIOCLK selected
value: 3
- name: HSI
description: HSI clock selected
value: 4
enum/SDMMCSEL:
bit_size: 1
variants:
- name: ICLK
description: ICLK clock selected
value: 0
- name: PLL1_P
description: PLL1 P (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode)
value: 1
enum/SECURITY:
bit_size: 1
variants:
- name: NON_SECURE
description: non secure
value: 0
- name: SECURE
description: secure
value: 1
enum/SPISEL:
bit_size: 2
variants:
- name: PCLK2
description: PCLK2 selected
value: 0
- name: SYS
description: SYSCLK selected
value: 1
- name: HSI
description: HSI selected
value: 2
- name: MSIK
description: MSIK selected
value: 3
enum/STOPKERWUCK:
bit_size: 1
variants:
- name: MSIK
description: MSIK oscillator automatically enabled when exiting Stop mode
value: 0
- name: HSI
description: HSI oscillator automatically enabled when exiting Stop mode
value: 1
enum/STOPWUCK:
bit_size: 1
variants:
- name: MSIS
description: MSIS oscillator selected as wakeup from stop clock and CSS backup clock
value: 0
- name: HSI
description: HSI oscillator selected as wakeup from stop clock and CSS backup clock
value: 1
enum/SW:
bit_size: 2
variants:
- name: MSIS
description: MSIS selected as system clock
value: 0
- name: HSI
description: HSI selected as system clock
value: 1
- name: HSE
description: HSE selected as system clock
value: 2
- name: PLL1_R
description: PLL pll1_r_ck selected as system clock
value: 3
enum/SYSTICKSEL:
bit_size: 2
variants:
- name: HCLK1_DIV_8
description: HCLK/8 selected
value: 0
- name: LSI
description: LSI selected
value: 1
- name: LSE
description: LSE selected
value: 2
enum/TIMICSEL:
bit_size: 3
variants:
- name: DISABLE
description: No sources can be selected by TIM16, TIM17 and LPTIM2 as internal input capture
value: 0
- name: HSI256_MSIS1024_MSIS4
description: HSI/256, MSIS/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture
value: 4
- name: HSI256_MSIS1024_MSIK4
description: HSI/256, MSIS/1024 and MSIK/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture
value: 5
- name: HSI256_MSIK1024_MSIS4
description: HSI/256, MSIK/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture
value: 6
- name: HSI256_MSIK1024_MSIK4
description: HSI/256, MSIK/1024 and MSIK/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture
value: 7
enum/UARTSEL:
bit_size: 2
variants:
- name: PCLK1
description: PCLK1 selected
value: 0
- name: SYS
description: SYSCLK selected
value: 1
- name: HSI
description: HSI selected
value: 2
- name: LSE
description: LSE selected
value: 3
enum/USARTSEL:
bit_size: 2
variants:
- name: PCLK2
description: PCLK2 selected
value: 0
- name: SYS
description: SYSCLK selected
value: 1
- name: HSI
description: HSI selected
value: 2
- name: LSE
description: LSE selected
value: 3
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