1261 lines
30 KiB
YAML
1261 lines
30 KiB
YAML
block/RCC:
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description: Reset and clock control
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items:
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- name: CR
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description: Clock control register
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byte_offset: 0
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fieldset: CR
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- name: ICSCR
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description: Internal clock sources calibration register
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byte_offset: 4
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fieldset: ICSCR
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- name: CRRCR
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description: Clock recovery RC register
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byte_offset: 8
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fieldset: CRRCR
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- name: CFGR
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description: Clock configuration register
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byte_offset: 12
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fieldset: CFGR
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- name: CIER
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description: Clock interrupt enable register
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byte_offset: 16
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access: Read
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fieldset: CIER
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- name: CIFR
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description: Clock interrupt flag register
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byte_offset: 20
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access: Read
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fieldset: CIFR
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- name: CICR
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description: Clock interrupt clear register
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byte_offset: 24
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access: Read
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fieldset: CICR
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- name: GPIORSTR
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description: GPIO reset register
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byte_offset: 28
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fieldset: GPIORSTR
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- name: AHBRSTR
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description: AHB peripheral reset register
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byte_offset: 32
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fieldset: AHBRSTR
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- name: APB2RSTR
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description: APB2 peripheral reset register
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byte_offset: 36
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fieldset: APB2RSTR
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- name: APB1RSTR
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description: APB1 peripheral reset register
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byte_offset: 40
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fieldset: APB1RSTR
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- name: GPIOENR
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description: GPIO clock enable register
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byte_offset: 44
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fieldset: GPIOENR
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- name: AHBENR
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description: AHB peripheral clock enable register
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byte_offset: 48
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fieldset: AHBENR
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- name: APB2ENR
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description: APB2 peripheral clock enable register
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byte_offset: 52
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fieldset: APB2ENR
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- name: APB1ENR
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description: APB1 peripheral clock enable register
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byte_offset: 56
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fieldset: APB1ENR
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- name: GPIOSMEN
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description: GPIO clock enable in sleep mode register
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byte_offset: 60
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fieldset: GPIOSMEN
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- name: AHBSMENR
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description: AHB peripheral clock enable in sleep mode register
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byte_offset: 64
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fieldset: AHBSMENR
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- name: APB2SMENR
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description: APB2 peripheral clock enable in sleep mode register
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byte_offset: 68
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fieldset: APB2SMENR
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- name: APB1SMENR
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description: APB1 peripheral clock enable in sleep mode register
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byte_offset: 72
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fieldset: APB1SMENR
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- name: CCIPR
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description: Clock configuration register
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byte_offset: 76
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fieldset: CCIPR
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- name: CSR
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description: Control and status register
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byte_offset: 80
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fieldset: CSR
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fieldset/AHBENR:
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description: AHB peripheral clock enable register
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fields:
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- name: DMA1EN
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description: DMA clock enable
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bit_offset: 0
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bit_size: 1
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- name: MIFEN
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description: NVM interface clock enable
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bit_offset: 8
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bit_size: 1
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- name: CRCEN
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description: CRC clock enable
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bit_offset: 12
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bit_size: 1
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- name: TOUCHEN
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description: Touch Sensing clock enable
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bit_offset: 16
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bit_size: 1
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- name: RNGEN
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description: Random Number Generator clock enable
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bit_offset: 20
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bit_size: 1
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- name: CRYPEN
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description: Crypto clock enable
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bit_offset: 24
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bit_size: 1
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fieldset/AHBRSTR:
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description: AHB peripheral reset register
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fields:
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- name: DMA1RST
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description: DMA reset
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bit_offset: 0
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bit_size: 1
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- name: MIFRST
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description: Memory interface reset
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bit_offset: 8
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bit_size: 1
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- name: CRCRST
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description: Test integration module reset
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bit_offset: 12
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bit_size: 1
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- name: TOUCHRST
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description: Touch Sensing reset
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bit_offset: 16
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bit_size: 1
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- name: RNGRST
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description: Random Number Generator module reset
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bit_offset: 20
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bit_size: 1
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- name: CRYPRST
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description: Crypto module reset
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bit_offset: 24
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bit_size: 1
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fieldset/AHBSMENR:
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description: AHB peripheral clock enable in sleep mode register
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fields:
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- name: DMA1SMEN
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description: DMA clock enable during sleep mode
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bit_offset: 0
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bit_size: 1
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- name: MIFSMEN
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description: NVM interface clock enable during sleep mode
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bit_offset: 8
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bit_size: 1
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- name: SRAMSMEN
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description: SRAM interface clock enable during sleep mode
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bit_offset: 9
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bit_size: 1
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- name: CRCSMEN
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description: CRC clock enable during sleep mode
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bit_offset: 12
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bit_size: 1
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- name: TOUCHSMEN
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description: Touch Sensing clock enable during sleep mode
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bit_offset: 16
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bit_size: 1
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- name: RNGSMEN
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description: Random Number Generator clock enable during sleep mode
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bit_offset: 20
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bit_size: 1
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- name: CRYPSMEN
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description: Crypto clock enable during sleep mode
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bit_offset: 24
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bit_size: 1
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fieldset/APB1ENR:
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description: APB1 peripheral clock enable register
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fields:
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- name: TIM2EN
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description: Timer2 clock enable
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bit_offset: 0
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bit_size: 1
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- name: TIM3EN
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description: Timer 3 clock enbale
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bit_offset: 1
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bit_size: 1
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- name: TIM6EN
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description: Timer 6 clock enable
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bit_offset: 4
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bit_size: 1
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- name: TIM7EN
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description: Timer 7 clock enable
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bit_offset: 5
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bit_size: 1
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- name: WWDGEN
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description: Window watchdog clock enable
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bit_offset: 11
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bit_size: 1
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- name: SPI2EN
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description: SPI2 clock enable
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bit_offset: 14
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bit_size: 1
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- name: USART2EN
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description: UART2 clock enable
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bit_offset: 17
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bit_size: 1
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- name: LPUART1EN
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description: LPUART1 clock enable
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bit_offset: 18
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bit_size: 1
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- name: USART4EN
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description: USART4 clock enable
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bit_offset: 19
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bit_size: 1
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- name: USART5EN
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description: USART5 clock enable
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bit_offset: 20
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bit_size: 1
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- name: I2C1EN
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description: I2C1 clock enable
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bit_offset: 21
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bit_size: 1
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- name: I2C2EN
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description: I2C2 clock enable
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bit_offset: 22
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bit_size: 1
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- name: USBEN
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description: USB clock enable
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bit_offset: 23
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bit_size: 1
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- name: CRSEN
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description: Clock recovery system clock enable
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bit_offset: 27
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bit_size: 1
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- name: PWREN
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description: Power interface clock enable
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bit_offset: 28
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bit_size: 1
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- name: DACEN
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description: DAC interface clock enable
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bit_offset: 29
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bit_size: 1
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- name: I2C3EN
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description: I2C3 clock enable
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bit_offset: 30
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bit_size: 1
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- name: LPTIM1EN
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description: Low power timer clock enable
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bit_offset: 31
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bit_size: 1
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fieldset/APB1RSTR:
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description: APB1 peripheral reset register
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fields:
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- name: TIM2RST
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description: Timer 2 reset
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bit_offset: 0
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bit_size: 1
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- name: TIM3RST
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description: Timer 3 reset
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bit_offset: 1
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bit_size: 1
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- name: TIM6RST
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description: Timer 6 reset
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bit_offset: 4
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bit_size: 1
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- name: TIM7RST
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description: Timer 7 reset
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bit_offset: 5
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bit_size: 1
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- name: WWDGRST
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description: Window watchdog reset
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bit_offset: 11
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bit_size: 1
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- name: SPI2RST
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description: SPI2 reset
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bit_offset: 14
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bit_size: 1
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- name: USART2RST
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description: USART2 reset
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bit_offset: 17
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bit_size: 1
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- name: LPUART1RST
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description: LPUART1 reset
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bit_offset: 18
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bit_size: 1
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- name: USART4RST
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description: USART4 reset
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bit_offset: 19
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bit_size: 1
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- name: USART5RST
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description: USART5 reset
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bit_offset: 20
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bit_size: 1
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- name: I2C1RST
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description: I2C1 reset
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bit_offset: 21
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bit_size: 1
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- name: I2C2RST
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description: I2C2 reset
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bit_offset: 22
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bit_size: 1
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- name: USBRST
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description: USB reset
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bit_offset: 23
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bit_size: 1
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- name: CRSRST
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description: Clock recovery system reset
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bit_offset: 27
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bit_size: 1
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- name: PWRRST
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description: Power interface reset
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bit_offset: 28
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bit_size: 1
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- name: DACRST
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description: DAC interface reset
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bit_offset: 29
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bit_size: 1
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- name: I2C3RST
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description: I2C3 reset
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bit_offset: 30
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bit_size: 1
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- name: LPTIM1RST
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description: Low power timer reset
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bit_offset: 31
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bit_size: 1
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fieldset/APB1SMENR:
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description: APB1 peripheral clock enable in sleep mode register
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fields:
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- name: TIM2SMEN
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description: Timer2 clock enable during sleep mode
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bit_offset: 0
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bit_size: 1
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- name: TIM3SMEN
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description: Timer 3 clock enable during sleep mode
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bit_offset: 1
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bit_size: 1
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- name: TIM6SMEN
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description: Timer 6 clock enable during sleep mode
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bit_offset: 4
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bit_size: 1
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- name: TIM7SMEN
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description: Timer 7 clock enable during sleep mode
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bit_offset: 5
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bit_size: 1
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- name: WWDGSMEN
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description: Window watchdog clock enable during sleep mode
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bit_offset: 11
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bit_size: 1
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- name: SPI2SMEN
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description: SPI2 clock enable during sleep mode
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bit_offset: 14
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bit_size: 1
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- name: USART2SMEN
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description: UART2 clock enable during sleep mode
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bit_offset: 17
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bit_size: 1
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- name: LPUART1SMEN
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description: LPUART1 clock enable during sleep mode
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bit_offset: 18
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bit_size: 1
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- name: USART4SMEN
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description: USART4 clock enabe during sleep mode
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bit_offset: 19
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bit_size: 1
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- name: USART5SMEN
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description: USART5 clock enable during sleep mode
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bit_offset: 20
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bit_size: 1
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- name: I2C1SMEN
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description: I2C1 clock enable during sleep mode
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bit_offset: 21
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bit_size: 1
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- name: I2C2SMEN
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description: I2C2 clock enable during sleep mode
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bit_offset: 22
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bit_size: 1
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- name: USBSMEN
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description: USB clock enable during sleep mode
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bit_offset: 23
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bit_size: 1
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- name: CRSSMEN
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description: Clock recovery system clock enable during sleep mode
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bit_offset: 27
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bit_size: 1
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- name: PWRSMEN
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description: Power interface clock enable during sleep mode
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bit_offset: 28
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bit_size: 1
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- name: DACSMEN
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description: DAC interface clock enable during sleep mode
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bit_offset: 29
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bit_size: 1
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- name: I2C3SMEN
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description: I2C3 clock enable during sleep mode
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bit_offset: 30
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bit_size: 1
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- name: LPTIM1SMEN
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description: Low power timer clock enable during sleep mode
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bit_offset: 31
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bit_size: 1
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fieldset/APB2ENR:
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description: APB2 peripheral clock enable register
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fields:
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- name: SYSCFGEN
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description: System configuration controller clock enable
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bit_offset: 0
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bit_size: 1
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- name: TIM21EN
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description: TIM21 timer clock enable
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bit_offset: 2
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bit_size: 1
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- name: TIM22EN
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description: TIM22 timer clock enable
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bit_offset: 5
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bit_size: 1
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- name: FWEN
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description: Firewall clock enable
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bit_offset: 7
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bit_size: 1
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- name: ADCEN
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description: ADC clock enable
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bit_offset: 9
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bit_size: 1
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- name: SPI1EN
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description: SPI1 clock enable
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bit_offset: 12
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bit_size: 1
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- name: USART1EN
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description: USART1 clock enable
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bit_offset: 14
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bit_size: 1
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- name: DBGEN
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description: DBG clock enable
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bit_offset: 22
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bit_size: 1
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fieldset/APB2RSTR:
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description: APB2 peripheral reset register
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fields:
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- name: SYSCFGRST
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description: System configuration controller reset
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bit_offset: 0
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bit_size: 1
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- name: TIM21RST
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description: TIM21 timer reset
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bit_offset: 2
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bit_size: 1
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- name: TIM22RST
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description: TIM22 timer reset
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bit_offset: 5
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bit_size: 1
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- name: ADCRST
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description: ADC interface reset
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bit_offset: 9
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bit_size: 1
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- name: SPI1RST
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description: SPI 1 reset
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bit_offset: 12
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bit_size: 1
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- name: USART1RST
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description: USART1 reset
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bit_offset: 14
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bit_size: 1
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- name: DBGRST
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description: DBG reset
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bit_offset: 22
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bit_size: 1
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fieldset/APB2SMENR:
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description: APB2 peripheral clock enable in sleep mode register
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fields:
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- name: SYSCFGSMEN
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description: System configuration controller clock enable during sleep mode
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bit_offset: 0
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bit_size: 1
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- name: TIM21SMEN
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description: TIM21 timer clock enable during sleep mode
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bit_offset: 2
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bit_size: 1
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- name: TIM22SMEN
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description: TIM22 timer clock enable during sleep mode
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bit_offset: 5
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bit_size: 1
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- name: ADCSMEN
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description: ADC clock enable during sleep mode
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bit_offset: 9
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bit_size: 1
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- name: SPI1SMEN
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description: SPI1 clock enable during sleep mode
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bit_offset: 12
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bit_size: 1
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- name: USART1SMEN
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description: USART1 clock enable during sleep mode
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bit_offset: 14
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bit_size: 1
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- name: DBGSMEN
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description: DBG clock enable during sleep mode
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bit_offset: 22
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bit_size: 1
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fieldset/CCIPR:
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description: Clock configuration register
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fields:
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- name: USART1SEL
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description: USART1 clock source selection
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bit_offset: 0
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bit_size: 2
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enum: UARTSEL
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- name: USART2SEL
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description: USART2 clock source selection
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bit_offset: 2
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bit_size: 2
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enum: UARTSEL
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- name: LPUART1SEL
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description: LPUART1 clock source selection
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bit_offset: 10
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bit_size: 2
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enum: UARTSEL
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- name: I2C1SEL
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description: I2C1 clock source selection
|
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bit_offset: 12
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bit_size: 2
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enum: ICSEL
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- name: I2C3SEL
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description: I2C3 clock source selection
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bit_offset: 16
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bit_size: 2
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enum: ICSEL
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- name: LPTIM1SEL
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description: Low Power Timer clock source selection
|
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bit_offset: 18
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bit_size: 2
|
|
enum: LPTIMSEL
|
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- name: HSI48MSEL
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description: 48 MHz HSI48 clock source selection
|
|
bit_offset: 26
|
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bit_size: 1
|
|
fieldset/CFGR:
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description: Clock configuration register
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fields:
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- name: SW
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description: System clock switch
|
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bit_offset: 0
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bit_size: 2
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enum: SW
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- name: SWS
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description: System clock switch status
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bit_offset: 2
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bit_size: 2
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enum: SW
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- name: HPRE
|
|
description: AHB prescaler
|
|
bit_offset: 4
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bit_size: 4
|
|
enum: HPRE
|
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- name: PPRE1
|
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description: APB low-speed prescaler (APB1)
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|
bit_offset: 8
|
|
bit_size: 3
|
|
enum: PPRE
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- name: PPRE2
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description: APB high-speed prescaler (APB2)
|
|
bit_offset: 11
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bit_size: 3
|
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enum: PPRE
|
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- name: STOPWUCK
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description: Wake-up from stop clock selection
|
|
bit_offset: 15
|
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bit_size: 1
|
|
enum: STOPWUCK
|
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- name: PLLSRC
|
|
description: PLL entry clock source
|
|
bit_offset: 16
|
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bit_size: 1
|
|
enum: PLLSRC
|
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- name: PLLMUL
|
|
description: PLL multiplication factor
|
|
bit_offset: 18
|
|
bit_size: 4
|
|
enum: PLLMUL
|
|
- name: PLLDIV
|
|
description: PLL output division
|
|
bit_offset: 22
|
|
bit_size: 2
|
|
enum: PLLDIV
|
|
- name: MCOSEL
|
|
description: Microcontroller clock output selection
|
|
bit_offset: 24
|
|
bit_size: 4
|
|
enum: MCOSEL
|
|
- name: MCOPRE
|
|
description: Microcontroller clock output prescaler
|
|
bit_offset: 28
|
|
bit_size: 3
|
|
enum: MCOPRE
|
|
fieldset/CICR:
|
|
description: Clock interrupt clear register
|
|
fields:
|
|
- name: LSIRDYC
|
|
description: LSI ready Interrupt clear
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYC
|
|
description: LSE ready Interrupt clear
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: HSIRDYC
|
|
description: HSI ready Interrupt clear
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSERDYC
|
|
description: HSE ready Interrupt clear
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: PLLRDYC
|
|
description: PLL ready Interrupt clear
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: MSIRDYC
|
|
description: MSI ready Interrupt clear
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: HSI48RDYC
|
|
description: HSI48 ready Interrupt clear
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: CSSLSEC
|
|
description: LSE Clock Security System Interrupt clear
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: CSSHSEC
|
|
description: Clock Security System Interrupt clear
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
fieldset/CIER:
|
|
description: Clock interrupt enable register
|
|
fields:
|
|
- name: LSIRDYIE
|
|
description: LSI ready interrupt flag
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYIE
|
|
description: LSE ready interrupt flag
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: HSIRDYIE
|
|
description: HSI ready interrupt flag
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSERDYIE
|
|
description: HSE ready interrupt flag
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: PLLRDYIE
|
|
description: PLL ready interrupt flag
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: MSIRDYIE
|
|
description: MSI ready interrupt flag
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: HSI48RDYIE
|
|
description: HSI48 ready interrupt flag
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: CSSLSE
|
|
description: LSE CSS interrupt flag
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
fieldset/CIFR:
|
|
description: Clock interrupt flag register
|
|
fields:
|
|
- name: LSIRDYF
|
|
description: LSI ready interrupt flag
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYF
|
|
description: LSE ready interrupt flag
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: HSIRDYF
|
|
description: HSI ready interrupt flag
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSERDYF
|
|
description: HSE ready interrupt flag
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: PLLRDYF
|
|
description: PLL ready interrupt flag
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: MSIRDYF
|
|
description: MSI ready interrupt flag
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: HSI48RDYF
|
|
description: HSI48 ready interrupt flag
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: CSSLSEF
|
|
description: LSE Clock Security System Interrupt flag
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: CSSHSEF
|
|
description: Clock Security System Interrupt flag
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
fieldset/CR:
|
|
description: Clock control register
|
|
fields:
|
|
- name: HSION
|
|
description: 16 MHz high-speed internal clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: HSIKERON
|
|
description: High-speed internal clock enable bit for some IP kernels
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: HSIRDY
|
|
description: Internal high-speed clock ready flag
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSIDIVEN
|
|
description: HSIDIVEN
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: HSIDIVF
|
|
description: HSIDIVF
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: HSIOUTEN
|
|
description: 16 MHz high-speed internal clock output enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: MSION
|
|
description: MSI clock enable
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: MSIRDY
|
|
description: MSI clock ready flag
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HSEON
|
|
description: HSE clock enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: HSERDY
|
|
description: HSE clock ready flag
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: HSEBYP
|
|
description: HSE clock bypass
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: CSSHSEON
|
|
description: Clock security system on HSE enable
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: RTCPRE
|
|
description: TC/LCD prescaler
|
|
bit_offset: 20
|
|
bit_size: 2
|
|
enum: RTCPRE
|
|
- name: PLLON
|
|
description: PLL enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: PLLRDY
|
|
description: PLL clock ready flag
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
fieldset/CRRCR:
|
|
description: Clock recovery RC register
|
|
fields:
|
|
- name: HSI48ON
|
|
description: 48MHz HSI clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: HSI48RDY
|
|
description: 48MHz HSI clock ready flag
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: HSI48DIV6EN
|
|
description: 48 MHz HSI clock divided by 6 output enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSI48CAL
|
|
description: 48 MHz HSI clock calibration
|
|
bit_offset: 8
|
|
bit_size: 8
|
|
fieldset/CSR:
|
|
description: Control and status register
|
|
fields:
|
|
- name: LSION
|
|
description: Internal low-speed oscillator enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSIRDY
|
|
description: Internal low-speed oscillator ready
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: LSEON
|
|
description: External low-speed oscillator enable
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LSERDY
|
|
description: External low-speed oscillator ready
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: LSEBYP
|
|
description: External low-speed oscillator bypass
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: LSEDRV
|
|
description: LSEDRV
|
|
bit_offset: 11
|
|
bit_size: 2
|
|
enum: LSEDRV
|
|
- name: CSSLSEON
|
|
description: CSSLSEON
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: CSSLSED
|
|
description: CSS on LSE failure detection flag
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: RTCSEL
|
|
description: RTC and LCD clock source selection
|
|
bit_offset: 16
|
|
bit_size: 2
|
|
enum: RTCSEL
|
|
- name: RTCEN
|
|
description: RTC clock enable
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: RTCRST
|
|
description: RTC software reset
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: RMVF
|
|
description: Remove reset flag
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: FWRSTF
|
|
description: Firewall reset flag
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: OBLRSTF
|
|
description: OBLRSTF
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: PINRSTF
|
|
description: PIN reset flag
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: PORRSTF
|
|
description: POR/PDR reset flag
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: SFTRSTF
|
|
description: Software reset flag
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: IWDGRSTF
|
|
description: Independent watchdog reset flag
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: WWDGRSTF
|
|
description: Window watchdog reset flag
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: LPWRRSTF
|
|
description: Low-power reset flag
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/GPIOENR:
|
|
description: GPIO clock enable register
|
|
fields:
|
|
- name: GPIOAEN
|
|
description: IO port A clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: GPIOBEN
|
|
description: IO port B clock enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: GPIOCEN
|
|
description: IO port A clock enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: GPIODEN
|
|
description: I/O port D clock enable
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: GPIOEEN
|
|
description: IO port E clock enable
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: GPIOHEN
|
|
description: I/O port H clock enable
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
fieldset/GPIORSTR:
|
|
description: GPIO reset register
|
|
fields:
|
|
- name: GPIOARST
|
|
description: I/O port A reset
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: GPIOBRST
|
|
description: I/O port B reset
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: GPIOCRST
|
|
description: I/O port A reset
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: GPIODRST
|
|
description: I/O port D reset
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: GPIOERST
|
|
description: I/O port E reset
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: GPIOHRST
|
|
description: I/O port H reset
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
fieldset/GPIOSMEN:
|
|
description: GPIO clock enable in sleep mode register
|
|
fields:
|
|
- name: GPIOASMEN
|
|
description: Port A clock enable during Sleep mode
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: GPIOBSMEN
|
|
description: Port B clock enable during Sleep mode
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: GPIOCSMEN
|
|
description: Port C clock enable during Sleep mode
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: GPIODSMEN
|
|
description: Port D clock enable during Sleep mode
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: GPIOESMEN
|
|
description: Port E clock enable during Sleep mode
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: GPIOHSMEN
|
|
description: Port H clock enable during Sleep mode
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
fieldset/ICSCR:
|
|
description: Internal clock sources calibration register
|
|
fields:
|
|
- name: HSICAL
|
|
description: nternal high speed clock calibration
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
- name: HSITRIM
|
|
description: High speed internal clock trimming
|
|
bit_offset: 8
|
|
bit_size: 5
|
|
- name: MSIRANGE
|
|
description: MSI clock ranges
|
|
bit_offset: 13
|
|
bit_size: 3
|
|
enum: MSIRANGE
|
|
- name: MSICAL
|
|
description: MSI clock calibration
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
- name: MSITRIM
|
|
description: MSI clock trimming
|
|
bit_offset: 24
|
|
bit_size: 8
|
|
enum/HPRE:
|
|
bit_size: 4
|
|
variants:
|
|
- name: Div1
|
|
description: system clock not divided
|
|
value: 0
|
|
- name: Div2
|
|
description: system clock divided by 2
|
|
value: 8
|
|
- name: Div4
|
|
description: system clock divided by 4
|
|
value: 9
|
|
- name: Div8
|
|
description: system clock divided by 8
|
|
value: 10
|
|
- name: Div16
|
|
description: system clock divided by 16
|
|
value: 11
|
|
- name: Div64
|
|
description: system clock divided by 64
|
|
value: 12
|
|
- name: Div128
|
|
description: system clock divided by 128
|
|
value: 13
|
|
- name: Div256
|
|
description: system clock divided by 256
|
|
value: 14
|
|
- name: Div512
|
|
description: system clock divided by 512
|
|
value: 15
|
|
enum/ICSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: PCLK1
|
|
description: APB clock selected as peripheral clock
|
|
value: 0
|
|
- name: SYS
|
|
description: System clock selected as peripheral clock
|
|
value: 1
|
|
- name: HSI
|
|
description: HSI clock selected as peripheral clock
|
|
value: 2
|
|
enum/LPTIMSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: PCLK1
|
|
description: APB clock selected as Timer clock
|
|
value: 0
|
|
- name: LSI
|
|
description: LSI clock selected as Timer clock
|
|
value: 1
|
|
- name: HSI
|
|
description: HSI clock selected as Timer clock
|
|
value: 2
|
|
- name: LSE
|
|
description: LSE clock selected as Timer clock
|
|
value: 3
|
|
enum/LSEDRV:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Low
|
|
description: Low driving capability
|
|
value: 0
|
|
- name: MediumLow
|
|
description: Medium low driving capability
|
|
value: 1
|
|
- name: MediumHigh
|
|
description: Medium high driving capability
|
|
value: 2
|
|
- name: High
|
|
description: High driving capability
|
|
value: 3
|
|
enum/MCOPRE:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Div1
|
|
description: No division
|
|
value: 0
|
|
- name: Div2
|
|
description: Division by 2
|
|
value: 1
|
|
- name: Div4
|
|
description: Division by 4
|
|
value: 2
|
|
- name: Div8
|
|
description: Division by 8
|
|
value: 3
|
|
- name: Div16
|
|
description: Division by 16
|
|
value: 4
|
|
enum/MCOSEL:
|
|
bit_size: 4
|
|
variants:
|
|
- name: DISABLE
|
|
description: No clock
|
|
value: 0
|
|
- name: SYS
|
|
description: SYSCLK clock selected
|
|
value: 1
|
|
- name: HSI
|
|
description: HSI oscillator clock selected
|
|
value: 2
|
|
- name: MSI
|
|
description: MSI oscillator clock selected
|
|
value: 3
|
|
- name: HSE
|
|
description: HSE oscillator clock selected
|
|
value: 4
|
|
- name: PLL
|
|
description: PLL clock selected
|
|
value: 5
|
|
- name: LSI
|
|
description: LSI oscillator clock selected
|
|
value: 6
|
|
- name: LSE
|
|
description: LSE oscillator clock selected
|
|
value: 7
|
|
enum/MSIRANGE:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Range0
|
|
description: range 0 around 65.536 kHz
|
|
value: 0
|
|
- name: Range1
|
|
description: range 1 around 131.072 kHz
|
|
value: 1
|
|
- name: Range2
|
|
description: range 2 around 262.144 kHz
|
|
value: 2
|
|
- name: Range3
|
|
description: range 3 around 524.288 kHz
|
|
value: 3
|
|
- name: Range4
|
|
description: range 4 around 1.048 MHz
|
|
value: 4
|
|
- name: Range5
|
|
description: range 5 around 2.097 MHz (reset value)
|
|
value: 5
|
|
- name: Range6
|
|
description: range 6 around 4.194 MHz
|
|
value: 6
|
|
- name: Range7
|
|
description: not allowed
|
|
value: 7
|
|
enum/PLLDIV:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Div2
|
|
description: PLLVCO / 2
|
|
value: 1
|
|
- name: Div3
|
|
description: PLLVCO / 3
|
|
value: 2
|
|
- name: Div4
|
|
description: PLLVCO / 4
|
|
value: 3
|
|
enum/PLLMUL:
|
|
bit_size: 4
|
|
variants:
|
|
- name: Mul3
|
|
description: PLL clock entry x 3
|
|
value: 0
|
|
- name: Mul4
|
|
description: PLL clock entry x 4
|
|
value: 1
|
|
- name: Mul6
|
|
description: PLL clock entry x 6
|
|
value: 2
|
|
- name: Mul8
|
|
description: PLL clock entry x 8
|
|
value: 3
|
|
- name: Mul12
|
|
description: PLL clock entry x 12
|
|
value: 4
|
|
- name: Mul16
|
|
description: PLL clock entry x 16
|
|
value: 5
|
|
- name: Mul24
|
|
description: PLL clock entry x 24
|
|
value: 6
|
|
- name: Mul32
|
|
description: PLL clock entry x 32
|
|
value: 7
|
|
- name: Mul48
|
|
description: PLL clock entry x 48
|
|
value: 8
|
|
enum/PLLSRC:
|
|
bit_size: 1
|
|
variants:
|
|
- name: HSI
|
|
description: HSI selected as PLL input clock
|
|
value: 0
|
|
- name: HSE
|
|
description: HSE selected as PLL input clock
|
|
value: 1
|
|
enum/PPRE:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Div1
|
|
description: HCLK not divided
|
|
value: 0
|
|
- name: Div2
|
|
description: HCLK divided by 2
|
|
value: 4
|
|
- name: Div4
|
|
description: HCLK divided by 4
|
|
value: 5
|
|
- name: Div8
|
|
description: HCLK divided by 8
|
|
value: 6
|
|
- name: Div16
|
|
description: HCLK divided by 16
|
|
value: 7
|
|
enum/RTCPRE:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Div2
|
|
description: HSE divided by 2
|
|
value: 0
|
|
- name: Div4
|
|
description: HSE divided by 4
|
|
value: 1
|
|
- name: Div8
|
|
description: HSE divided by 8
|
|
value: 2
|
|
- name: Div16
|
|
description: HSE divided by 16
|
|
value: 3
|
|
enum/RTCSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: DISABLE
|
|
description: No clock
|
|
value: 0
|
|
- name: LSE
|
|
description: LSE oscillator clock used as RTC clock
|
|
value: 1
|
|
- name: LSI
|
|
description: LSI oscillator clock used as RTC clock
|
|
value: 2
|
|
- name: HSE
|
|
description: HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock
|
|
value: 3
|
|
enum/STOPWUCK:
|
|
bit_size: 1
|
|
variants:
|
|
- name: MSI
|
|
description: Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock
|
|
value: 0
|
|
- name: HSI
|
|
description: Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock (or HSI/4 if HSIDIVEN=1)
|
|
value: 1
|
|
enum/SW:
|
|
bit_size: 2
|
|
variants:
|
|
- name: MSI
|
|
description: MSI oscillator used as system clock
|
|
value: 0
|
|
- name: HSI
|
|
description: HSI oscillator used as system clock
|
|
value: 1
|
|
- name: HSE
|
|
description: HSE oscillator used as system clock
|
|
value: 2
|
|
- name: PLL1_P
|
|
description: PLL used as system clock
|
|
value: 3
|
|
enum/UARTSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: PCLK1
|
|
description: APB clock selected as peripheral clock
|
|
value: 0
|
|
- name: SYS
|
|
description: System clock selected as peripheral clock
|
|
value: 1
|
|
- name: HSI
|
|
description: HSI clock selected as peripheral clock
|
|
value: 2
|
|
- name: LSE
|
|
description: LSE clock selected as peripheral clock
|
|
value: 3
|