stm32-data/data/registers/pwr_wba.yaml

block/PWR:
  description: Power control
  items:
  - name: CR1
    description: control register 1
    byte_offset: 0
    fieldset: CR1
  - name: CR2
    description: control register 2
    byte_offset: 4
    fieldset: CR2
  - name: CR3
    description: control register 3
    byte_offset: 8
    fieldset: CR3
  - name: VOSR
    description: voltage scaling register
    byte_offset: 12
    fieldset: VOSR
  - name: SVMCR
    description: supply voltage monitoring control register
    byte_offset: 16
    fieldset: SVMCR
  - name: WUCR1
    description: wakeup control register 1
    byte_offset: 20
    fieldset: WUCR1
  - name: WUCR2
    description: wakeup control register 2
    byte_offset: 24
    fieldset: WUCR2
  - name: WUCR3
    description: wakeup control register 3
    byte_offset: 28
    fieldset: WUCR3
  - name: DBPCR
    description: disable Backup domain register
    byte_offset: 40
    fieldset: DBPCR
  - name: SECCFGR
    description: security configuration register
    byte_offset: 48
    fieldset: SECCFGR
  - name: PRIVCFGR
    description: privilege control register
    byte_offset: 52
    fieldset: PRIVCFGR
  - name: SR
    description: status register
    byte_offset: 56
    fieldset: SR
  - name: SVMSR
    description: supply voltage monitoring status register
    byte_offset: 60
    fieldset: SVMSR
  - name: WUSR
    description: wakeup status register
    byte_offset: 68
    fieldset: WUSR
  - name: WUSCR
    description: wakeup status clear register
    byte_offset: 72
    fieldset: WUSCR
  - name: IORETENR
    description: port Standby IO retention enable register
    array:
      len: 8
      stride: 8
    byte_offset: 80
    fieldset: IORETENR
  - name: IORETRA
    description: port Standby IO retention status register
    array:
      len: 8
      stride: 8
    byte_offset: 84
    fieldset: IORETR
  - name: RADIOSCR
    description: 2.4 GHz RADIO status and control register
    byte_offset: 256
    fieldset: RADIOSCR
fieldset/CR1:
  description: control register 1
  fields:
  - name: LPMS
    description: "Low-power mode selection\r These bits select the low-power mode entered when the CPU enters the SleepDeep mode.\r 10x: Standby mode\r others reserved"
    bit_offset: 0
    bit_size: 3
    enum: LPMS
  - name: R2RSB1
    description: "SRAM2 retention in Standby mode\r This bit is used to keep the SRAM2 content in Standby retention mode."
    bit_offset: 5
    bit_size: 1
    enum: RRSB
  - name: ULPMEN
    description: "BOR0 ultra-low-power mode. \r This bit is used to reduce the consumption by configuring the BOR0 in discontinuous mode for Stop 1 and Standby modes. Discontinuous mode is only available when BOR levels 1 to 4 and PVD are disabled.\r Note: This bit must be set to reach the lowest power consumption in the low-power modes.\r Note: This bit must not be set together with autonomous peripherals using HSI as kernel clock.\r Note: When BOR level 1 to 4 or PVD is enabled continuous mode applies independent from ULPMEN."
    bit_offset: 7
    bit_size: 1
  - name: RADIORSB
    description: "2.4 GHz RADIO SRAMs (RXTXRAM and Sequence RAM) and Sleep clock retention in Standby mode.\r This bit is used to keep the 2.4 GHz RADIO SRAMs content in Standby retention mode and the 2.4 GHz RADIO sleep timer counter operational."
    bit_offset: 9
    bit_size: 1
    enum: RADIORSB
  - name: R1RSB1
    description: "SRAM1 retention in Standby mode\r This bit is used to keep the SRAM1 content in Standby retention mode."
    bit_offset: 12
    bit_size: 1
    enum: RRSB
fieldset/CR2:
  description: control register 2
  fields:
  - name: SRAM1PDS1
    description: "SRAM1 power-down in Stop modes (Stop 0, 1)\r Note: The SRAM1 retention in Standby mode is controlled by R1RSB1 bit in CR1."
    bit_offset: 0
    bit_size: 1
    enum: SRAMPDS
  - name: SRAM2PDS1
    description: "SRAM2 power-down in Stop modes (Stop 0, 1)\r Note: The SRAM2 retention in Standby mode is controlled by R2RSB1 bit in CR1."
    bit_offset: 4
    bit_size: 1
    enum: SRAMPDS
  - name: ICRAMPDS
    description: ICACHE SRAM power-down in Stop modes (Stop 0, 1)
    bit_offset: 8
    bit_size: 1
    enum: ICRAMPDS
  - name: FLASHFWU
    description: "Flash memory fast wakeup from Stop modes (Stop 0, 1)\r This bit is used to obtain the best trade-off between low-power consumption and wakeup time when exiting the Stop 0 or Stop 1 modes.\r When this bit is set, the Flash memory remains in normal mode in Stop 0 and Stop 1 modes, which offers a faster startup time with higher consumption."
    bit_offset: 14
    bit_size: 1
    enum: FLASHFWU
fieldset/CR3:
  description: control register 3
  fields:
  - name: FSTEN
    description: Fast soft start
    bit_offset: 2
    bit_size: 1
fieldset/DBPCR:
  description: disable Backup domain register
  fields:
  - name: DBP
    description: "Disable Backup domain write protection\r In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers."
    bit_offset: 0
    bit_size: 1
fieldset/IORETENR:
  description: port A Standby IO retention enable register
  fields:
  - name: EN
    description: "Port A Standby GPIO retention enable\r Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV.\r When set, each bit enables the Standby GPIO retention feature for PAy"
    bit_offset: 0
    bit_size: 1
    array:
      len: 16
      stride: 1
fieldset/IORETR:
  description: port A Standby IO retention status register
  fields:
  - name: RET
    description: "Port A Standby GPIO retention active\r Access can be protected by GPIOA SECy, privilege protection is controlled by SPRIV or NSPRIV."
    bit_offset: 0
    bit_size: 1
    array:
      len: 16
      stride: 1
fieldset/PRIVCFGR:
  description: privilege control register
  fields:
  - name: SPRIV
    description: "secure functions privilege configuration\r This bit is set and reset by software.\r It can be written only by a secure privileged access."
    bit_offset: 0
    bit_size: 1
    enum: PRIV
  - name: NSPRIV
    description: "non-secure functions privilege configuration\r This bit is set and reset by software.\r It can be written only by privileged access, secure or non-secure."
    bit_offset: 1
    bit_size: 1
    enum: PRIV
fieldset/RADIOSCR:
  description: 2.4 GHz RADIO status and control register
  fields:
  - name: MODE
    description: "2.4 GHz RADIO operating mode.\r 1x: 2.4 GHz RADIO active mode"
    bit_offset: 0
    bit_size: 2
    enum: MODE
  - name: PHYMODE
    description: 2.4 GHz RADIO PHY operating mode
    bit_offset: 2
    bit_size: 1
  - name: ENCMODE
    description: 2.4 GHz RADIO encryption function operating mode
    bit_offset: 3
    bit_size: 1
  - name: RFVDDHPA
    description: "2.4 GHz RADIO VDDHPA control word.\r Bits [3:0] see Table 81: PA output power table format for definition.\r Bit [4] rf_event."
    bit_offset: 8
    bit_size: 5
  - name: REGPARDYVDDRFPA
    description: "Ready bit for V<sub>DDHPA</sub> voltage level when selecting VDDRFPA input.\r Note: REGPARDYVDDRFPA does not allow to detect correct V<sub>DDHPA</sub> voltage level when request to lower the level."
    bit_offset: 15
    bit_size: 1
    enum: REGPARDYVDDRFPA
fieldset/SECCFGR:
  description: security configuration register
  fields:
  - name: WUP1SEC
    description: WUP1 secure protection
    bit_offset: 0
    bit_size: 1
    array:
      len: 8
      stride: 1
    enum: SEC
  - name: LPMSEC
    description: Low-power modes secure protection
    bit_offset: 12
    bit_size: 1
    enum: SEC
  - name: VDMSEC
    description: Voltage detection secure protection
    bit_offset: 13
    bit_size: 1
    enum: SEC
  - name: VBSEC
    description: Backup domain secure protection
    bit_offset: 14
    bit_size: 1
    enum: SEC
fieldset/SR:
  description: status register
  fields:
  - name: CSSF
    description: "Clear Stop and Standby flags\r Access can be secured by LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.\r Writing 1 to this bit clears the STOPF and SBF flags."
    bit_offset: 0
    bit_size: 1
  - name: STOPF
    description: "Stop flag\r This bit is set by hardware when the device enters a Stop or Standby mode at the same time as the sysclk has been set by hardware to select HSI. It’s cleared by software by writing 1 to the CSSF bit and by hardware when SBF is set."
    bit_offset: 1
    bit_size: 1
  - name: SBF
    description: "Standby flag\r This bit is set by hardware when the device enters the Standby mode and the CPU restart from its reset vector. It’s cleared by writing 1 to the CSSF bit, or by a power-on reset. It is not cleared by the system reset."
    bit_offset: 2
    bit_size: 1
fieldset/SVMCR:
  description: supply voltage monitoring control register
  fields:
  - name: PVDE
    description: Programmable voltage detector enable
    bit_offset: 4
    bit_size: 1
  - name: PVDLS
    description: "Programmable voltage detector level selection\r These bits select the voltage threshold detected by the programmable voltage detector:"
    bit_offset: 5
    bit_size: 3
    enum: PVDLS
fieldset/SVMSR:
  description: supply voltage monitoring status register
  fields:
  - name: PVDO
    description: Programmable voltage detector output
    bit_offset: 4
    bit_size: 1
    enum: PVDO
  - name: ACTVOSRDY
    description: Voltage level ready for currently used VOS
    bit_offset: 15
    bit_size: 1
  - name: ACTVOS
    description: "VOS currently applied to V<sub>CORE</sub>\r This field provides the last VOS value."
    bit_offset: 16
    bit_size: 1
    enum: ACTVOS
fieldset/VOSR:
  description: voltage scaling register
  fields:
  - name: VOSRDY
    description: "Ready bit for V<sub>CORE</sub> voltage scaling output selection\r Set and cleared by hardware. When decreasing the voltage scaling range, VOSRDY must be one before increasing the SYSCLK frequency."
    bit_offset: 15
    bit_size: 1
  - name: VOS
    description: "Voltage scaling range selection\r Set a and cleared by software.\r Cleared by hardware when entering Stop 1 mode.\r Access can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
    bit_offset: 16
    bit_size: 1
    enum: VOS
fieldset/WUCR1:
  description: wakeup control register 1
  fields:
  - name: WUPEN
    description: "Wakeup and interrupt pin WKUP1 enable\r Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
    bit_offset: 0
    bit_size: 1
    array:
      len: 8
      stride: 1
fieldset/WUCR2:
  description: wakeup control register 2
  fields:
  - name: WUPP
    description: "Wakeup pin WKUP1 polarity.\r This bit must be configured when WUPEN1 = 0.\r Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
    bit_offset: 0
    bit_size: 1
    array:
      len: 8
      stride: 1
    enum: WUPP
fieldset/WUCR3:
  description: wakeup control register 3
  fields:
  - name: WUSEL1
    description: "Wakeup and interrupt pin WKUP1 selection\r This field must be configured when WUPEN1 = 0.\r Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
    bit_offset: 0
    bit_size: 2
    enum: WUSEL
  - name: WUSEL2
    description: "Wakeup and interrupt pin WKUP2 selection\r This field must be configured when WUPEN2 = 0.\r Access can be secured by WUP2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
    bit_offset: 2
    bit_size: 2
    enum: WUSEL
  - name: WUSEL3
    description: "Wakeup and interrupt pin WKUP3 selection\r This field must be configured when WUPEN3 = 0.\r Access can be secured by WUP3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
    bit_offset: 4
    bit_size: 2
    enum: WUSEL
  - name: WUSEL4
    description: "Wakeup and interrupt pin WKUP4 selection\r This field must be configured when WUPEN4 = 0.\r Access can be secured by WUP4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
    bit_offset: 6
    bit_size: 2
    enum: WUSEL
  - name: WUSEL5
    description: "Wakeup and interrupt pin WKUP5 selection\r This field must be configured when WUPEN5 = 0.\r Access can be secured by WUP5SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
    bit_offset: 8
    bit_size: 2
    enum: WUSEL
  - name: WUSEL6
    description: "Wakeup and interrupt pin WKUP6 selection\r This field must be configured when WUPEN6 = 0.\r Access can be secured by WUP6SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
    bit_offset: 10
    bit_size: 2
    enum: WUSEL
  - name: WUSEL7
    description: "Wakeup and interrupt pin WKUP7 selection\r This field must be configured when WUPEN7 = 0.\r Access can be secured by WUP7SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
    bit_offset: 12
    bit_size: 2
    enum: WUSEL
  - name: WUSEL8
    description: "Wakeup and interrupt pin WKUP8 selection\r This field must be configured when WUPEN8 = 0.\r Access can be secured by WUP8SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV."
    bit_offset: 14
    bit_size: 2
    enum: WUSEL
fieldset/WUSCR:
  description: wakeup status clear register
  fields:
  - name: CWUF
    description: "Clear wakeup flag 1\r Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.\r Writing 1 to this bit clears the WUF1 flag in WUSR."
    bit_offset: 0
    bit_size: 1
    array:
      len: 8
      stride: 1
fieldset/WUSR:
  description: wakeup status register
  fields:
  - name: WUF
    description: "Wakeup and interrupt pending flag 1\r This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR or by hardware when WUPEN1 = 0."
    bit_offset: 0
    bit_size: 1
    array:
      len: 8
      stride: 1
enum/ACTVOS:
  bit_size: 1
  variants:
  - name: Range2
    description: Range 2 (lowest power)
    value: 0
  - name: Range1
    description: Range 1 (highest frequency)
    value: 1
enum/FLASHFWU:
  bit_size: 1
  variants:
  - name: LowPower
    description: Flash memory enters low-power mode in Stop 0 and Stop 1 modes (lower-power consumption).
    value: 0
  - name: Normal
    description: Flash memory remains in normal mode in Stop 0 and Stop 1 modes (faster wakeup time).
    value: 1
enum/ICRAMPDS:
  bit_size: 1
  variants:
  - name: Retained
    description: ICACHE SRAM content retained in Stop modes
    value: 0
  - name: NotRetained
    description: ICACHE SRAM content lost in Stop modes
    value: 1
enum/LPMS:
  bit_size: 3
  variants:
  - name: Stop0
    description: Stop 0 mode
    value: 0
  - name: Stop1
    description: Stop 1 mode
    value: 1
enum/MODE:
  bit_size: 2
  variants:
  - name: DeepSleep
    description: 2.4 GHz RADIO deep sleep mode
    value: 0
  - name: Sleep
    description: 2.4 GHz RADIO sleep mode
    value: 1
enum/PRIV:
  bit_size: 1
  variants:
  - name: Unprivileged
    description: Read and write to non-secure functions can be done by privileged or unprivileged access.
    value: 0
  - name: Privileged
    description: Read and write to non-secure functions can be done by privileged access only.
    value: 1
enum/PVDLS:
  bit_size: 3
  variants:
  - name: v20
    description: VPVD0 around 2.0 V
    value: 0
  - name: v22
    description: VPVD1 around 2.2 V
    value: 1
  - name: v24
    description: VPVD2 around 2.4 V
    value: 2
  - name: v25
    description: VPVD3 around 2.5 V
    value: 3
  - name: v26
    description: VPVD4 around 2.6 V
    value: 4
  - name: v28
    description: VPVD5 around 2.8 V
    value: 5
  - name: v29
    description: VPVD6 around 2.9 V
    value: 6
  - name: pvd_in
    description: External input analog voltage PVD_IN (compared internally to VREFINT)
    value: 7
enum/PVDO:
  bit_size: 1
  variants:
  - name: AboveOrEqual
    description: VDD is equal or above the PVD threshold selected by PVDLS[2:0].
    value: 0
  - name: Below
    description: VDD is below the PVD threshold selected by PVDLS[2:0].
    value: 1
enum/RADIORSB:
  bit_size: 1
  variants:
  - name: NotRetained
    description: 2.4 GHz RADIO SRAMs and sleep timer content not retained in Standby mode
    value: 0
  - name: Retained
    description: 2.4 GHz RADIO SRAMs and sleep timer content retained in Standby mode
    value: 1
enum/REGPARDYVDDRFPA:
  bit_size: 1
  variants:
  - name: NotReady
    description: Not ready, V<sub>DDHPA</sub> voltage level < REGPAVOS selected supply level
    value: 0
  - name: Ready
    description: Ready, V<sub>DDHPA</sub> voltage level ≥ REGPAVOS selected supply level
    value: 1
enum/RRSB:
  bit_size: 1
  variants:
  - name: B_0x0
    description: SRAM2 content not retained in Standby mode
    value: 0
  - name: B_0x1
    description: SRAM2 content retained in Standby mode
    value: 1
enum/SEC:
  bit_size: 1
  variants:
  - name: NotSecure
    description: SVMCR and CR3 can be read and written with secure or non-secure access.
    value: 0
  - name: Secure
    description: SVMCR and CR3 can be read and written only with secure access.
    value: 1
enum/SRAMPDS:
  bit_size: 1
  variants:
  - name: PoweredOn
    description: SRAM1 content retained in Stop modes
    value: 0
  - name: PoweredOff
    description: SRAM1 content lost in Stop modes
    value: 1
enum/VOS:
  bit_size: 1
  variants:
  - name: Range2
    description: Range 2 (lowest power)
    value: 0
  - name: Range1
    description: Range 1 (highest frequency).
    value: 1
enum/WUPP:
  bit_size: 1
  variants:
  - name: High
    description: Detection on high level (rising edge)
    value: 0
  - name: Low
    description: Detection on low level (falling edge)
    value: 1
enum/WUSEL:
  bit_size: 2
  variants:
  - name: B_0x0
    description: reserved
    value: 0
  - name: B_0x1
    description: WKUP3_1
    value: 1
  - name: B_0x2
    description: WKUP3_2
    value: 2
  - name: B_0x3
    description: reserved
    value: 3