stm32-data/data/registers/i3c_v1.yaml

block/DataRegs:
  items:
  - name: DR
    description: I3C transmit data byte register.
    byte_offset: 0
    fieldset: DR
  - name: DWR
    description: I3C transmit data word register.
    byte_offset: 4
    fieldset: DWR
block/I3C:
  description: Improved inter-integrated circuit.
  items:
  - name: CR
    description: I3C message control register.
    byte_offset: 0
    fieldset: CR
  - name: CR_ALTERNATE
    description: I3C message control register alternate.
    byte_offset: 0
    fieldset: CR_ALTERNATE
  - name: CFGR
    description: I3C configuration register.
    byte_offset: 4
    fieldset: CFGR
  - name: RxDataRegs
    byte_offset: 16
    block: DataRegs
  - name: TxDataRegs
    byte_offset: 24
    block: DataRegs
  - name: IBIDR
    description: I3C IBI payload data register.
    byte_offset: 32
    fieldset: IBIDR
  - name: TGTTDR
    description: I3C target transmit configuration register.
    byte_offset: 36
    fieldset: TGTTDR
  - name: SR
    description: I3C status register.
    byte_offset: 48
    fieldset: SR
  - name: SER
    description: I3C status error register.
    byte_offset: 52
    fieldset: SER
  - name: RMR
    description: I3C received message register.
    byte_offset: 64
    fieldset: RMR
  - name: EVR
    description: I3C event register.
    byte_offset: 80
    fieldset: EVR
  - name: IER
    description: I3C interrupt enable register.
    byte_offset: 84
    fieldset: IER
  - name: CEVR
    description: I3C clear event register.
    byte_offset: 88
    fieldset: CEVR
  - name: DEVR0
    description: I3C own device characteristics register.
    byte_offset: 96
    fieldset: DEVR0
  - name: DEVR1
    description: I3C device 1 characteristics register.
    byte_offset: 100
    fieldset: DEVR1
  - name: DEVR2
    description: I3C device 2 characteristics register.
    byte_offset: 104
    fieldset: DEVR2
  - name: DEVR3
    description: I3C device 3 characteristics register.
    byte_offset: 108
    fieldset: DEVR3
  - name: DEVR4
    description: I3C device 4 characteristics register.
    byte_offset: 112
    fieldset: DEVR4
  - name: MAXRLR
    description: I3C maximum read length register.
    byte_offset: 144
    fieldset: MAXRLR
  - name: MAXWLR
    description: I3C maximum write length register.
    byte_offset: 148
    fieldset: MAXWLR
  - name: TIMINGR0
    description: I3C timing register 0.
    byte_offset: 160
    fieldset: TIMINGR0
  - name: TIMINGR1
    description: I3C timing register 1.
    byte_offset: 164
    fieldset: TIMINGR1
  - name: TIMINGR2
    description: I3C timing register 2.
    byte_offset: 168
    fieldset: TIMINGR2
  - name: BCR
    description: I3C bus characteristics register.
    byte_offset: 192
    fieldset: BCR
  - name: DCR
    description: I3C device characteristics register.
    byte_offset: 196
    fieldset: DCR
  - name: GETCAPR
    description: I3C get capability register.
    byte_offset: 200
    fieldset: GETCAPR
  - name: CRCAPR
    description: I3C controller-role capability register.
    byte_offset: 204
    fieldset: CRCAPR
  - name: GETMXDSR
    description: I3C get capability register.
    byte_offset: 208
    fieldset: GETMXDSR
  - name: EPIDR
    description: I3C extended provisioned ID register.
    byte_offset: 212
    fieldset: EPIDR
fieldset/BCR:
  description: I3C bus characteristics register.
  fields:
  - name: BCR0
    description: max data speed limitation.
    bit_offset: 0
    bit_size: 1
  - name: BCR2
    description: in-band interrupt (IBI) payload.
    bit_offset: 2
    bit_size: 1
  - name: BCR6
    description: controller capable.
    bit_offset: 6
    bit_size: 1
fieldset/CEVR:
  description: I3C clear event register.
  fields:
  - name: CFCF
    description: clear frame complete flag (whatever the I3C is acting as controller/target).
    bit_offset: 9
    bit_size: 1
  - name: CRXTGTENDF
    description: clear target-initiated read end flag (when the I3C is acting as controller).
    bit_offset: 10
    bit_size: 1
  - name: CERRF
    description: clear error flag (whatever the I3C is acting as controller/target).
    bit_offset: 11
    bit_size: 1
  - name: CIBIF
    description: clear IBI request flag (when the I3C is acting as controller).
    bit_offset: 15
    bit_size: 1
  - name: CIBIENDF
    description: clear IBI end flag (when the I3C is acting as target).
    bit_offset: 16
    bit_size: 1
  - name: CCRF
    description: clear controller-role request flag (when the I3C is acting as controller).
    bit_offset: 17
    bit_size: 1
  - name: CCRUPDF
    description: clear controller-role update flag (when the I3C is acting as target).
    bit_offset: 18
    bit_size: 1
  - name: CHJF
    description: clear hot-join flag (when the I3C is acting as controller).
    bit_offset: 19
    bit_size: 1
  - name: CWKPF
    description: clear wakeup flag (when the I3C is acting as target).
    bit_offset: 21
    bit_size: 1
  - name: CGETF
    description: clear GETxxx CCC flag (when the I3C is acting as target).
    bit_offset: 22
    bit_size: 1
  - name: CSTAF
    description: clear GETSTATUS CCC flag (when the I3C is acting as target).
    bit_offset: 23
    bit_size: 1
  - name: CDAUPDF
    description: clear ENTDAA/RSTDAA/SETNEWDA CCC flag (when the I3C is acting as target).
    bit_offset: 24
    bit_size: 1
  - name: CMWLUPDF
    description: clear SETMWL CCC flag (when the I3C is acting as target).
    bit_offset: 25
    bit_size: 1
  - name: CMRLUPDF
    description: clear SETMRL CCC flag (when the I3C is acting as target).
    bit_offset: 26
    bit_size: 1
  - name: CRSTF
    description: clear reset pattern flag (when the I3C is acting as target).
    bit_offset: 27
    bit_size: 1
  - name: CASUPDF
    description: clear ENTASx CCC flag (when the I3C is acting as target).
    bit_offset: 28
    bit_size: 1
  - name: CINTUPDF
    description: clear ENEC/DISEC CCC flag (when the I3C is acting as target).
    bit_offset: 29
    bit_size: 1
  - name: CDEFF
    description: clear DEFTGTS CCC flag (when the I3C is acting as target).
    bit_offset: 30
    bit_size: 1
  - name: CGRPF
    description: clear DEFGRPA CCC flag (when the I3C is acting as target).
    bit_offset: 31
    bit_size: 1
fieldset/CFGR:
  description: I3C configuration register.
  fields:
  - name: EN
    description: I3C enable (whatever I3C is acting as controller/target) - Except registers, the peripheral is under reset (a.k.a. partial reset). - Before clearing EN, when I3C is acting as a controller, all the possible target requests must be disabled using DISEC CCC. - When I3C is acting as a target, software should not disable the I3C, unless a partial reset is needed. In this state, some register fields can not be modified (like CRINIT, HKSDAEN for the I3C_CFGR).
    bit_offset: 0
    bit_size: 1
  - name: CRINIT
    description: initial controller/target role This bit can be modified only when I3C_CFGR.EN = 0. Once enabled by setting I3C_CFGR.EN = 1, I3C peripheral initially acts as an I3C target. I3C does not drive SCL line and does not enable SDA pull-up, until it eventually acquires the controller role. Once enabled by setting I3C_CFGR.EN = 1, I3C peripheral initially acts as a controller. It has the I3C controller role, so drives SCL line and enables SDA pull-up, until it eventually offers the controller role to an I3C secondary controller.
    bit_offset: 1
    bit_size: 1
  - name: NOARBH
    description: no arbitrable header after a START (when I3C is acting as a controller) This bit can be modified only when there is no on-going frame. - The target address is emitted directly after a START in case of a legacy I2C message or an I3C SDR private read/write message. - This is a more performing option (when is useless the emission of the 0x7E arbitrable header), but this is to be used only when the controller is sure that the addressed target device can not emit concurrently an IBI or a controller-role request (to insure no misinterpretation and no potential conflict between the address emitted by the controller in open-drain mode and the same address a target device can emit after a START, for IBI or MR).
    bit_offset: 2
    bit_size: 1
  - name: RSTPTRN
    description: HDR reset pattern enable (when I3C is acting as a controller) This bit can be modified only when there is no on-going frame.
    bit_offset: 3
    bit_size: 1
  - name: EXITPTRN
    description: HDR Exit Pattern enable (when I3C is acting as a controller) This bit can be modified only when there is no on-going frame. This is used to send only the header to test ownership of the bus when there is a suspicion of problem after controller-role hand-off (new controller didn’t assert its controller-role by accessing the previous one in less than Activity State time). The HDR Exit Pattern is sent even if the message header {S/Sr + 0x7E addr + W } is ACKed.
    bit_offset: 4
    bit_size: 1
  - name: HKSDAEN
    description: High-keeper enable on SDA line (when I3C is acting as a controller) This bit can be modified only when I3C_CFGR.EN=0.
    bit_offset: 5
    bit_size: 1
  - name: HJACK
    description: Hot Join request acknowledge (when I3C is acting as a controller) After the NACK, the message continues as initially programmed (the hot-joining target is aware of the NACK and surely emits another hot-join request later on). After the ACK, the message continues as initially programmed. The software is aware by the HJ interrupt (flag I3C_EVR.HJF is set) and initiates the ENTDAA sequence later on, potentially preventing others Hot Join requests with a Disable target events command (DISEC, with DISHJ=1). Independently of the HJACK configuration, further Hot Join request(s) are NACKed until the Hot Join flag, HJF, is cleared. However, a NACKed target can be assigned a dynamic address by the ENTDAA sequence initiated later on by the first HJ request, preventing this target to emit an HJ request again.
    bit_offset: 7
    bit_size: 1
  - name: RXDMAEN
    description: RX-FIFO DMA request enable (whatever I3C is acting as controller/target) - Software reads and pops a data byte/word from RX-FIFO i.e. reads I3C_RDR or I3C_RDWR register. - A next data byte/word is to be read by the software either via polling on the flag I3C_EVR.RXFNEF=1 or via interrupt notification (enabled by I3C_IER.RXFNEIE=1). - DMA reads and pops data byte(s)/word(s) from RX-FIFO i.e. reads I3C_RDR or I3C_RDWR register. - A next data byte/word is automatically read by the programmed hardware (i.e. via the asserted RX-FIFO DMA request from the I3C and the programmed DMA channel).
    bit_offset: 8
    bit_size: 1
  - name: RXFLUSH
    description: RX-FIFO flush (whatever I3C is acting as controller/target) This bit can only be written.
    bit_offset: 9
    bit_size: 1
  - name: RXTHRES
    description: RX-FIFO threshold (whatever I3C is acting as controller/target) This threshold defines, compared to the RX-FIFO level, when the I3C_EVR.RXFNEF flag is set (and consequently if RXDMAEN=1 when is asserted a DMA RX request). RXFNEF is set when 1 byte is to be read in RX-FIFO (i.e. in I3C_RDR). RXFNEF is set when 4 bytes are to be read in RX-FIFO (i.e. in I3C_RDWR).
    bit_offset: 10
    bit_size: 1
  - name: TXDMAEN
    description: TX-FIFO DMA request enable (whatever I3C is acting as controller/target) - Software writes and pushes a data byte/word into TX-FIFO i.e. writes I3C_TDR or I3C_TDWR register, to be transmitted over the I3C bus. - A next data byte/word is to be written by the software either via polling on the flag I3C_EVR.TXFNFF=1 or via interrupt notification (enabled by I3C_IER.TXFNFIE=1). - DMA writes and pushes data byte(s)/word(s) into TX-FIFO i.e. writes I3C_TDR or I3C_TDWR register. - A next data byte/word transfer is automatically pushed by the programmed hardware (i.e. via the asserted TX-FIFO DMA request from the I3C and the programmed DMA channel).
    bit_offset: 12
    bit_size: 1
  - name: TXFLUSH
    description: TX-FIFO flush (whatever I3C is acting as controller/target) This bit can only be written. When the I3C is acting as target, this bit can be used to flush the TX-FIFO on a private read if the controller has early ended the read data (i.e. driven low the T bit) and there is/are remaining data in the TX-FIFO (i.e. I3C_SR.ABT=1 and I3C_SR.XDCNT[15:0] < I3C_TGTTDR.TGTTDCNT[15:0]).
    bit_offset: 13
    bit_size: 1
  - name: TXTHRES
    description: TX-FIFO threshold (whatever I3C is acting as controller/target) This threshold defines, compared to the TX-FIFO level, when the I3C_EVR.TXFNFF flag is set (and consequently if TXDMAEN=1 when is asserted a DMA TX request). TXFNFF is set when 1 byte is to be written in TX-FIFO (i.e. in I3C_TDR). TXFNFF is set when 4 bytes are to be written in TX-FIFO (i.e. in I3C_TDWR).
    bit_offset: 14
    bit_size: 1
  - name: SDMAEN
    description: 'S-FIFO DMA request enable (when I3C is acting as controller) Condition: When RMODE=1 (FIFO is enabled for the status): - Software reads and pops a status word from S-FIFO i.e. reads I3C_SR register after a completed frame (I3C_EVR.FCF=1) or an error (I3C_EVR.ERRF=1). - A status word can be read by the software either via polling on these register flags or via interrupt notification (enabled by I3C_IER.FCIE=1 and I3C_IER.ERRIE=1). - DMA reads and pops status word(s) from S-FIFO i.e. reads I3C_SR register. - Status word(s) are automatically read by the programmed hardware (i.e. via the asserted S-FIFO DMA request from the I3C and the programmed DMA channel).'
    bit_offset: 16
    bit_size: 1
  - name: SFLUSH
    description: S-FIFO flush (when I3C is acting as controller) When I3C is acting as I3C controller, this bit can only be written (and is only used when I3C is acting as controller).
    bit_offset: 17
    bit_size: 1
  - name: RMODE
    description: S-FIFO enable / status receive mode (when I3C is acting as controller) When I3C is acting as I3C controller, this bit is used for the enabling the FIFO for the status (S-FIFO) vs the received status from the target on the I3C bus. When I3C is acting as target, this bit must be cleared. - Status register (i.e. I3C_SR) is used without FIFO mechanism. - There is no SCL stretch if a new status register content is not read. - Status register must be read before being lost/overwritten. All message status must be read. There is SCL stretch when there is no more space in the S-FIFO.
    bit_offset: 18
    bit_size: 1
  - name: TMODE
    description: transmit mode (when I3C is acting as controller) When I3C is acting as I3C controller, this bit is used for the C-FIFO and TX-FIFO management vs the emitted frame on the I3C bus. A frame transfer starts as soon as first control word is present in C-FIFO.
    bit_offset: 19
    bit_size: 1
  - name: CDMAEN
    description: 'C-FIFO DMA request enable (when I3C is acting as controller) When I3C is acting as controller: - Software writes and pushes control word(s) into C-FIFO i.e. writes I3C_CR register, as needed for a given frame. - A next control word transfer can be written by software either via polling on the flag I3C_EVR.CFNFF=1 or via interrupt notification (enabled by I3C_IER.CFNFIE=1). - DMA writes and pushes control word(s) into C-FIFO i.e. writes I3C_CR register, as needed for a given frame. - A next control word transfer is automatically written by the programmed hardware (i.e. via the asserted C-FIFO DMA request from the I3C and the programmed DMA channel).'
    bit_offset: 20
    bit_size: 1
  - name: CFLUSH
    description: C-FIFO flush (when I3C is acting as controller) This bit can only be written.
    bit_offset: 21
    bit_size: 1
  - name: TSFSET
    description: 'frame transfer set (a.k.a. software trigger) (when I3C is acting as controller) This bit can only be written. When I3C is acting as I3C controller: Note: If this bit is not set, the other alternative for the software to initiate a frame transfer is to directly write the first control word register (i.e. I3C_CR) while C-FIFO is empty (i.e. I3C_EVR.CFEF=1). Then, if the first written control word is not tagged as a message end (i.e I3C_CR.MEND=0), it causes the hardware to assert the flag I3C_EVR.CFNFF (C-FIFO not full and a next control word is needed).'
    bit_offset: 30
    bit_size: 1
fieldset/CR:
  description: I3C message control register.
  fields:
  - name: DCNT
    description: count of data to transfer during a read or write message, in bytes (whatever I3C is acting as controller/target) Linear encoding up to 64 Kbytes -1 ...
    bit_offset: 0
    bit_size: 16
  - name: RNW
    description: read / non-write message (when I3C is acting as controller) When I3C is acting as controller, this field is used if MTYPE[3:0]=0010 (private message) or MTYPE[3:0]=0011 (direct message) or MTYPE[3:0]=0100 (legacy I2C message), in order to emit the RnW bit on the I3C bus.
    bit_offset: 16
    bit_size: 1
  - name: ADD
    description: 7-bit I3C dynamic / I2C static target address (when I3C is acting as controller) When I3C is acting as controller, this field is used if MTYPE[3:0]=0010 (private message) or MTYPE[3:0]=0011 (direct message) or MTYPE[3:0]=0100 (legacy I2C message).
    bit_offset: 17
    bit_size: 7
  - name: MTYPE
    description: 'message type (whatever I3C is acting as controller/target) Bits[26:0] are ignored. After M2 error detection on an I3C SDR message, this is needed for SCL “stuck at” recovery. Bits[26:0] are ignored. If I3C_CFGR.EXITPTRN=1, an HDR exit pattern is emitted on the bus to generate an escalation fault. Bits[23:17] (ADD[6:0]) is the emitted 7-bit dynamic address. Bit[16] (RNW) is the emitted RnW bit. The transferred private message is: {S / S+7’h7E+RnW=0+Sr / Sr+*} + 7-bit DynAddr + RnW + (8-bit Data + T)* + Sr/P. After a S (START), depending on I3C_CFGR.NOARBH, the arbitrable header (7’h7E+RnW=0) is inserted or not. Sr+*: after a Sr (Repeated Start), the hardware automatically inserts (7’h7E+RnW=0) if needed, i.e. if it follows an I3C direct message without ending by a P (Stop). Bits[23:17] (ADD[6:0]) is the emitted 7-bit dynamic address. Bit[16] (RNW) is the emitted RnW bit. The transferred direct message is: Sr + 7-bit DynAddr + RnW + (8-bit Data + T)* + Sr/P Bits[23:17] (ADD[6:0]) is the emitted 7-bit static address. Bit[16] (RNW) is the emitted RnW bit. The transferred legacy I2C message is: {S / S+ 7’h7E+RnW=0 + Sr / Sr+*} + 7-bit StaAddr + RnW + (8-bit Data + T)* + Sr/P. After a S (START), depending on I3C_CFGR.NOARBH, the arbitrable header (7’h7E+RnW=0) is inserted or not. Sr+*: after a Sr (Repeated Start), the hardware automatically inserts (7’h7E+RnW=0) if needed, i.e. if it follows an I3C direct message without ending by a P (Stop). 1xxx: reserved (when I3C is acting as I3C controller, used when target) 0xxx: reserved {S +} 7’h02 addr + RnW=0 {S +} 7-bit I3C_DEVR0.DA[6:0] + RnW=0 after a bus available condition (the target first emits a START request), or once the controller drives a START. {S +} 7-bit I3C_DEVR0.DA[6:0] + RnW=1 (+Ack/Nack from controller) When acknowledged from controller, the next (optional, depending on I3C_BCR.BCR2) transmitted IBI payload data is defined by I3C_CR.DCNT[15:0] and must be consistently programmed vs the maximum IBI payload data size which is defined by I3C_IBIDR.IBIP[2:0]. Others: reserved.'
    bit_offset: 27
    bit_size: 4
  - name: MEND
    description: message end type (when the I3C is acting as controller).
    bit_offset: 31
    bit_size: 1
fieldset/CRCAPR:
  description: I3C controller-role capability register.
  fields:
  - name: CAPDHOFF
    description: delayed controller-role hand-off This bit is written by software during bus initialization (i.e. I3C_CFGR.EN=0) and indicates if this target I3C may need additional time to process a controller-role hand-off requested by the current controller. This bit is used to return the CRCAP2 byte in response to the GETCAPS CCC format 2.
    bit_offset: 3
    bit_size: 1
  - name: CAPGRP
    description: group management support (when acting as controller) This bit is written by software during bus initialization (i.e. I3C_CFGR.EN=0) and indicates if the I3C is able to support group management when it acts as a controller (after controller-role hand-off) via emitted DEFGRPA, RSTGRPA, and SETGRPA CCC. This bit is used to return the CRCAP1 byte in response to the GETCAPS CCC format 2.
    bit_offset: 9
    bit_size: 1
fieldset/CR_ALTERNATE:
  description: I3C message control register alternate.
  fields:
  - name: DCNT
    description: count of data to transfer during a read or write message, in bytes (when I3C is acting as controller) Linear encoding up to 64 Kbytes -1. ...
    bit_offset: 0
    bit_size: 16
  - name: CCC
    description: 8-bit CCC code (when I3C is acting as controller) If Bit[23]=CCC[7]=1, this is the 1st part of an I3C SDR direct CCC command. If Bit[23]=CCC[7]=0, this is an I3C SDR broadcast CCC command (including ENTDAA and ENTHDR0).
    bit_offset: 16
    bit_size: 8
  - name: MTYPE
    description: 'message type (when I3C is acting as controller) Bits[23:16] (CCC[7:0]) is the emitted 8-bit CCC code If Bit[23]=CCC[7]=1: this is the 1st part of an I3C SDR direct CCC command The transferred direct CCC command message is: {S / S+7’h7E +RnW=0 / Sr+*} + (direct CCC + T) + (8-bit Data + T)* + Sr After a S (START), depending on I3C_CFGR.NOARBH, the arbitrable header (7’h7E+RnW=0) is inserted or not. Sr+*: after a Sr (Repeated Start), the hardware automatically inserts (7’h7E+R/W). If Bit[23]=CCC[7]=0: this is an I3C SDR broadcast CCC command (including ENTDAA and ENTHDR0) The transferred broadcast CCC command message is: {S / S+7’h7E +RnW=0 / Sr+*} + (broadcast CCC + T) + (8-bit Data + T)* + Sr/P After a S (START), depending on I3C_CFGR.NOARBH, the arbitrable header (7’h7E+RnW=0) is inserted or not. Sr+*: after a Sr (Repeated Start), the hardware automatically inserts (7’h7E+R/W). others: reserved.'
    bit_offset: 27
    bit_size: 4
  - name: MEND
    description: message end type (when I3C is acting as controller).
    bit_offset: 31
    bit_size: 1
fieldset/DCR:
  description: I3C device characteristics register.
  fields:
  - name: DCR
    description: 'device characteristics ID others: ID to describe the type of the I3C sensor/device Note: The latest MIPI DCR ID assignments are available at: https://www.mipi.org/MIPI_I3C_device_characteristics_register.'
    bit_offset: 0
    bit_size: 8
fieldset/DEVR0:
  description: I3C own device characteristics register.
  fields:
  - name: DAVAL
    description: dynamic address is valid (when the I3C is acting as target) When the I3C is acting as controller, this field can be written by software, for validating its own dynamic address, for example before a controller-role hand-off. When the I3C is acting as target, this field is asserted by hardware on the acknowledge of the broadcast ENTDAA CCC or the direct SETNEWDA CCC, and this field is cleared by hardware on the acknowledge of the broadcast RSTDAA CCC.
    bit_offset: 0
    bit_size: 1
  - name: DA
    description: 7-bit dynamic address When the I3C is acting as controller, this field can be written by software, for defining its own dynamic address. When the I3C is acting as target, this field is updated by hardware on the reception of either the broadcast ENTDAA CCC or the direct SETNEWDA CCC.
    bit_offset: 1
    bit_size: 7
  - name: IBIEN
    description: IBI request enable (when the I3C is acting as target) This field is initially written by software when I3C_CFGR.EN=0, and is updated by hardware on the reception of DISEC CCC with DISINT=1 (i.e. cleared) and the reception of ENEC CCC with ENINT=1 (i.e. set).
    bit_offset: 16
    bit_size: 1
  - name: CREN
    description: controller-role request enable (when the I3C is acting as target) This field is initially written by software when I3C_CFGR.EN=0, and is updated by hardware on the reception of DISEC CCC with DISCR=1 (i.e. cleared) and the reception of ENEC CCC with ENCR=1 (i.e. set).
    bit_offset: 17
    bit_size: 1
  - name: HJEN
    description: hot-join request enable (when the I3C is acting as target) This field is initially written by software when I3C_CFGR.EN=0, and is updated by hardware on the reception of DISEC CCC with DISHJ=1 (i.e. cleared) and the reception of ENEC CCC with ENHJ=1 (i.e. set).
    bit_offset: 19
    bit_size: 1
  - name: AS
    description: activity state (when the I3C is acting as target) This read field is updated by hardware on the reception of a ENTASx CCC (enter activity state, with x=0-3):.
    bit_offset: 20
    bit_size: 2
  - name: RSTACT
    description: 'reset action/level on received reset pattern (when the I3C is acting as target) This read field is used by hardware on the reception of a direct read RSTACT CCC in order to return the corresponding data byte on the I3C bus. This read field is updated by hardware on the reception of a broadcast or direct write RSTACT CCC (target reset action). Only the defining bytes 0x00, 0x01 and 0x02 are mapped, and RSTACT[1:0] = Defining Byte[1:0]. a) partially reset the I3C peripheral, by a write and clear of the enable bit of the i3C configuration register (i.e. write I3C_CFGR.EN=0). This reset the I3C bus interface and the I3C kernel sub-parts, without modifying the content of the I3C APB registers (excepted the I3C_CFGR.EN bit). b) reset fully the I3C peripheral including all its registers via a write and set to the I3C reset control bit of the RCC (Reset and Clock Controller) register. a system reset. This has the same impact as a pin reset (i.e. NRST=0) (refer to RCC functional description - Reset part): – the software writes and set the AICR.SYSRESETREQ register control bit, when the device is controlled by a CortexTM-M. – the software writes and set the RCC_GRSTCSETR.SYSRST=1, when the device is controlled by a CortexTM-A.'
    bit_offset: 22
    bit_size: 2
  - name: RSTVAL
    description: 'reset action is valid (when the I3C is acting as target) This read bit is asserted by hardware to indicate that the RTSACT[1:0] field has been updated on the reception of a broadcast or direct write RSTACT CCC (target reset action) and is valid. This field is cleared by hardware when the target receives a frame start. If RSTVAL=1: when the RSTF is asserted (and/or the corresponding interrupt if enabled), I3C_DEVR0.RSTACT[1:0] dictates the reset action to be performed by the software if any. If RSTVAL=0: when the RSTF is asserted (and/or the corresponding interrupt if enabled), the software should issue an I3C reset after a first detected reset pattern, and a system reset on the second one.'
    bit_offset: 24
    bit_size: 1
fieldset/DEVR1:
  description: I3C device 1 characteristics register.
  fields:
  - name: DA
    description: assigned I3C dynamic address to target x (when the I3C is acting as controller) When the I3C is acting as controller, this field should be written by software to store the 7-bit dynamic address that the controller sends via a broadcast ENTDAA or a direct SETNEWDA CCC which has been acknowledged by the target x. Writing to this field has no impact when the read field I3C_DEVRx.DIS=1.
    bit_offset: 1
    bit_size: 7
  - name: IBIACK
    description: 'IBI request acknowledge (when the I3C is acting as controller) When the I3C is acting as controller, this bit is written by software to define the acknowledge policy to be applied on the I3C bus on the reception of a IBI request from target x: - After the NACK, the message continues as initially programmed (the target is aware of the NACK and can emit another IBI request later on) - The field DIS is asserted by hardware to protect DA[6:0] from being modified by software meanwhile the hardware can store internally the current DA[6:0] into the kernel clock domain. - After the ACK, the controller logs the IBI payload data, if any, depending on I3C_DEVRx.IBIDEN. - The software is notified by the IBI flag (i.e. I3C_EVR.IBIF=1) and/or the corresponding interrupt if enabled; - Independently from IBIACK configuration for this or other devices, further IBI request(s) are NACKed until IBI request flag (i.e. I3C_EVR.IBIF) and controller-role request flag (i.e. I3C_EVR.CRF) are both cleared.'
    bit_offset: 16
    bit_size: 1
  - name: CRACK
    description: 'controller-role request acknowledge (when the I3C is acting as controller) When the I3C is acting as controller, this bit is written by software to define the acknowledge policy to be applied on the I3C bus on the reception of a controller-role request from target x: After the NACK, the message continues as initially programmed (the target is aware of the NACK and can emit another controller-role request later on) - The field DIS is asserted by hardware to protect DA[6:0] from being modified by software meanwhile the hardware can store internally the current DA[6:0] into the kernel clock domain. - After the ACK, the message continues as initially programmed. The software is notified by the controller-role request flag (i.e. I3C_EVR.CRF=1) and/or the corresponding interrupt if enabled; For effectively granting the controller-role to the requesting secondary controller, software should issue a GETACCCR (formerly known as GETACCMST), followed by a STOP. - Independently of CRACK configuration for this or other devices, further controller-role request(s) are NACKed until controller-role request flag (i.e. I3C_EVR.CRF) and IBI flag (i.e. I3C_EVR.IBIF) are both cleared.'
    bit_offset: 17
    bit_size: 1
  - name: IBIDEN
    description: IBI data enable (when the I3C is acting as controller) When the I3C is acting as controller, this bit should be written by software to store the BCR[2] bit as received from the target x during broadcast ENTDAA or direct GETBCR CCC via the received I3C_RDR. Writing to this field has no impact when the read field I3C_DEVRx.DIS=1.
    bit_offset: 18
    bit_size: 1
  - name: SUSP
    description: suspend/stop I3C transfer on received IBI (when the I3C is acting as controller) When the I3C is acting as controller, this bit is used to receive an IBI from target x with pending read notification feature (i.e. with received MDB[7:5]=3’b101). If this bit is set, when an IBI is received (i.e. I3C_EVR.IBIF=1), a Stop is emitted on the I3C bus and the C-FIFO is automatically flushed by hardware; to avoid a next private read communication issue if a previous private read message to the target x was stored in the C-FIFO.
    bit_offset: 19
    bit_size: 1
  - name: DIS
    description: DA[6:0] write disabled (when the I3C is acting as controller) When the I3C is acting as controller, once that software set IBIACK=1 or CRACK=1, this read bit is set by hardware (i.e. DIS=1) to lock the configured DA[6:0] and IBIDEN values. Then, to be able to next modify DA[6:0] or IBIDEN, the software must wait for this field DIS to be de-asserted by hardware (i.e. polling on DIS=0) before modifying these two assigned values to the target x. Indeed, the target may be requesting an IBI or a controller-role meanwhile the controller intends to modify DA[6:0] or IBIDEN.
    bit_offset: 31
    bit_size: 1
fieldset/DEVR2:
  description: I3C device 2 characteristics register.
  fields:
  - name: DA
    description: assigned I3C dynamic address to target x (when the I3C is acting as controller) When the I3C is acting as controller, this field should be written by software to store the 7-bit dynamic address that the controller sends via a broadcast ENTDAA or a direct SETNEWDA CCC which has been acknowledged by the target x. Writing to this field has no impact when the read field I3C_DEVRx.DIS=1.
    bit_offset: 1
    bit_size: 7
  - name: IBIACK
    description: 'IBI request acknowledge (when the I3C is acting as controller) When the I3C is acting as controller, this bit is written by software to define the acknowledge policy to be applied on the I3C bus on the reception of a IBI request from target x: - After the NACK, the message continues as initially programmed (the target is aware of the NACK and can emit another IBI request later on) - The field DIS is asserted by hardware to protect DA[6:0] from being modified by software meanwhile the hardware can store internally the current DA[6:0] into the kernel clock domain. - After the ACK, the controller logs the IBI payload data, if any, depending on I3C_DEVRx.IBIDEN. - The software is notified by the IBI flag (i.e. I3C_EVR.IBIF=1) and/or the corresponding interrupt if enabled; - Independently from IBIACK configuration for this or other devices, further IBI request(s) are NACKed until IBI request flag (i.e. I3C_EVR.IBIF) and controller-role request flag (i.e. I3C_EVR.CRF) are both cleared.'
    bit_offset: 16
    bit_size: 1
  - name: CRACK
    description: 'controller-role request acknowledge (when the I3C is acting as controller) When the I3C is acting as controller, this bit is written by software to define the acknowledge policy to be applied on the I3C bus on the reception of a controller-role request from target x: After the NACK, the message continues as initially programmed (the target is aware of the NACK and can emit another controller-role request later on) - The field DIS is asserted by hardware to protect DA[6:0] from being modified by software meanwhile the hardware can store internally the current DA[6:0] into the kernel clock domain. - After the ACK, the message continues as initially programmed. The software is notified by the controller-role request flag (i.e. I3C_EVR.CRF=1) and/or the corresponding interrupt if enabled; For effectively granting the controller-role to the requesting secondary controller, software should issue a GETACCCR (formerly known as GETACCMST), followed by a STOP. - Independently of CRACK configuration for this or other devices, further controller-role request(s) are NACKed until controller-role request flag (i.e. I3C_EVR.CRF) and IBI flag (i.e. I3C_EVR.IBIF) are both cleared.'
    bit_offset: 17
    bit_size: 1
  - name: IBIDEN
    description: IBI data enable (when the I3C is acting as controller) When the I3C is acting as controller, this bit should be written by software to store the BCR[2] bit as received from the target x during broadcast ENTDAA or direct GETBCR CCC via the received I3C_RDR. Writing to this field has no impact when the read field I3C_DEVRx.DIS=1.
    bit_offset: 18
    bit_size: 1
  - name: SUSP
    description: suspend/stop I3C transfer on received IBI (when the I3C is acting as controller) When the I3C is acting as controller, this bit is used to receive an IBI from target x with pending read notification feature (i.e. with received MDB[7:5]=3’b101). If this bit is set, when an IBI is received (i.e. I3C_EVR.IBIF=1), a Stop is emitted on the I3C bus and the C-FIFO is automatically flushed by hardware; to avoid a next private read communication issue if a previous private read message to the target x was stored in the C-FIFO.
    bit_offset: 19
    bit_size: 1
  - name: DIS
    description: DA[6:0] write disabled (when the I3C is acting as controller) When the I3C is acting as controller, once that software set IBIACK=1 or CRACK=1, this read bit is set by hardware (i.e. DIS=1) to lock the configured DA[6:0] and IBIDEN values. Then, to be able to next modify DA[6:0] or IBIDEN, the software must wait for this field DIS to be de-asserted by hardware (i.e. polling on DIS=0) before modifying these two assigned values to the target x. Indeed, the target may be requesting an IBI or a controller-role meanwhile the controller intends to modify DA[6:0] or IBIDEN.
    bit_offset: 31
    bit_size: 1
fieldset/DEVR3:
  description: I3C device 3 characteristics register.
  fields:
  - name: DA
    description: assigned I3C dynamic address to target x (when the I3C is acting as controller) When the I3C is acting as controller, this field should be written by software to store the 7-bit dynamic address that the controller sends via a broadcast ENTDAA or a direct SETNEWDA CCC which has been acknowledged by the target x. Writing to this field has no impact when the read field I3C_DEVRx.DIS=1.
    bit_offset: 1
    bit_size: 7
  - name: IBIACK
    description: 'IBI request acknowledge (when the I3C is acting as controller) When the I3C is acting as controller, this bit is written by software to define the acknowledge policy to be applied on the I3C bus on the reception of a IBI request from target x: - After the NACK, the message continues as initially programmed (the target is aware of the NACK and can emit another IBI request later on) - The field DIS is asserted by hardware to protect DA[6:0] from being modified by software meanwhile the hardware can store internally the current DA[6:0] into the kernel clock domain. - After the ACK, the controller logs the IBI payload data, if any, depending on I3C_DEVRx.IBIDEN. - The software is notified by the IBI flag (i.e. I3C_EVR.IBIF=1) and/or the corresponding interrupt if enabled; - Independently from IBIACK configuration for this or other devices, further IBI request(s) are NACKed until IBI request flag (i.e. I3C_EVR.IBIF) and controller-role request flag (i.e. I3C_EVR.CRF) are both cleared.'
    bit_offset: 16
    bit_size: 1
  - name: CRACK
    description: 'controller-role request acknowledge (when the I3C is acting as controller) When the I3C is acting as controller, this bit is written by software to define the acknowledge policy to be applied on the I3C bus on the reception of a controller-role request from target x: After the NACK, the message continues as initially programmed (the target is aware of the NACK and can emit another controller-role request later on) - The field DIS is asserted by hardware to protect DA[6:0] from being modified by software meanwhile the hardware can store internally the current DA[6:0] into the kernel clock domain. - After the ACK, the message continues as initially programmed. The software is notified by the controller-role request flag (i.e. I3C_EVR.CRF=1) and/or the corresponding interrupt if enabled; For effectively granting the controller-role to the requesting secondary controller, software should issue a GETACCCR (formerly known as GETACCMST), followed by a STOP. - Independently of CRACK configuration for this or other devices, further controller-role request(s) are NACKed until controller-role request flag (i.e. I3C_EVR.CRF) and IBI flag (i.e. I3C_EVR.IBIF) are both cleared.'
    bit_offset: 17
    bit_size: 1
  - name: IBIDEN
    description: IBI data enable (when the I3C is acting as controller) When the I3C is acting as controller, this bit should be written by software to store the BCR[2] bit as received from the target x during broadcast ENTDAA or direct GETBCR CCC via the received I3C_RDR. Writing to this field has no impact when the read field I3C_DEVRx.DIS=1.
    bit_offset: 18
    bit_size: 1
  - name: SUSP
    description: suspend/stop I3C transfer on received IBI (when the I3C is acting as controller) When the I3C is acting as controller, this bit is used to receive an IBI from target x with pending read notification feature (i.e. with received MDB[7:5]=3’b101). If this bit is set, when an IBI is received (i.e. I3C_EVR.IBIF=1), a Stop is emitted on the I3C bus and the C-FIFO is automatically flushed by hardware; to avoid a next private read communication issue if a previous private read message to the target x was stored in the C-FIFO.
    bit_offset: 19
    bit_size: 1
  - name: DIS
    description: DA[6:0] write disabled (when the I3C is acting as controller) When the I3C is acting as controller, once that software set IBIACK=1 or CRACK=1, this read bit is set by hardware (i.e. DIS=1) to lock the configured DA[6:0] and IBIDEN values. Then, to be able to next modify DA[6:0] or IBIDEN, the software must wait for this field DIS to be de-asserted by hardware (i.e. polling on DIS=0) before modifying these two assigned values to the target x. Indeed, the target may be requesting an IBI or a controller-role meanwhile the controller intends to modify DA[6:0] or IBIDEN.
    bit_offset: 31
    bit_size: 1
fieldset/DEVR4:
  description: I3C device 4 characteristics register.
  fields:
  - name: DA
    description: assigned I3C dynamic address to target x (when the I3C is acting as controller) When the I3C is acting as controller, this field should be written by software to store the 7-bit dynamic address that the controller sends via a broadcast ENTDAA or a direct SETNEWDA CCC which has been acknowledged by the target x. Writing to this field has no impact when the read field I3C_DEVRx.DIS=1.
    bit_offset: 1
    bit_size: 7
  - name: IBIACK
    description: 'IBI request acknowledge (when the I3C is acting as controller) When the I3C is acting as controller, this bit is written by software to define the acknowledge policy to be applied on the I3C bus on the reception of a IBI request from target x: - After the NACK, the message continues as initially programmed (the target is aware of the NACK and can emit another IBI request later on) - The field DIS is asserted by hardware to protect DA[6:0] from being modified by software meanwhile the hardware can store internally the current DA[6:0] into the kernel clock domain. - After the ACK, the controller logs the IBI payload data, if any, depending on I3C_DEVRx.IBIDEN. - The software is notified by the IBI flag (i.e. I3C_EVR.IBIF=1) and/or the corresponding interrupt if enabled; - Independently from IBIACK configuration for this or other devices, further IBI request(s) are NACKed until IBI request flag (i.e. I3C_EVR.IBIF) and controller-role request flag (i.e. I3C_EVR.CRF) are both cleared.'
    bit_offset: 16
    bit_size: 1
  - name: CRACK
    description: 'controller-role request acknowledge (when the I3C is acting as controller) When the I3C is acting as controller, this bit is written by software to define the acknowledge policy to be applied on the I3C bus on the reception of a controller-role request from target x: After the NACK, the message continues as initially programmed (the target is aware of the NACK and can emit another controller-role request later on) - The field DIS is asserted by hardware to protect DA[6:0] from being modified by software meanwhile the hardware can store internally the current DA[6:0] into the kernel clock domain. - After the ACK, the message continues as initially programmed. The software is notified by the controller-role request flag (i.e. I3C_EVR.CRF=1) and/or the corresponding interrupt if enabled; For effectively granting the controller-role to the requesting secondary controller, software should issue a GETACCCR (formerly known as GETACCMST), followed by a STOP. - Independently of CRACK configuration for this or other devices, further controller-role request(s) are NACKed until controller-role request flag (i.e. I3C_EVR.CRF) and IBI flag (i.e. I3C_EVR.IBIF) are both cleared.'
    bit_offset: 17
    bit_size: 1
  - name: IBIDEN
    description: IBI data enable (when the I3C is acting as controller) When the I3C is acting as controller, this bit should be written by software to store the BCR[2] bit as received from the target x during broadcast ENTDAA or direct GETBCR CCC via the received I3C_RDR. Writing to this field has no impact when the read field I3C_DEVRx.DIS=1.
    bit_offset: 18
    bit_size: 1
  - name: SUSP
    description: suspend/stop I3C transfer on received IBI (when the I3C is acting as controller) When the I3C is acting as controller, this bit is used to receive an IBI from target x with pending read notification feature (i.e. with received MDB[7:5]=3’b101). If this bit is set, when an IBI is received (i.e. I3C_EVR.IBIF=1), a Stop is emitted on the I3C bus and the C-FIFO is automatically flushed by hardware; to avoid a next private read communication issue if a previous private read message to the target x was stored in the C-FIFO.
    bit_offset: 19
    bit_size: 1
  - name: DIS
    description: DA[6:0] write disabled (when the I3C is acting as controller) When the I3C is acting as controller, once that software set IBIACK=1 or CRACK=1, this read bit is set by hardware (i.e. DIS=1) to lock the configured DA[6:0] and IBIDEN values. Then, to be able to next modify DA[6:0] or IBIDEN, the software must wait for this field DIS to be de-asserted by hardware (i.e. polling on DIS=0) before modifying these two assigned values to the target x. Indeed, the target may be requesting an IBI or a controller-role meanwhile the controller intends to modify DA[6:0] or IBIDEN.
    bit_offset: 31
    bit_size: 1
fieldset/DR:
  description: I3C transmit data byte register.
  fields:
  - name: DB
    description: 8-bit data to transmit on I3C bus.
    bit_offset: 0
    bit_size: 8
fieldset/DWR:
  description: I3C receive data word register.
  fields:
  - name: DB
    description: 8-bit received data (earliest byte on I3C bus).
    bit_offset: 0
    bit_size: 8
    array:
      len: 4
      stride: 8
fieldset/EPIDR:
  description: I3C extended provisioned ID register.
  fields:
  - name: MIPIID
    description: '4-bit MIPI Instance ID This field is written by software to set and identify individually each instance of this I3C IP with a specific number on a single I3C bus. This field represents the bits[15:12] of the 48-bit provisioned ID. Note: The bits[11:0] of the provisioned ID may be 0.'
    bit_offset: 12
    bit_size: 4
  - name: IDTSEL
    description: 'provisioned ID type selector This field is set as 0 i.e. vendor fixed value. This field represents the bit[32] of the 48-bit provisioned ID. Note: The bits[31:16] of the provisioned ID may be 0.'
    bit_offset: 16
    bit_size: 1
  - name: MIPIMID
    description: 15-bit MIPI manufacturer ID This read field is the 15-bit STMicroelectronics MIPI ID i.e. 0x0104. This field represents the bits[47:33] of the 48-bit provisioned ID.
    bit_offset: 17
    bit_size: 15
fieldset/EVR:
  description: I3C event register.
  fields:
  - name: CFEF
    description: 'C-FIFO empty flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that the C-FIFO is empty when controller, and that the I3C_CR register contains no control word (i.e. none IBI/CR/HJ request) when target. This flag is de-asserted by hardware to indicate that the C-FIFO is not empty when controller, and that the I3C_CR register contains one control word (i.e. a pending IBI/CR/HJ request) when target. Note: When the I3C is acting as controller, if the C-FIFO and TX-FIFO preload is configured (i.e. I3C_CFGR.TMODE=1), the software must wait for TXFEF=1 and CFEF=1 before starting a new frame transfer.'
    bit_offset: 0
    bit_size: 1
  - name: TXFEF
    description: 'TX-FIFO empty flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that the TX-FIFO is empty. This flag is de-asserted by hardware to indicate that the TX-FIFO is not empty. Note: When the I3C is acting as controller, if the C-FIFO and TX-FIFO preload is configured (i.e. I3C_CFGR.TMODE=1), the software must wait for TXFEF=1 and CFEF=1 before starting a new frame transfer.'
    bit_offset: 1
    bit_size: 1
  - name: CFNFF
    description: 'C-FIFO not full flag (when the I3C is acting as controller) When the I3C is acting as controller, this flag is asserted by hardware to indicate that a control word is to be written to the C-FIFO. This flag is de-asserted by hardware to indicate that a control word is not to be written to the C-FIFO. Note: The software must wait for CFNFF=1 (by polling or via the enabled interrupt) before writing to C-FIFO (i.e. writing to I3C_CR).'
    bit_offset: 2
    bit_size: 1
  - name: SFNEF
    description: S-FIFO not empty flag (when the I3C is acting as controller) When the I3C is acting as controller, if the S-FIFO is enabled (i.e. I3C_CFGR.RMODE=1), this flag is asserted by hardware to indicate that a status word is to be read from the S-FIFO. This flag is de-asserted by hardware to indicate that a status word is not to be read from the S-FIFO.
    bit_offset: 3
    bit_size: 1
  - name: TXFNFF
    description: 'TX-FIFO not full flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that a data byte/word is to be written to the TX-FIFO. This flag is de-asserted by hardware to indicate that a data byte/word is not to be written to the TX-FIFO. Note: The software must wait for TXFNFF=1 (by polling or via the enabled interrupt) before writing to TX-FIFO (i.e. writing to I3C_TDR or I3C_TDWR depending on I3C_CFGR.TXTHRES). Note: When the I3C is acting as target, if the software intends to use the TXFNFF flag for writing into I3C_TDR/I3C_TDWR, it must have configured and set the TX-FIFO preload (i.e. write I3C_TGTTDR.PRELOAD).'
    bit_offset: 4
    bit_size: 1
  - name: RXFNEF
    description: 'RX-FIFO not empty flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that a data byte is to be read from the RX-FIFO. This flag is de-asserted by hardware to indicate that a data byte is not to be read from the RX-FIFO. Note: The software must wait for RXFNEF=1 (by polling or via the enabled interrupt) before reading from RX-FIFO (i.e. writing to I3C_RDR or I3C_RDWR depending on I3C_CFGR.RXTHRES).'
    bit_offset: 5
    bit_size: 1
  - name: TXLASTF
    description: last written data byte/word flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that the last data byte/word (depending on I3C_CFGR.TXTHRES) of a message is to be written to the TX-FIFO. This flag is de-asserted by hardware when the last data byte/word of a message is written.
    bit_offset: 6
    bit_size: 1
  - name: RXLASTF
    description: last read data byte/word flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that the last data byte/word (depending on I3C_CFGR.RXTHRES) of a message is to be read from the RX-FIFO. This flag is de-asserted by hardware when the last data byte/word of a message is read.
    bit_offset: 7
    bit_size: 1
  - name: FCF
    description: frame complete flag (whatever the I3C is acting as controller/target) When the I3C is acting as controller, this flag is asserted by hardware to indicate that a frame has been (normally) completed on the I3C bus, i.e when a stop is issued. When the I3C is acting as target, this flag is asserted by hardware to indicate that a message addressed to/by this target has been (normally) completed on the I3C bus, i.e when a next stop or repeated start is then issued by the controller. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CFCF bit.
    bit_offset: 9
    bit_size: 1
  - name: RXTGTENDF
    description: target-initiated read end flag (when the I3C is acting as controller) When the I3C is acting as controller, this flag is asserted by hardware to indicate that the target has prematurely ended a read transfer. Then, software should read I3C_SR to get more information on the prematurely read transfer. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CRXTGTENDF bit.
    bit_offset: 10
    bit_size: 1
  - name: ERRF
    description: flag (whatever the I3C is acting as controller/target) This flag is asserted by hardware to indicate that an error occurred.Then, software should read I3C_SER to get the error type. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CERRF bit.
    bit_offset: 11
    bit_size: 1
  - name: IBIF
    description: IBI flag (when the I3C is acting as controller) When the I3C is acting as controller, this flag is asserted by hardware to indicate that an IBI request has been received. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CIBIF bit.
    bit_offset: 15
    bit_size: 1
  - name: IBIENDF
    description: IBI end flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a IBI transfer has been received and completed (IBI acknowledged and IBI data bytes read by controller if any). This flag is cleared when software writes 1 into corresponding I3C_CEVR.CIBIENDF bit.
    bit_offset: 16
    bit_size: 1
  - name: CRF
    description: controller-role request flag (when the I3C is acting as controller) When the I3C is acting as controller, this flag is asserted by hardware to indicate that a controller-role request has been acknowledged and completed (by hardware). The software should then issue a GETACCCR CCC (get accept controller role) for the controller-role hand-off procedure. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CCRF bit.
    bit_offset: 17
    bit_size: 1
  - name: CRUPDF
    description: controller-role update flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that it has now gained the controller role after the completed controller-role hand-off procedure. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CCRUPDF bit.
    bit_offset: 18
    bit_size: 1
  - name: HJF
    description: hot-join flag (when the I3C is acting as controller) When the I3C is acting as controller, this flag is asserted by hardware to indicate that an hot join request has been received. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CHJF bit.
    bit_offset: 19
    bit_size: 1
  - name: WKPF
    description: wakeup/missed start flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a start has been detected (i.e. a SDA falling edge followed by a SCL falling edge) but on the next SCL falling edge, the I3C kernel clock is (still) gated. Thus an I3C bus transaction may have been lost by the target. The corresponding interrupt may be used to wakeup the device from a low power mode (Sleep or Stop mode). This flag is cleared when software writes 1 into corresponding I3C_CEVR.CWKPF bit.
    bit_offset: 21
    bit_size: 1
  - name: GETF
    description: get flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that any direct CCC of get type (GET*** CCC) has been received. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CGETF bit.
    bit_offset: 22
    bit_size: 1
  - name: STAF
    description: get status flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a direct GETSTATUS CCC (get status) has been received. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CSTAF bit.
    bit_offset: 23
    bit_size: 1
  - name: DAUPDF
    description: dynamic address update flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a dynamic address update has been received via any of the broadcast ENTDAA, RSTDAA and direct SETNEWDA CCC. Then, software should read I3C_DEVR0.DA[6:0] to get the maximum write length value. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CDAUPDF bit.
    bit_offset: 24
    bit_size: 1
  - name: MWLUPDF
    description: maximum write length update flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a direct SETMWL CCC (set max write length) has been received. Then, software should read I3C_MAXWLR.MWL[15:0] to get the maximum write length value. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CMWLUPDF bit.
    bit_offset: 25
    bit_size: 1
  - name: MRLUPDF
    description: maximum read length update flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a direct SETMRL CCC (set max read length) has been received. Then, software should read I3C_MAXRLR.MRL[15:0] to get the maximum read length value. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CMRLUPDF bit.
    bit_offset: 26
    bit_size: 1
  - name: RSTF
    description: 'reset pattern flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that a reset pattern has been detected (i.e. 14 SDA transitions while SCL is low, followed by repeated start, then stop). Then, software should read I3C_DEVR0.RSTACT[1:0] and I3C_DEVR0.RSTVAL, to know what reset level is required. If RSTVAL=1: when the RSTF is asserted (and/or the corresponding interrupt if enabled), I3C_DEVR0.RSTACT[1:0] dictates the reset action to be performed by the software if any. If RSTVAL=0: when the RSTF is asserted (and/or the corresponding interrupt if enabled), the software should issue an I3C reset after a first detected reset pattern, and a system reset on the second one. The corresponding interrupt may be used to wakeup the device from a low power mode (Sleep or Stop mode). This flag is cleared when software writes 1 into corresponding I3C_CEVR.CRSTF bit.'
    bit_offset: 27
    bit_size: 1
  - name: ASUPDF
    description: activity state update flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that the direct or broadcast ENTASx CCC (with x=0...3) has been received. Then, software should read I3C_DEVR0.AS[1:0]. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CASUPDF bit.
    bit_offset: 28
    bit_size: 1
  - name: INTUPDF
    description: interrupt/controller-role/hot-join update flag (when the I3C is acting as target) When the I3C is acting as target, this flag is asserted by hardware to indicate that the direct or broadcast ENEC/DISEC CCC (enable/disable target events) has been received, where a target event is either an interrupt/IBI request, a controller-role request, or an hot-join request. Then, software should read respectively I3C_DEVR0.IBIEN, I3C_DEVR0.CREN or I3C_DEVR0.HJEN. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CINTUPDF bit.
    bit_offset: 29
    bit_size: 1
  - name: DEFF
    description: DEFTGTS flag (when the I3C is acting as target) When the I3C is acting as target (and is typically controller capable), this flag is asserted by hardware to indicate that the broadcast DEFTGTS CCC (define list of targets) has been received. Then, software may store the received data for when getting the controller role. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CDEFF bit.
    bit_offset: 30
    bit_size: 1
  - name: GRPF
    description: group addressing flag (when the I3C is acting as target) When the I3C is acting as target (and is typically controller capable), this flag is asserted by hardware to indicate that the broadcast DEFGRPA CCC (define list of group addresses) has been received. Then, software may store the received data for when getting the controller role. This flag is cleared when software writes 1 into corresponding I3C_CEVR.CGRPF bit.
    bit_offset: 31
    bit_size: 1
fieldset/GETCAPR:
  description: I3C get capability register.
  fields:
  - name: CAPPEND
    description: IBI MDB support for pending read notification This bit is written by software during bus initialization (i.e. I3C_CFGR.EN=0) and indicates the support (or not) of the pending read notification via the IBI MDB[7:0] value. This bit is used to return the GETCAP3 byte in response to the GETCAPS CCC format 1.
    bit_offset: 14
    bit_size: 1
fieldset/GETMXDSR:
  description: I3C get capability register.
  fields:
  - name: HOFFAS
    description: controller hand-off activity state This bit is written by software during bus initialization (i.e. I3C_CFGR.EN=0) and indicates in which initial activity state the (other) current controller should expect the I3C bus after a controller-role hand-off to this controller-capable I3C, when returning the defining byte CRHDLY (0x91) to a GETMXDS CCC. This 2-bit field is used to return the CRHDLY1 byte in response to the GETCAPS CCC format 3, in order to state which is the activity state of this I3C when becoming controller after a controller-role hand-off, and consequently the time the former controller should wait before testing this I3C to be confirmed its ownership.
    bit_offset: 0
    bit_size: 2
  - name: FMT
    description: GETMXDS CCC format.
    bit_offset: 8
    bit_size: 2
  - name: RDTURN
    description: programmed byte of the 3-byte MaxRdTurn (maximum read turnaround byte) This bit is written by software during bus initialization (i.e. I3C_CFGR.EN=0) and writes the value of the selected byte (via the FMT[1:0] field) of the 3-byte MaxRdTurn which is returned in response to the GETMXDS CCC format 2 to encode the maximum read turnaround time.
    bit_offset: 16
    bit_size: 8
  - name: TSCO
    description: clock-to-data turnaround time (tSCO) This bit is written by software during bus initialization (i.e. I3C_CFGR.EN=0) and is used to specify the clock-to-data turnaround time tSCO (vs the value of 12 ns). This bit is used by the hardware in response to the GETMXDS CCC to return the encoded clock-to-data turnaround time via the returned MaxRd[5:3] bits.
    bit_offset: 24
    bit_size: 1
fieldset/IBIDR:
  description: I3C IBI payload data register.
  fields:
  - name: IBIDB0
    description: 8-bit IBI payload data (earliest byte on I3C bus, i.e. MDB[7:0] mandatory data byte).
    bit_offset: 0
    bit_size: 8
  - name: IBIDB1
    description: 8-bit IBI payload data (next byte on I3C bus after IBIDB0[7:0]).
    bit_offset: 8
    bit_size: 8
  - name: IBIDB2
    description: 8-bit IBI payload data (next byte on I3C bus after IBIDB1[7:0]).
    bit_offset: 16
    bit_size: 8
  - name: IBIDB3
    description: 8-bit IBI payload data (latest byte on I3C bus).
    bit_offset: 24
    bit_size: 8
fieldset/IER:
  description: I3C interrupt enable register.
  fields:
  - name: CFNFIE
    description: C-FIFO not full interrupt enable (whatever the I3C is acting as controller/target).
    bit_offset: 2
    bit_size: 1
  - name: SFNEIE
    description: S-FIFO not empty interrupt enable (whatever the I3C is acting as controller/target).
    bit_offset: 3
    bit_size: 1
  - name: TXFNFIE
    description: TX-FIFO not full interrupt enable (whatever the I3C is acting as controller/target).
    bit_offset: 4
    bit_size: 1
  - name: RXFNEIE
    description: RX-FIFO not empty interrupt enable (whatever the I3C is acting as controller/target).
    bit_offset: 5
    bit_size: 1
  - name: FCIE
    description: frame complete interrupt enable (whatever the I3C is acting as controller/target).
    bit_offset: 9
    bit_size: 1
  - name: RXTGTENDIE
    description: target-initiated read end interrupt enable (when the I3C is acting as controller).
    bit_offset: 10
    bit_size: 1
  - name: ERRIE
    description: error interrupt enable (whatever the I3C is acting as controller/target).
    bit_offset: 11
    bit_size: 1
  - name: IBIIE
    description: IBI request interrupt enable (when the I3C is acting as controller).
    bit_offset: 15
    bit_size: 1
  - name: IBIENDIE
    description: IBI end interrupt enable (when the I3C is acting as target).
    bit_offset: 16
    bit_size: 1
  - name: CRIE
    description: controller-role request interrupt enable (when the I3C is acting as controller).
    bit_offset: 17
    bit_size: 1
  - name: CRUPDIE
    description: controller-role update interrupt enable (when the I3C is acting as target).
    bit_offset: 18
    bit_size: 1
  - name: HJIE
    description: hot-join interrupt enable (when the I3C is acting as controller).
    bit_offset: 19
    bit_size: 1
  - name: WKPIE
    description: wakeup interrupt enable (when the I3C is acting as target).
    bit_offset: 21
    bit_size: 1
  - name: GETIE
    description: GETxxx CCC interrupt enable (when the I3C is acting as target).
    bit_offset: 22
    bit_size: 1
  - name: STAIE
    description: GETSTATUS CCC interrupt enable (when the I3C is acting as target).
    bit_offset: 23
    bit_size: 1
  - name: DAUPDIE
    description: ENTDAA/RSTDAA/SETNEWDA CCC interrupt enable (when the I3C is acting as target).
    bit_offset: 24
    bit_size: 1
  - name: MWLUPDIE
    description: SETMWL CCC interrupt enable (when the I3C is acting as target).
    bit_offset: 25
    bit_size: 1
  - name: MRLUPDIE
    description: SETMRL CCC interrupt enable (when the I3C is acting as target).
    bit_offset: 26
    bit_size: 1
  - name: RSTIE
    description: reset pattern interrupt enable (when the I3C is acting as target).
    bit_offset: 27
    bit_size: 1
  - name: ASUPDIE
    description: ENTASx CCC interrupt enable (when the I3C is acting as target).
    bit_offset: 28
    bit_size: 1
  - name: INTUPDIE
    description: ENEC/DISEC CCC interrupt enable (when the I3C is acting as target).
    bit_offset: 29
    bit_size: 1
  - name: DEFIE
    description: DEFTGTS CCC interrupt enable (when the I3C is acting as target).
    bit_offset: 30
    bit_size: 1
  - name: GRPIE
    description: DEFGRPA CCC interrupt enable (when the I3C is acting as target).
    bit_offset: 31
    bit_size: 1
fieldset/MAXRLR:
  description: I3C maximum read length register.
  fields:
  - name: MRL
    description: maximum data read length (when I3C is acting as target) This field is initially written by software when I3C_CFGR.EN=0 and updated by hardware on the reception of SETMRL command (with potentially also updated IBIP[2:0]). Software is notified of a MRL update by the I3C_EVR.MRLUPF and the corresponding interrupt if enabled. This field is used by hardware to return the value on the I3C bus when the target receives a GETMRL CCC.
    bit_offset: 0
    bit_size: 16
  - name: IBIP
    description: 'IBI payload data size, in bytes (when I3C is acting as target) This field is initially written by software when I3C_CFGR.EN=0 to set the number of data bytes to be sent to the controller after an IBI request has been acknowledged.This field may be updated by hardware on the reception of SETMRL command (which potentially also updated IBIP[2:0]). Software is notified of a MRL update by the I3C_EVR.MRLUPF and the corresponding interrupt if enabled. others: same as 100.'
    bit_offset: 16
    bit_size: 3
fieldset/MAXWLR:
  description: I3C maximum write length register.
  fields:
  - name: MWL
    description: maximum data write length (when I3C is acting as target) This field is initially written by software when I3C_CFGR.EN=0 and updated by hardware on the reception of SETMWL command. Software is notified of a MWL update by the I3C_EVR.MWLUPF and the corresponding interrupt if enabled. This field is used by hardware to return the value on the I3C bus when the target receives a GETMWL CCC.
    bit_offset: 0
    bit_size: 16
fieldset/RMR:
  description: I3C received message register.
  fields:
  - name: IBIRDCNT
    description: IBI received payload data count (when the I3C is configured as controller) When the I3C is configured as controller, this field logs the number of data bytes effectively received in the I3C_IBIDR register.
    bit_offset: 0
    bit_size: 3
  - name: RCODE
    description: received CCC code (when the I3C is configured as target) When the I3C is configured as target, this field logs the received CCC code.
    bit_offset: 8
    bit_size: 8
  - name: RADD
    description: received target address (when the I3C is configured as controller) When the I3C is configured as controller, this field logs the received dynamic address from the target during acknowledged IBI or controller-role request.
    bit_offset: 17
    bit_size: 7
fieldset/SER:
  description: I3C status error register.
  fields:
  - name: CODERR
    description: 'protocol error code/type controller detected an illegally formatted CCC controller detected that transmitted data on the bus is different from expected controller detected a not acknowledged broadcast address (7’hE) controller detected the new controller did not drive bus after controller-role hand-off target detected an invalid broadcast address 7’hE+W target detected a parity error on a CCC code via a parity check (vs T bit) target detected a parity error on a write data via a parity check (vs T bit) target detected a parity error on the assigned address during dynamic address arbitration via a parity check (vs PAR bit) target detected a 7’hE+R missing after Sr during dynamic address arbitration target detected an illegally formatted CCC target detected that transmitted data on the bus is different from expected others: reserved.'
    bit_offset: 0
    bit_size: 4
  - name: PERR
    description: protocol error.
    bit_offset: 4
    bit_size: 1
  - name: STALL
    description: SCL stall error (when the I3C is acting as target).
    bit_offset: 5
    bit_size: 1
  - name: DOVR
    description: 'RX-FIFO overrun or TX-FIFO underrun i) a TX-FIFO underrun: TX-FIFO is empty and a write data byte has to be transmitted ii) a RX-FIFO overrun: RX-FIFO is full and a new data byte is received.'
    bit_offset: 6
    bit_size: 1
  - name: COVR
    description: 'C-FIFO underrun or S-FIFO overrun (when the I3C is acting as controller) i) a C-FIFO underrun: control FIFO is empty and a restart has to be emitted ii) a S-FIFO overrun: S-FIFO is full and a new message ends.'
    bit_offset: 7
    bit_size: 1
  - name: ANACK
    description: address not acknowledged (when the I3C is configured as controller) i) a legacy I2C read/write transfer ii) a direct CCC write transfer iii) the second trial of a direct CCC read transfer iv) a private read/write transfer.
    bit_offset: 8
    bit_size: 1
  - name: DNACK
    description: data not acknowledged (when the I3C is acting as controller) i) a legacy I2C write transfer ii) the second trial when sending dynamic address during ENTDAA procedure.
    bit_offset: 9
    bit_size: 1
  - name: DERR
    description: data error (when the I3C is acting as controller).
    bit_offset: 10
    bit_size: 1
fieldset/SR:
  description: I3C status register.
  fields:
  - name: XDCNT
    description: 'data counter - When the I3C is acting as controller: number of targets detected on the bus - When the I3C is acting as target: number of transmitted bytes - Whatever the I3C is acting as controller or target: number of data bytes read from or transmitted on the I3C bus during the MID[7:0] message.'
    bit_offset: 0
    bit_size: 16
  - name: ABT
    description: a private read message is completed/aborted prematurely by the target (when the I3C is acting as controller) When the I3C is acting as controller, this bit indicates if the private read data which is transmitted by the target early terminates (i.e. the target drives T bit low earlier vs what does expect the controller in terms of programmed number of read data bytes i.e. I3C_CR.DCNT[15:0]).
    bit_offset: 17
    bit_size: 1
  - name: DIR
    description: 'message direction Whatever the I3C is acting as controller or target, this bit indicates the direction of the related message on the I3C bus Note: ENTDAA CCC is considered as a write command.'
    bit_offset: 18
    bit_size: 1
  - name: MID
    description: message identifier/counter of a given frame (when the I3C is acting as controller) When the I3C is acting as controller, this field identifies the control word message (i.e. I3C_CR) to which the I3C_SR status register refers. First message of a frame is identified with MID[7:0]=0. This field is incremented (by hardware) on the completion of a new message control word (i.e. I3C_CR) over I3C bus. This field is reset for every new frame start.
    bit_offset: 24
    bit_size: 8
fieldset/TGTTDR:
  description: I3C target transmit configuration register.
  fields:
  - name: TGTTDCNT
    description: transmit data counter, in bytes (when I3C is configured as target) This field must be written by software in the same access when is asserted PRELOAD, in order to define the number of bytes to preload and to transmit. This field is updated by hardware and reports, when read, the remaining number of bytes to be loaded into the TX-FIFO.
    bit_offset: 0
    bit_size: 16
  - name: PRELOAD
    description: preload of the TX-FIFO (when I3C is configured as target) This bit must be written and asserted by software in the same access when is written and defined the number of bytes to preload into the TX-FIFO and to transmit. This bit is cleared by hardware when all the data bytes to transmit are loaded into the TX-FIFO.
    bit_offset: 16
    bit_size: 1
fieldset/TIMINGR0:
  description: I3C timing register 0.
  fields:
  - name: SCLL_PP
    description: 'SCL low duration in I3C push-pull phases, in number of kernel clocks cycles: tSCLL_PP = (SCLL_PP + 1) x tI3CCLK SCLL_PP is used to generate tLOW (I3C) timing.'
    bit_offset: 0
    bit_size: 8
  - name: SCLH_I3C
    description: 'SCL high duration, used for I3C messages (both in push-pull and open-drain phases), in number of kernel clocks cycles: tSCLH_I3C = (SCLH_I3C + 1) x tI3CCLK SCLH_I3C is used to generate both tHIGH (I3C) and tHIGH_MIXED timings.'
    bit_offset: 8
    bit_size: 8
  - name: SCLL_OD
    description: 'SCL low duration in open-drain phases, used for legacy I2C commands and for I3C open-drain phases (address header phase following a START, not a Repeated START), in number of kernel clocks cycles: tSCLL_OD = (SCLL_OD + 1) x tI3CCLK SCLL_OD is used to generate both tLOW (I2C) and tLOW_OD timings (max. of the two).'
    bit_offset: 16
    bit_size: 8
  - name: SCLH_I2C
    description: 'SCL high duration, used for legacy I2C commands, in number of kernel clocks cycles: tSCLH_I2C = (SCLH_I2C + 1) x tI3CCLK SCLH_I2C is used to generate tHIGH (I2C) timing.'
    bit_offset: 24
    bit_size: 8
fieldset/TIMINGR1:
  description: I3C timing register 1.
  fields:
  - name: AVAL
    description: 'number of kernel clock cycles, that is used whatever I3C is acting as controller or target, to set the following MIPI I3C timings, like bus available condition time: When the I3C is acting as target: for bus available condition time: it must wait for (bus available condition) time to be elapsed after a stop and before issuing a start request for an IBI or a controller-role request (i.e. bus free condition is sustained for at least tAVAL). refer to MIPI timing tAVAL = 1 <20>s. This timing is defined by: tAVAL = (AVAL[7:0] + 2) x tI3CCLK for bus idle condition time: it must wait for (bus idle condition) time to be elapsed after that both SDA and SCL are continuously high and stable before issuing a hot-join event. Refer to MIPI v1.1 timing tIDLE = 200 <20>s . This timing is defined by: tIDLE = (AVAL[7:0] + 2) x 200 x tI3CCLK When the I3C is acting as controller, it can not stall the clock beyond a maximum stall time (i.e. stall the SCL clock low), as follows: on first bit of assigned address during dynamic address assignment: it can not stall the clock beyond the MIPI timing tSTALLDAA = 15 ms. This timing is defined by: tSTALLDAA = (AVAL[7:0] + 1) x 15000 x tI3CCLK on ACK/NACK phase of I3C/I2C transfer, on parity bit of write data transfer, on transition bit of I3C read transfer: it can not stall the clock beyond the MIPI timing tSTALL = 100 <20>s. This timing is defined by: tSTALL = (AVAL[7:0] + 1) x 100 x tI3CCLK Whatever the I3C is acting as controller or as (controller-capable) target, during a controller-role hand-off procedure: The new controller must wait for a time (refer to MIPI timing tNEWCRLock) before pulling SDA low (i.e. issuing a start). And the active controller must wait for the same time while monitoring new controller and before testing the new controller by pulling SDA low. This time to wait is dependent on the defined I3C_TIMINGR1.ANSCR[1:0], as follows: If ASNCR[1:0]=00: tNEWCRLock = (AVAL[7:0] + 1) x tI3CCLK If ASNCR[1:0]=01: tNEWCRLock = (AVAL[7:0] + 1) x 100 x tI3CCLK If ASNCR[1:0]=10: tNEWCRLock = (AVAL[7:0] + 1) x 2000 x tI3CCLK If ASNCR[1:0]=11: tNEWCRLock = (AVAL[7:0] + 1) x 50000 x tI3CCLK.'
    bit_offset: 0
    bit_size: 8
  - name: ASNCR
    description: activity state of the new controller (when I3C is acting as - active- controller) This field indicates the time to wait before being accessed as new target, refer to the other field AVAL[7:0]. This field can be modified only when the I3C is acting as controller.
    bit_offset: 8
    bit_size: 2
  - name: FREE
    description: 'number of kernel clocks cycles that is used to set some MIPI timings like bus free condition time (when the I3C is acting as controller) When the I3C is acting as controller: for I3C start timing: it must wait for (bus free condition) time to be elapsed after a stop and before a start, refer to MIPI timings (I3C) tCAS and (I2C) tBUF. These timings are defined by: tBUF= tCAS = [ (FREE[6:0] + 1) x 2 - (0,5 + SDA_HD)] x tI3CCLK Note: for pure I3C bus: tCASmin= 38,4 ns. Note: for pure I3C bus: tCASmax=1<>s, 100<30>s, 2ms, 50ms for respectively ENTAS0,1,2, and 3. Note: for mixed bus with I2C fm+ device: tBUFmin = 0,5 <20>s. Note: for mixed bus with I2C fm device: tBUFmin = 1,3 <20>s. for I3C repeated start timing: it must wait for time to be elapsed after a repeated start (i.e. SDA is de-asserted) and before driving SCL low, refer to. MIPI timing tCASr. This timing is defined by: tCASr = [ (FREE[6:0] + 1) x 2 - (0,5 + SDA_HD)] x tI3CCLK for I3C stop timing: it must wait for time to be elapsed after that the SCL clock is driven high and before the stop condition (i.e. SDA is asserted). This timing is defined by: tCBP = (FREE[6:0] + 1) x tI3CCLK for I3C repeated start timing (T-bit when controller ends read with repeated start followed by stop): it must wait for time to be elapsed after that the SCL clock is driven high and before the repeated start condition (i.e. SDA is de-asserted). This timing is defined by: tCBSr = (FREE[6:0] + 1) x tI3CCLK.'
    bit_offset: 16
    bit_size: 7
  - name: SDA_HD
    description: SDA hold time (when the I3C is acting as controller), in number of kernel clocks cycles (refer to MIPI timing SDA hold time in push-pull tHD_PP):.
    bit_offset: 28
    bit_size: 1
fieldset/TIMINGR2:
  description: I3C timing register 2.
  fields:
  - name: STALLT
    description: Controller clock stall on T-bit phase of Data enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase (before 9th bit). This allows the target to prepare data to be sent.
    bit_offset: 0
    bit_size: 1
  - name: STALLD
    description: controller clock stall on PAR phase of Data enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase (before 9th bit). This allows the target to read received data.
    bit_offset: 1
    bit_size: 1
  - name: STALLC
    description: controller clock stall on PAR phase of CCC enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase of common command code (before 9th bit). This allows the target to decode the command.
    bit_offset: 2
    bit_size: 1
  - name: STALLA
    description: controller clock stall enable on ACK phase The SCL is stalled (during tSCLL_STALLas defined by STALL) in the address ACK/NACK phase (before 9th bit). This allows the target to prepare data or the controller to respond to target interrupt.
    bit_offset: 3
    bit_size: 1
  - name: STALL
    description: controller clock stall time, in number of kernel clock cycles tSCLL_STALL = STALL x tI3CCLK.
    bit_offset: 8
    bit_size: 8