stm32-data/data/registers/rcc_l4.yaml

block/RCC:
  description: Reset and clock control
  items:
  - byte_offset: 0
    description: Clock control register
    fieldset: CR
    name: CR
  - byte_offset: 4
    description: Internal clock sources calibration register
    fieldset: ICSCR
    name: ICSCR
  - byte_offset: 8
    description: Clock configuration register
    fieldset: CFGR
    name: CFGR
  - byte_offset: 12
    description: PLL configuration register
    fieldset: PLLCFGR
    name: PLLCFGR
  - byte_offset: 16
    description: PLLSAI1 configuration register
    fieldset: PLLSAI1CFGR
    name: PLLSAI1CFGR
  - byte_offset: 20
    description: PLLSAI2 configuration register
    fieldset: PLLSAI2CFGR
    name: PLLSAI2CFGR
  - byte_offset: 24
    description: Clock interrupt enable register
    fieldset: CIER
    name: CIER
  - access: Read
    byte_offset: 28
    description: Clock interrupt flag register
    fieldset: CIFR
    name: CIFR
  - access: Write
    byte_offset: 32
    description: Clock interrupt clear register
    fieldset: CICR
    name: CICR
  - byte_offset: 40
    description: AHB1 peripheral reset register
    fieldset: AHB1RSTR
    name: AHB1RSTR
  - byte_offset: 44
    description: AHB2 peripheral reset register
    fieldset: AHB2RSTR
    name: AHB2RSTR
  - byte_offset: 48
    description: AHB3 peripheral reset register
    fieldset: AHB3RSTR
    name: AHB3RSTR
  - byte_offset: 56
    description: APB1 peripheral reset register 1
    fieldset: APB1RSTR1
    name: APB1RSTR1
  - byte_offset: 60
    description: APB1 peripheral reset register 2
    fieldset: APB1RSTR2
    name: APB1RSTR2
  - byte_offset: 64
    description: APB2 peripheral reset register
    fieldset: APB2RSTR
    name: APB2RSTR
  - byte_offset: 72
    description: AHB1 peripheral clock enable register
    fieldset: AHB1ENR
    name: AHB1ENR
  - byte_offset: 76
    description: AHB2 peripheral clock enable register
    fieldset: AHB2ENR
    name: AHB2ENR
  - byte_offset: 80
    description: AHB3 peripheral clock enable register
    fieldset: AHB3ENR
    name: AHB3ENR
  - byte_offset: 88
    description: APB1ENR1
    fieldset: APB1ENR1
    name: APB1ENR1
  - byte_offset: 92
    description: APB1 peripheral clock enable register 2
    fieldset: APB1ENR2
    name: APB1ENR2
  - byte_offset: 96
    description: APB2ENR
    fieldset: APB2ENR
    name: APB2ENR
  - byte_offset: 104
    description: AHB1 peripheral clocks enable in Sleep and Stop modes register
    fieldset: AHB1SMENR
    name: AHB1SMENR
  - byte_offset: 108
    description: AHB2 peripheral clocks enable in Sleep and Stop modes register
    fieldset: AHB2SMENR
    name: AHB2SMENR
  - byte_offset: 112
    description: AHB3 peripheral clocks enable in Sleep and Stop modes register
    fieldset: AHB3SMENR
    name: AHB3SMENR
  - byte_offset: 120
    description: APB1SMENR1
    fieldset: APB1SMENR1
    name: APB1SMENR1
  - byte_offset: 124
    description: APB1 peripheral clocks enable in Sleep and Stop modes register 2
    fieldset: APB1SMENR2
    name: APB1SMENR2
  - byte_offset: 128
    description: APB2SMENR
    fieldset: APB2SMENR
    name: APB2SMENR
  - byte_offset: 136
    description: CCIPR
    fieldset: CCIPR
    name: CCIPR
  - byte_offset: 144
    description: BDCR
    fieldset: BDCR
    name: BDCR
  - byte_offset: 148
    description: CSR
    fieldset: CSR
    name: CSR
  - byte_offset: 152
    description: Clock recovery RC register
    fieldset: CRRCR
    name: CRRCR
  - byte_offset: 156
    description: Peripherals independent clock configuration register
    fieldset: CCIPR2
    name: CCIPR2
enum/MSIRANGE:
  bit_size: 4
  variants:
  - description: range 0 around 100 kHz
    name: Range100K
    value: 0
  - description: range 1 around 200 kHz
    name: Range200K
    value: 1
  - description: range 2 around 400 kHz
    name: Range400K
    value: 2
  - description: range 3 around 800 kHz
    name: Range800K
    value: 3
  - description: range 4 around 1 MHz
    name: Range1M
    value: 4
  - description: range 5 around 2 MHz
    name: Range2M
    value: 5
  - description: range 6 around 4 MHz
    name: Range4M
    value: 6
  - description: range 7 around 8 MHz
    name: Range8M
    value: 7
  - description: range 8 around 16 MHz
    name: Range16M
    value: 8
  - description: range 9 around 24 MHz
    name: Range24M
    value: 9
  - description: range 10 around 32 MHz
    name: Range32M
    value: 10
  - description: range 11 around 48 MHz
    name: Range48M
    value: 11
fieldset/AHB1ENR:
  description: AHB1 peripheral clock enable register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: DMA1 clock enable
    name: DMA1EN
  - bit_offset: 1
    bit_size: 1
    description: DMA2 clock enable
    name: DMA2EN
  - bit_offset: 2
    bit_size: 1
    description: DMAMUX clock enable
    name: DMAMUX1EN
  - bit_offset: 8
    bit_size: 1
    description: Flash memory interface clock enable
    name: FLASHEN
  - bit_offset: 12
    bit_size: 1
    description: CRC clock enable
    name: CRCEN
  - bit_offset: 16
    bit_size: 1
    description: Touch Sensing Controller clock enable
    name: TSCEN
  - bit_offset: 17
    bit_size: 1
    description: DMA2D clock enable
    name: DMA2DEN
  - bit_offset: 18
    bit_size: 1
    description: Graphic MMU clock enable
    name: GFXMMUEN
fieldset/AHB1RSTR:
  description: AHB1 peripheral reset register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: DMA1 reset
    name: DMA1RST
  - bit_offset: 1
    bit_size: 1
    description: DMA2 reset
    name: DMA2RST
  - bit_offset: 2
    bit_size: 1
    description: DMAMUXRST
    name: DMAMUX1RST
  - bit_offset: 8
    bit_size: 1
    description: Flash memory interface reset
    name: FLASHRST
  - bit_offset: 12
    bit_size: 1
    description: CRC reset
    name: CRCRST
  - bit_offset: 16
    bit_size: 1
    description: Touch Sensing Controller reset
    name: TSCRST
  - bit_offset: 17
    bit_size: 1
    description: DMA2D reset
    name: DMA2DRST
  - bit_offset: 18
    bit_size: 1
    description: GFXMMU reset
    name: GFXMMURST
fieldset/AHB1SMENR:
  description: AHB1 peripheral clocks enable in Sleep and Stop modes register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: DMA1 clocks enable during Sleep and Stop modes
    name: DMA1SMEN
  - bit_offset: 1
    bit_size: 1
    description: DMA2 clocks enable during Sleep and Stop modes
    name: DMA2SMEN
  - bit_offset: 2
    bit_size: 1
    description: DMAMUX clock enable during Sleep and Stop modes
    name: DMAMUX1SMEN
  - bit_offset: 8
    bit_size: 1
    description: Flash memory interface clocks enable during Sleep and Stop modes
    name: FLASHSMEN
  - bit_offset: 9
    bit_size: 1
    description: SRAM1 interface clocks enable during Sleep and Stop modes
    name: SRAM1SMEN
  - bit_offset: 12
    bit_size: 1
    description: CRCSMEN
    name: CRCSMEN
  - bit_offset: 16
    bit_size: 1
    description: Touch Sensing Controller clocks enable during Sleep and Stop modes
    name: TSCSMEN
  - bit_offset: 17
    bit_size: 1
    description: DMA2D clock enable during Sleep and Stop modes
    name: DMA2DSMEN
  - bit_offset: 18
    bit_size: 1
    description: GFXMMU clock enable during Sleep and Stop modes
    name: GFXMMUSMEN
fieldset/AHB2ENR:
  description: AHB2 peripheral clock enable register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: IO port A clock enable
    name: GPIOAEN
  - bit_offset: 1
    bit_size: 1
    description: IO port B clock enable
    name: GPIOBEN
  - bit_offset: 2
    bit_size: 1
    description: IO port C clock enable
    name: GPIOCEN
  - bit_offset: 3
    bit_size: 1
    description: IO port D clock enable
    name: GPIODEN
  - bit_offset: 4
    bit_size: 1
    description: IO port E clock enable
    name: GPIOEEN
  - bit_offset: 5
    bit_size: 1
    description: IO port F clock enable
    name: GPIOFEN
  - bit_offset: 6
    bit_size: 1
    description: IO port G clock enable
    name: GPIOGEN
  - bit_offset: 7
    bit_size: 1
    description: IO port H clock enable
    name: GPIOHEN
  - bit_offset: 8
    bit_size: 1
    description: IO port I clock enable
    name: GPIOIEN
  - bit_offset: 12
    bit_size: 1
    description: OTG full speed clock enable
    name: OTGFSEN
  - bit_offset: 13
    bit_size: 1
    description: ADC clock enable
    name: ADCEN
  - bit_offset: 14
    bit_size: 1
    description: DCMI clock enable
    name: DCMIEN
  - bit_offset: 16
    bit_size: 1
    description: AES accelerator clock enable
    name: AESEN
  - bit_offset: 17
    bit_size: 1
    description: HASH clock enable
    name: HASHEN
  - bit_offset: 18
    bit_size: 1
    description: Random Number Generator clock enable
    name: RNGEN
  - bit_offset: 20
    bit_size: 1
    description: OctoSPI IO manager clock enable
    name: OSPIMEN
  - bit_offset: 22
    bit_size: 1
    description: SDMMC1 clock enable
    name: SDMMC1EN
fieldset/AHB2RSTR:
  description: AHB2 peripheral reset register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: IO port A reset
    name: GPIOARST
  - bit_offset: 1
    bit_size: 1
    description: IO port B reset
    name: GPIOBRST
  - bit_offset: 2
    bit_size: 1
    description: IO port C reset
    name: GPIOCRST
  - bit_offset: 3
    bit_size: 1
    description: IO port D reset
    name: GPIODRST
  - bit_offset: 4
    bit_size: 1
    description: IO port E reset
    name: GPIOERST
  - bit_offset: 5
    bit_size: 1
    description: IO port F reset
    name: GPIOFRST
  - bit_offset: 6
    bit_size: 1
    description: IO port G reset
    name: GPIOGRST
  - bit_offset: 7
    bit_size: 1
    description: IO port H reset
    name: GPIOHRST
  - bit_offset: 8
    bit_size: 1
    description: IO port I reset
    name: GPIOIRST
  - bit_offset: 12
    bit_size: 1
    description: USB OTG FS reset
    name: OTGFSRST
  - bit_offset: 13
    bit_size: 1
    description: ADC reset
    name: ADCRST
  - bit_offset: 14
    bit_size: 1
    description: Digital Camera Interface reset
    name: DCMIRST
  - bit_offset: 16
    bit_size: 1
    description: AES hardware accelerator reset
    name: AESRST
  - bit_offset: 17
    bit_size: 1
    description: Hash reset
    name: HASHRST
  - bit_offset: 18
    bit_size: 1
    description: Random number generator reset
    name: RNGRST
  - bit_offset: 20
    bit_size: 1
    description: OCTOSPI IO manager reset
    name: OSPIMRST
  - bit_offset: 22
    bit_size: 1
    description: SDMMC1 reset
    name: SDMMC1RST
fieldset/AHB2SMENR:
  description: AHB2 peripheral clocks enable in Sleep and Stop modes register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: IO port A clocks enable during Sleep and Stop modes
    name: GPIOASMEN
  - bit_offset: 1
    bit_size: 1
    description: IO port B clocks enable during Sleep and Stop modes
    name: GPIOBSMEN
  - bit_offset: 2
    bit_size: 1
    description: IO port C clocks enable during Sleep and Stop modes
    name: GPIOCSMEN
  - bit_offset: 3
    bit_size: 1
    description: IO port D clocks enable during Sleep and Stop modes
    name: GPIODSMEN
  - bit_offset: 4
    bit_size: 1
    description: IO port E clocks enable during Sleep and Stop modes
    name: GPIOESMEN
  - bit_offset: 5
    bit_size: 1
    description: IO port F clocks enable during Sleep and Stop modes
    name: GPIOFSMEN
  - bit_offset: 6
    bit_size: 1
    description: IO port G clocks enable during Sleep and Stop modes
    name: GPIOGSMEN
  - bit_offset: 7
    bit_size: 1
    description: IO port H clocks enable during Sleep and Stop modes
    name: GPIOHSMEN
  - bit_offset: 8
    bit_size: 1
    description: IO port I clocks enable during Sleep and Stop modes
    name: GPIOISMEN
  - bit_offset: 9
    bit_size: 1
    description: SRAM2 interface clocks enable during Sleep and Stop modes
    name: SRAM2SMEN
  - bit_offset: 10
    bit_size: 1
    description: SRAM2 interface clocks enable during Sleep and Stop modes
    name: SRAM3SMEN
  - bit_offset: 12
    bit_size: 1
    description: OTG full speed clocks enable during Sleep and Stop modes
    name: OTGFSSMEN
  - bit_offset: 13
    bit_size: 1
    description: ADC clocks enable during Sleep and Stop modes
    name: ADCFSSMEN
  - bit_offset: 14
    bit_size: 1
    description: DCMI clock enable during Sleep and Stop modes
    name: DCMISMEN
  - bit_offset: 16
    bit_size: 1
    description: AES accelerator clocks enable during Sleep and Stop modes
    name: AESSMEN
  - bit_offset: 17
    bit_size: 1
    description: HASH clock enable during Sleep and Stop modes
    name: HASHSMEN
  - bit_offset: 17
    bit_size: 1
    description: HASH clock enable during Sleep and Stop modes
    name: HASH1SMEN
  - bit_offset: 18
    bit_size: 1
    description: Random Number Generator clocks enable during Sleep and Stop modes
    name: RNGSMEN
  - bit_offset: 20
    bit_size: 1
    description: OctoSPI IO manager clocks enable during Sleep and Stop modes
    name: OSPIMSMEN
  - bit_offset: 22
    bit_size: 1
    description: SDMMC1 clocks enable during Sleep and Stop modes
    name: SDMMC1SMEN
fieldset/AHB3ENR:
  description: AHB3 peripheral clock enable register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: Flexible memory controller clock enable
    name: FMCEN
  - bit_offset: 8
    bit_size: 1
    description: QSPIEN
    name: QSPIEN
  - bit_offset: 9
    bit_size: 1
    description: OSPI2EN memory interface clock enable
    name: OSPI2EN
fieldset/AHB3RSTR:
  description: AHB3 peripheral reset register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: Flexible memory controller reset
    name: FMCRST
  - bit_offset: 8
    bit_size: 1
    description: Quad SPI memory interface reset
    name: QSPIRST
  - bit_offset: 9
    bit_size: 1
    description: OctOSPI2 memory interface reset
    name: OSPI2RST
fieldset/AHB3SMENR:
  description: AHB3 peripheral clocks enable in Sleep and Stop modes register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: Flexible memory controller clocks enable during Sleep and Stop modes
    name: FMCSMEN
  - bit_offset: 8
    bit_size: 1
    description: QSPISMEN
    name: QSPISMEN
  - bit_offset: 9
    bit_size: 1
    description: OctoSPI2 memory interface clocks enable during Sleep and Stop modes
    name: OCTOSPI2
fieldset/APB1ENR1:
  description: APB1ENR1
  fields:
  - bit_offset: 0
    bit_size: 1
    description: TIM2 timer clock enable
    name: TIM2EN
  - bit_offset: 1
    bit_size: 1
    description: TIM3 timer clock enable
    name: TIM3EN
  - bit_offset: 2
    bit_size: 1
    description: TIM4 timer clock enable
    name: TIM4EN
  - bit_offset: 3
    bit_size: 1
    description: TIM5 timer clock enable
    name: TIM5EN
  - bit_offset: 4
    bit_size: 1
    description: TIM6 timer clock enable
    name: TIM6EN
  - bit_offset: 5
    bit_size: 1
    description: TIM7 timer clock enable
    name: TIM7EN
  - bit_offset: 9
    bit_size: 1
    description: LCD clock enable
    name: LCDEN
  - bit_offset: 10
    bit_size: 1
    description: RTC APB clock enable
    name: RTCAPBEN
  - bit_offset: 11
    bit_size: 1
    description: Window watchdog clock enable
    name: WWDGEN
  - bit_offset: 14
    bit_size: 1
    description: SPI2 clock enable
    name: SPI2EN
  - bit_offset: 15
    bit_size: 1
    description: SPI3 clock enable
    name: SPI3EN
  - bit_offset: 17
    bit_size: 1
    description: USART2 clock enable
    name: USART2EN
  - bit_offset: 18
    bit_size: 1
    description: USART3 clock enable
    name: USART3EN
  - bit_offset: 19
    bit_size: 1
    description: UART4 clock enable
    name: UART4EN
  - bit_offset: 20
    bit_size: 1
    description: UART5 clock enable
    name: UART5EN
  - bit_offset: 21
    bit_size: 1
    description: I2C1 clock enable
    name: I2C1EN
  - bit_offset: 22
    bit_size: 1
    description: I2C2 clock enable
    name: I2C2EN
  - bit_offset: 23
    bit_size: 1
    description: I2C3 clock enable
    name: I2C3EN
  - bit_offset: 24
    bit_size: 1
    description: Clock Recovery System clock enable
    name: CRSEN
  - bit_offset: 25
    bit_size: 1
    description: CAN1 clock enable
    name: CAN1EN
  - bit_offset: 26
    bit_size: 1
    description: USB FS clock enable
    name: USBFSEN
  - bit_offset: 26
    bit_size: 1
    description: CAN2 clock enable
    name: CAN2EN
  - bit_offset: 28
    bit_size: 1
    description: Power interface clock enable
    name: PWREN
  - bit_offset: 29
    bit_size: 1
    description: DAC1 interface clock enable
    name: DAC1EN
  - bit_offset: 30
    bit_size: 1
    description: OPAMP interface clock enable
    name: OPAMPEN
  - bit_offset: 31
    bit_size: 1
    description: Low power timer 1 clock enable
    name: LPTIM1EN
fieldset/APB1ENR2:
  description: APB1 peripheral clock enable register 2
  fields:
  - bit_offset: 0
    bit_size: 1
    description: Low power UART 1 clock enable
    name: LPUART1EN
  - bit_offset: 1
    bit_size: 1
    description: I2C4 clock enable
    name: I2C4EN
  - bit_offset: 2
    bit_size: 1
    description: Single wire protocol clock enable
    name: SWPMI1EN
  - bit_offset: 5
    bit_size: 1
    description: LPTIM2EN
    name: LPTIM2EN
  - bit_offset: 24
    bit_size: 1
    description: DFSDMEN enable
    name: DFSDMEN
fieldset/APB1RSTR1:
  description: APB1 peripheral reset register 1
  fields:
  - bit_offset: 0
    bit_size: 1
    description: TIM2 timer reset
    name: TIM2RST
  - bit_offset: 1
    bit_size: 1
    description: TIM3 timer reset
    name: TIM3RST
  - bit_offset: 2
    bit_size: 1
    description: TIM3 timer reset
    name: TIM4RST
  - bit_offset: 3
    bit_size: 1
    description: TIM5 timer reset
    name: TIM5RST
  - bit_offset: 4
    bit_size: 1
    description: TIM6 timer reset
    name: TIM6RST
  - bit_offset: 5
    bit_size: 1
    description: TIM7 timer reset
    name: TIM7RST
  - bit_offset: 9
    bit_size: 1
    description: LCD interface reset
    name: LCDRST
  - bit_offset: 14
    bit_size: 1
    description: SPI2 reset
    name: SPI2RST
  - bit_offset: 15
    bit_size: 1
    description: SPI3 reset
    name: SPI3RST
  - bit_offset: 17
    bit_size: 1
    description: USART2 reset
    name: USART2RST
  - bit_offset: 18
    bit_size: 1
    description: USART3 reset
    name: USART3RST
  - bit_offset: 19
    bit_size: 1
    description: UART4 reset
    name: UART4RST
  - bit_offset: 20
    bit_size: 1
    description: UART5 reset
    name: UART5RST
  - bit_offset: 21
    bit_size: 1
    description: I2C1 reset
    name: I2C1RST
  - bit_offset: 22
    bit_size: 1
    description: I2C2 reset
    name: I2C2RST
  - bit_offset: 23
    bit_size: 1
    description: I2C3 reset
    name: I2C3RST
  - bit_offset: 24
    bit_size: 1
    description: CRS reset
    name: CRSRST
  - bit_offset: 25
    bit_size: 1
    description: CAN1 reset
    name: CAN1RST
  - bit_offset: 26
    bit_size: 1
    description: USB FS reset
    name: USBFSRST
  - bit_offset: 26
    bit_size: 1
    description: CAN2 reset
    name: CAN2RST
  - bit_offset: 28
    bit_size: 1
    description: Power interface reset
    name: PWRRST
  - bit_offset: 29
    bit_size: 1
    description: DAC1 interface reset
    name: DAC1RST
  - bit_offset: 30
    bit_size: 1
    description: OPAMP interface reset
    name: OPAMPRST
  - bit_offset: 31
    bit_size: 1
    description: Low Power Timer 1 reset
    name: LPTIM1RST
fieldset/APB1RSTR2:
  description: APB1 peripheral reset register 2
  fields:
  - bit_offset: 0
    bit_size: 1
    description: Low-power UART 1 reset
    name: LPUART1RST
  - bit_offset: 1
    bit_size: 1
    description: I2C4 reset
    name: I2C4RST
  - bit_offset: 2
    bit_size: 1
    description: Single wire protocol reset
    name: SWPMI1RST
  - bit_offset: 5
    bit_size: 1
    description: Low-power timer 2 reset
    name: LPTIM2RST
fieldset/APB1SMENR1:
  description: APB1SMENR1
  fields:
  - bit_offset: 0
    bit_size: 1
    description: TIM2 timer clocks enable during Sleep and Stop modes
    name: TIM2SMEN
  - bit_offset: 1
    bit_size: 1
    description: TIM3 timer clocks enable during Sleep and Stop modes
    name: TIM3SMEN
  - bit_offset: 2
    bit_size: 1
    description: TIM4 timer clocks enable during Sleep and Stop modes
    name: TIM4SMEN
  - bit_offset: 3
    bit_size: 1
    description: TIM5 timer clocks enable during Sleep and Stop modes
    name: TIM5SMEN
  - bit_offset: 4
    bit_size: 1
    description: TIM6 timer clocks enable during Sleep and Stop modes
    name: TIM6SMEN
  - bit_offset: 5
    bit_size: 1
    description: TIM7 timer clocks enable during Sleep and Stop modes
    name: TIM7SMEN
  - bit_offset: 9
    bit_size: 1
    description: LCD clocks enable during Sleep and Stop modes
    name: LCDSMEN
  - bit_offset: 10
    bit_size: 1
    description: RTC APB clock enable during Sleep and Stop modes
    name: RTCAPBSMEN
  - bit_offset: 11
    bit_size: 1
    description: Window watchdog clocks enable during Sleep and Stop modes
    name: WWDGSMEN
  - bit_offset: 14
    bit_size: 1
    description: SPI2 clocks enable during Sleep and Stop modes
    name: SPI2SMEN
  - bit_offset: 15
    bit_size: 1
    description: SPI3 clocks enable during Sleep and Stop modes
    name: SP3SMEN
  - bit_offset: 17
    bit_size: 1
    description: USART2 clocks enable during Sleep and Stop modes
    name: USART2SMEN
  - bit_offset: 18
    bit_size: 1
    description: USART3 clocks enable during Sleep and Stop modes
    name: USART3SMEN
  - bit_offset: 19
    bit_size: 1
    description: UART4 clocks enable during Sleep and Stop modes
    name: UART4SMEN
  - bit_offset: 20
    bit_size: 1
    description: UART5 clocks enable during Sleep and Stop modes
    name: UART5SMEN
  - bit_offset: 21
    bit_size: 1
    description: I2C1 clocks enable during Sleep and Stop modes
    name: I2C1SMEN
  - bit_offset: 22
    bit_size: 1
    description: I2C2 clocks enable during Sleep and Stop modes
    name: I2C2SMEN
  - bit_offset: 23
    bit_size: 1
    description: I2C3 clocks enable during Sleep and Stop modes
    name: I2C3SMEN
  - bit_offset: 24
    bit_size: 1
    description: CRS clock enable during Sleep and Stop modes
    name: CRSSMEN
  - bit_offset: 25
    bit_size: 1
    description: CAN1 clocks enable during Sleep and Stop modes
    name: CAN1SMEN
  - bit_offset: 26
    bit_size: 1
    description: USB FS clock enable during Sleep and Stop modes
    name: USBFSSMEN
  - bit_offset: 26
    bit_size: 1
    description: CAN2 clocks enable during Sleep and Stop modes
    name: CAN2SMEN
  - bit_offset: 28
    bit_size: 1
    description: Power interface clocks enable during Sleep and Stop modes
    name: PWRSMEN
  - bit_offset: 29
    bit_size: 1
    description: DAC1 interface clocks enable during Sleep and Stop modes
    name: DAC1SMEN
  - bit_offset: 30
    bit_size: 1
    description: OPAMP interface clocks enable during Sleep and Stop modes
    name: OPAMPSMEN
  - bit_offset: 31
    bit_size: 1
    description: Low power timer 1 clocks enable during Sleep and Stop modes
    name: LPTIM1SMEN
fieldset/APB1SMENR2:
  description: APB1 peripheral clocks enable in Sleep and Stop modes register 2
  fields:
  - bit_offset: 0
    bit_size: 1
    description: Low power UART 1 clocks enable during Sleep and Stop modes
    name: LPUART1SMEN
  - bit_offset: 1
    bit_size: 1
    description: I2C4 clocks enable during Sleep and Stop modes
    name: I2C4SMEN
  - bit_offset: 2
    bit_size: 1
    description: Single wire protocol clocks enable during Sleep and Stop modes
    name: SWPMI1SMEN
  - bit_offset: 5
    bit_size: 1
    description: LPTIM2SMEN
    name: LPTIM2SMEN
fieldset/APB2ENR:
  description: APB2ENR
  fields:
  - bit_offset: 0
    bit_size: 1
    description: SYSCFG clock enable
    name: SYSCFGEN
  - bit_offset: 7
    bit_size: 1
    description: Firewall clock enable
    name: FWEN
  - bit_offset: 7
    bit_size: 1
    description: Firewall clock enable
    name: FIREWALLEN
  - bit_offset: 10
    bit_size: 1
    description: SDMMC clock enable
    name: SDMMCEN
  - bit_offset: 11
    bit_size: 1
    description: TIM1 timer clock enable
    name: TIM1EN
  - bit_offset: 12
    bit_size: 1
    description: SPI1 clock enable
    name: SPI1EN
  - bit_offset: 13
    bit_size: 1
    description: TIM8 timer clock enable
    name: TIM8EN
  - bit_offset: 14
    bit_size: 1
    description: USART1clock enable
    name: USART1EN
  - bit_offset: 16
    bit_size: 1
    description: TIM15 timer clock enable
    name: TIM15EN
  - bit_offset: 17
    bit_size: 1
    description: TIM16 timer clock enable
    name: TIM16EN
  - bit_offset: 18
    bit_size: 1
    description: TIM17 timer clock enable
    name: TIM17EN
  - bit_offset: 21
    bit_size: 1
    description: SAI1 clock enable
    name: SAI1EN
  - bit_offset: 22
    bit_size: 1
    description: SAI2 clock enable
    name: SAI2EN
  - bit_offset: 24
    bit_size: 1
    description: DFSDM timer clock enable
    name: DFSDM1EN
  - bit_offset: 24
    bit_size: 1
    description: DFSDM timer clock enable
    name: DFSDMEN
  - bit_offset: 26
    bit_size: 1
    description: LCD-TFT clock enable
    name: LTDCEN
  - bit_offset: 27
    bit_size: 1
    description: DSI clock enable
    name: DSIEN
fieldset/APB2RSTR:
  description: APB2 peripheral reset register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: System configuration (SYSCFG) reset
    name: SYSCFGRST
  - bit_offset: 10
    bit_size: 1
    description: SDMMC reset
    name: SDMMCRST
  - bit_offset: 11
    bit_size: 1
    description: TIM1 timer reset
    name: TIM1RST
  - bit_offset: 12
    bit_size: 1
    description: SPI1 reset
    name: SPI1RST
  - bit_offset: 13
    bit_size: 1
    description: TIM8 timer reset
    name: TIM8RST
  - bit_offset: 14
    bit_size: 1
    description: USART1 reset
    name: USART1RST
  - bit_offset: 16
    bit_size: 1
    description: TIM15 timer reset
    name: TIM15RST
  - bit_offset: 17
    bit_size: 1
    description: TIM16 timer reset
    name: TIM16RST
  - bit_offset: 18
    bit_size: 1
    description: TIM17 timer reset
    name: TIM17RST
  - bit_offset: 21
    bit_size: 1
    description: Serial audio interface 1 (SAI1) reset
    name: SAI1RST
  - bit_offset: 22
    bit_size: 1
    description: Serial audio interface 2 (SAI2) reset
    name: SAI2RST
  - bit_offset: 24
    bit_size: 1
    description: Digital filters for sigma-delata modulators (DFSDM) reset
    name: DFSDM1RST
  - bit_offset: 24
    bit_size: 1
    description: DFSDM filter reset
    name: DFSDMRST
  - bit_offset: 26
    bit_size: 1
    description: LCD-TFT reset
    name: LTDCRST
  - bit_offset: 27
    bit_size: 1
    description: DSI reset
    name: DSIRST
fieldset/APB2SMENR:
  description: APB2SMENR
  fields:
  - bit_offset: 0
    bit_size: 1
    description: SYSCFG clocks enable during Sleep and Stop modes
    name: SYSCFGSMEN
  - bit_offset: 10
    bit_size: 1
    description: SDMMC clocks enable during Sleep and Stop modes
    name: SDMMCSMEN
  - bit_offset: 11
    bit_size: 1
    description: TIM1 timer clocks enable during Sleep and Stop modes
    name: TIM1SMEN
  - bit_offset: 12
    bit_size: 1
    description: SPI1 clocks enable during Sleep and Stop modes
    name: SPI1SMEN
  - bit_offset: 13
    bit_size: 1
    description: TIM8 timer clocks enable during Sleep and Stop modes
    name: TIM8SMEN
  - bit_offset: 14
    bit_size: 1
    description: USART1clocks enable during Sleep and Stop modes
    name: USART1SMEN
  - bit_offset: 16
    bit_size: 1
    description: TIM15 timer clocks enable during Sleep and Stop modes
    name: TIM15SMEN
  - bit_offset: 17
    bit_size: 1
    description: TIM16 timer clocks enable during Sleep and Stop modes
    name: TIM16SMEN
  - bit_offset: 18
    bit_size: 1
    description: TIM17 timer clocks enable during Sleep and Stop modes
    name: TIM17SMEN
  - bit_offset: 21
    bit_size: 1
    description: SAI1 clocks enable during Sleep and Stop modes
    name: SAI1SMEN
  - bit_offset: 22
    bit_size: 1
    description: SAI2 clocks enable during Sleep and Stop modes
    name: SAI2SMEN
  - bit_offset: 24
    bit_size: 1
    description: DFSDM timer clocks enable during Sleep and Stop modes
    name: DFSDM1SMEN
  - bit_offset: 24
    bit_size: 1
    description: DFSDM timer clocks enable during Sleep and Stop modes
    name: DFSDMSMEN
  - bit_offset: 26
    bit_size: 1
    description: LCD-TFT timer clocks enable during Sleep and Stop modes
    name: LTDCSMEN
  - bit_offset: 27
    bit_size: 1
    description: DSI clocks enable during Sleep and Stop modes
    name: DSISMEN
fieldset/BDCR:
  description: BDCR
  fields:
  - bit_offset: 0
    bit_size: 1
    description: LSE oscillator enable
    name: LSEON
  - bit_offset: 1
    bit_size: 1
    description: LSE oscillator ready
    name: LSERDY
  - bit_offset: 2
    bit_size: 1
    description: LSE oscillator bypass
    name: LSEBYP
  - bit_offset: 3
    bit_size: 2
    description: SE oscillator drive capability
    name: LSEDRV
  - bit_offset: 5
    bit_size: 1
    description: LSECSSON
    name: LSECSSON
  - bit_offset: 6
    bit_size: 1
    description: LSECSSD
    name: LSECSSD
  - bit_offset: 8
    bit_size: 2
    description: RTC clock source selection
    name: RTCSEL
  - bit_offset: 15
    bit_size: 1
    description: RTC clock enable
    name: RTCEN
  - bit_offset: 16
    bit_size: 1
    description: Backup domain software reset
    name: BDRST
  - bit_offset: 24
    bit_size: 1
    description: Low speed clock output enable
    name: LSCOEN
  - bit_offset: 25
    bit_size: 1
    description: Low speed clock output selection
    name: LSCOSEL
fieldset/CCIPR:
  description: CCIPR
  fields:
  - bit_offset: 0
    bit_size: 2
    description: USART1 clock source selection
    name: USART1SEL
  - bit_offset: 2
    bit_size: 2
    description: USART2 clock source selection
    name: USART2SEL
  - bit_offset: 4
    bit_size: 2
    description: USART3 clock source selection
    name: USART3SEL
  - bit_offset: 6
    bit_size: 2
    description: UART4 clock source selection
    name: UART4SEL
  - bit_offset: 8
    bit_size: 2
    description: UART5 clock source selection
    name: UART5SEL
  - bit_offset: 10
    bit_size: 2
    description: LPUART1 clock source selection
    name: LPUART1SEL
  - bit_offset: 12
    bit_size: 2
    description: I2C1 clock source selection
    name: I2C1SEL
  - bit_offset: 14
    bit_size: 2
    description: I2C2 clock source selection
    name: I2C2SEL
  - bit_offset: 16
    bit_size: 2
    description: I2C3 clock source selection
    name: I2C3SEL
  - bit_offset: 18
    bit_size: 2
    description: Low power timer 1 clock source selection
    name: LPTIM1SEL
  - bit_offset: 20
    bit_size: 2
    description: Low power timer 2 clock source selection
    name: LPTIM2SEL
  - bit_offset: 22
    bit_size: 2
    description: SAI1 clock source selection
    name: SAI1SEL
  - bit_offset: 24
    bit_size: 2
    description: SAI2 clock source selection
    name: SAI2SEL
  - bit_offset: 26
    bit_size: 2
    description: 48 MHz clock source selection
    name: CLK48SEL
  - bit_offset: 28
    bit_size: 2
    description: ADCs clock source selection
    name: ADCSEL
  - bit_offset: 30
    bit_size: 1
    description: SWPMI1 clock source selection
    name: SWPMI1SEL
  - bit_offset: 31
    bit_size: 1
    description: DFSDM clock source selection
    name: DFSDMSEL
fieldset/CCIPR2:
  description: Peripherals independent clock configuration register
  fields:
  - bit_offset: 0
    bit_size: 2
    description: I2C4 clock source selection
    name: I2C4SEL
  - bit_offset: 2
    bit_size: 1
    description: Digital filter for sigma delta modulator kernel clock source selection
    name: DFSDMSEL
  - bit_offset: 3
    bit_size: 2
    description: Digital filter for sigma delta modulator audio clock source selection
    name: ADFSDMSEL
  - bit_offset: 5
    bit_size: 3
    description: SAI1 clock source selection
    name: SAI1SEL
  - bit_offset: 8
    bit_size: 3
    description: SAI2 clock source selection
    name: SAI2SEL
  - bit_offset: 12
    bit_size: 1
    description: clock selection
    name: DSISEL
  - bit_offset: 14
    bit_size: 1
    description: SDMMC clock selection
    name: SDMMCSEL
  - bit_offset: 16
    bit_size: 2
    description: division factor for LTDC clock
    name: PLLSAI2DIVR
  - bit_offset: 20
    bit_size: 2
    description: Octospi clock source selection
    name: OSPISEL
fieldset/CFGR:
  description: Clock configuration register
  fields:
  - bit_offset: 0
    bit_size: 2
    description: System clock switch
    name: SW
  - bit_offset: 2
    bit_size: 2
    description: System clock switch status
    name: SWS
  - bit_offset: 4
    bit_size: 4
    description: AHB prescaler
    name: HPRE
  - bit_offset: 8
    bit_size: 3
    description: PB low-speed prescaler (APB1)
    name: PPRE1
  - bit_offset: 11
    bit_size: 3
    description: APB high-speed prescaler (APB2)
    name: PPRE2
  - bit_offset: 15
    bit_size: 1
    description: Wakeup from Stop and CSS backup clock selection
    name: STOPWUCK
  - bit_offset: 24
    bit_size: 3
    description: Microcontroller clock output
    name: MCOSEL
  - bit_offset: 28
    bit_size: 3
    description: Microcontroller clock output prescaler
    name: MCOPRE
fieldset/CICR:
  description: Clock interrupt clear register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: LSI ready interrupt clear
    name: LSIRDYC
  - bit_offset: 1
    bit_size: 1
    description: LSE ready interrupt clear
    name: LSERDYC
  - bit_offset: 2
    bit_size: 1
    description: MSI ready interrupt clear
    name: MSIRDYC
  - bit_offset: 3
    bit_size: 1
    description: HSI ready interrupt clear
    name: HSIRDYC
  - bit_offset: 4
    bit_size: 1
    description: HSE ready interrupt clear
    name: HSERDYC
  - bit_offset: 5
    bit_size: 1
    description: PLL ready interrupt clear
    name: PLLRDYC
  - bit_offset: 6
    bit_size: 1
    description: PLLSAI1 ready interrupt clear
    name: PLLSAI1RDYC
  - bit_offset: 7
    bit_size: 1
    description: PLLSAI2 ready interrupt clear
    name: PLLSAI2RDYC
  - bit_offset: 8
    bit_size: 1
    description: Clock security system interrupt clear
    name: CSSC
  - bit_offset: 9
    bit_size: 1
    description: LSE Clock security system interrupt clear
    name: LSECSSC
  - bit_offset: 10
    bit_size: 1
    description: HSI48 oscillator ready interrupt clear
    name: HSI48RDYC
fieldset/CIER:
  description: Clock interrupt enable register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: LSI ready interrupt enable
    name: LSIRDYIE
  - bit_offset: 1
    bit_size: 1
    description: LSE ready interrupt enable
    name: LSERDYIE
  - bit_offset: 2
    bit_size: 1
    description: MSI ready interrupt enable
    name: MSIRDYIE
  - bit_offset: 3
    bit_size: 1
    description: HSI ready interrupt enable
    name: HSIRDYIE
  - bit_offset: 4
    bit_size: 1
    description: HSE ready interrupt enable
    name: HSERDYIE
  - bit_offset: 5
    bit_size: 1
    description: PLL ready interrupt enable
    name: PLLRDYIE
  - bit_offset: 6
    bit_size: 1
    description: PLLSAI1 ready interrupt enable
    name: PLLSAI1RDYIE
  - bit_offset: 7
    bit_size: 1
    description: PLLSAI2 ready interrupt enable
    name: PLLSAI2RDYIE
  - bit_offset: 9
    bit_size: 1
    description: LSE clock security system interrupt enable
    name: LSECSSIE
  - bit_offset: 10
    bit_size: 1
    description: HSI48 ready interrupt enable
    name: HSI48RDYIE
fieldset/CIFR:
  description: Clock interrupt flag register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: LSI ready interrupt flag
    name: LSIRDYF
  - bit_offset: 1
    bit_size: 1
    description: LSE ready interrupt flag
    name: LSERDYF
  - bit_offset: 2
    bit_size: 1
    description: MSI ready interrupt flag
    name: MSIRDYF
  - bit_offset: 3
    bit_size: 1
    description: HSI ready interrupt flag
    name: HSIRDYF
  - bit_offset: 4
    bit_size: 1
    description: HSE ready interrupt flag
    name: HSERDYF
  - bit_offset: 5
    bit_size: 1
    description: PLL ready interrupt flag
    name: PLLRDYF
  - bit_offset: 6
    bit_size: 1
    description: PLLSAI1 ready interrupt flag
    name: PLLSAI1RDYF
  - bit_offset: 7
    bit_size: 1
    description: PLLSAI2 ready interrupt flag
    name: PLLSAI2RDYF
  - bit_offset: 8
    bit_size: 1
    description: Clock security system interrupt flag
    name: CSSF
  - bit_offset: 9
    bit_size: 1
    description: LSE Clock security system interrupt flag
    name: LSECSSF
  - bit_offset: 10
    bit_size: 1
    description: HSI48 ready interrupt flag
    name: HSI48RDYF
fieldset/CR:
  description: Clock control register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: MSI clock enable
    name: MSION
  - bit_offset: 1
    bit_size: 1
    description: MSI clock ready flag
    name: MSIRDY
  - bit_offset: 2
    bit_size: 1
    description: MSI clock PLL enable
    name: MSIPLLEN
  - bit_offset: 3
    bit_size: 1
    description: MSI clock range selection
    name: MSIRGSEL
  - bit_offset: 4
    bit_size: 4
    description: MSI clock ranges
    enum: MSIRANGE
    name: MSIRANGE
  - bit_offset: 8
    bit_size: 1
    description: HSI clock enable
    name: HSION
  - bit_offset: 9
    bit_size: 1
    description: HSI always enable for peripheral kernels
    name: HSIKERON
  - bit_offset: 10
    bit_size: 1
    description: HSI clock ready flag
    name: HSIRDY
  - bit_offset: 11
    bit_size: 1
    description: HSI automatic start from Stop
    name: HSIASFS
  - bit_offset: 16
    bit_size: 1
    description: HSE clock enable
    name: HSEON
  - bit_offset: 17
    bit_size: 1
    description: HSE clock ready flag
    name: HSERDY
  - bit_offset: 18
    bit_size: 1
    description: HSE crystal oscillator bypass
    name: HSEBYP
  - bit_offset: 19
    bit_size: 1
    description: Clock security system enable
    name: CSSON
  - bit_offset: 24
    bit_size: 1
    description: Main PLL enable
    name: PLLON
  - bit_offset: 25
    bit_size: 1
    description: Main PLL clock ready flag
    name: PLLRDY
  - bit_offset: 26
    bit_size: 1
    description: SAI1 PLL enable
    name: PLLSAI1ON
  - bit_offset: 27
    bit_size: 1
    description: SAI1 PLL clock ready flag
    name: PLLSAI1RDY
  - bit_offset: 28
    bit_size: 1
    description: SAI2 PLL enable
    name: PLLSAI2ON
  - bit_offset: 29
    bit_size: 1
    description: SAI2 PLL clock ready flag
    name: PLLSAI2RDY
fieldset/CRRCR:
  description: Clock recovery RC register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: HSI48 clock enable
    name: HSI48ON
  - bit_offset: 1
    bit_size: 1
    description: HSI48 clock ready flag
    name: HSI48RDY
  - bit_offset: 7
    bit_size: 9
    description: HSI48 clock calibration
    name: HSI48CAL
fieldset/CSR:
  description: CSR
  fields:
  - bit_offset: 0
    bit_size: 1
    description: LSI oscillator enable
    name: LSION
  - bit_offset: 1
    bit_size: 1
    description: LSI oscillator ready
    name: LSIRDY
  - bit_offset: 8
    bit_size: 4
    description: SI range after Standby mode
    name: MSISRANGE
  - bit_offset: 23
    bit_size: 1
    description: Remove reset flag
    name: RMVF
  - bit_offset: 24
    bit_size: 1
    description: Firewall reset flag
    name: FWRSTF
  - bit_offset: 24
    bit_size: 1
    description: Firewall reset flag
    name: FIREWALLRSTF
  - bit_offset: 25
    bit_size: 1
    description: Option byte loader reset flag
    name: OBLRSTF
  - bit_offset: 26
    bit_size: 1
    description: Pin reset flag
    name: PINRSTF
  - bit_offset: 27
    bit_size: 1
    description: BOR flag
    name: BORRSTF
  - bit_offset: 28
    bit_size: 1
    description: Software reset flag
    name: SFTRSTF
  - bit_offset: 29
    bit_size: 1
    description: Independent window watchdog reset flag
    name: IWDGRSTF
  - bit_offset: 30
    bit_size: 1
    description: Window watchdog reset flag
    name: WWDGRSTF
  - bit_offset: 31
    bit_size: 1
    description: Low-power reset flag
    name: LPWRSTF
fieldset/ICSCR:
  description: Internal clock sources calibration register
  fields:
  - bit_offset: 0
    bit_size: 8
    description: MSI clock calibration
    name: MSICAL
  - bit_offset: 8
    bit_size: 8
    description: MSI clock trimming
    name: MSITRIM
  - bit_offset: 16
    bit_size: 8
    description: HSI clock calibration
    name: HSICAL
  - bit_offset: 24
    bit_size: 7
    description: HSI clock trimming
    name: HSITRIM
fieldset/PLLCFGR:
  description: PLL configuration register
  fields:
  - bit_offset: 0
    bit_size: 2
    description: Main PLL, PLLSAI1 and PLLSAI2 entry clock source
    name: PLLSRC
  - bit_offset: 4
    bit_size: 4
    description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2)
      input clock
    name: PLLM
  - bit_offset: 8
    bit_size: 7
    description: Main PLL multiplication factor for VCO
    name: PLLN
  - bit_offset: 16
    bit_size: 1
    description: Main PLL PLLSAI3CLK output enable
    name: PLLPEN
  - bit_offset: 17
    bit_size: 1
    description: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)
    name: PLLP
  - bit_offset: 20
    bit_size: 1
    description: Main PLL PLLUSB1CLK output enable
    name: PLLQEN
  - bit_offset: 21
    bit_size: 2
    description: Main PLL division factor for PLLUSB1CLK(48 MHz clock)
    name: PLLQ
  - bit_offset: 24
    bit_size: 1
    description: Main PLL PLLCLK output enable
    name: PLLREN
  - bit_offset: 25
    bit_size: 2
    description: Main PLL division factor for PLLCLK (system clock)
    name: PLLR
  - bit_offset: 27
    bit_size: 5
    description: Main PLL division factor for PLLSAI2CLK
    name: PLLPDIV
fieldset/PLLSAI1CFGR:
  description: PLLSAI1 configuration register
  fields:
  - bit_offset: 4
    bit_size: 4
    description: Division factor for PLLSAI1 input clock
    name: PLLSAI1M
  - bit_offset: 8
    bit_size: 7
    description: SAI1PLL multiplication factor for VCO
    name: PLLSAI1N
  - bit_offset: 16
    bit_size: 1
    description: SAI1PLL PLLSAI1CLK output enable
    name: PLLSAI1PEN
  - bit_offset: 17
    bit_size: 1
    description: SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock)
    name: PLLSAI1P
  - bit_offset: 20
    bit_size: 1
    description: SAI1PLL PLLUSB2CLK output enable
    name: PLLSAI1QEN
  - bit_offset: 21
    bit_size: 2
    description: SAI1PLL division factor for PLLUSB2CLK (48 MHz clock)
    name: PLLSAI1Q
  - bit_offset: 24
    bit_size: 1
    description: PLLSAI1 PLLADC1CLK output enable
    name: PLLSAI1REN
  - bit_offset: 25
    bit_size: 2
    description: PLLSAI1 division factor for PLLADC1CLK (ADC clock)
    name: PLLSAI1R
  - bit_offset: 27
    bit_size: 5
    description: PLLSAI1 division factor for PLLSAI1CLK
    name: PLLSAI1PDIV
fieldset/PLLSAI2CFGR:
  description: PLLSAI2 configuration register
  fields:
  - bit_offset: 4
    bit_size: 4
    description: Division factor for PLLSAI2 input clock
    name: PLLSAI2M
  - bit_offset: 8
    bit_size: 7
    description: SAI2PLL multiplication factor for VCO
    name: PLLSAI2N
  - bit_offset: 16
    bit_size: 1
    description: SAI2PLL PLLSAI2CLK output enable
    name: PLLSAI2PEN
  - bit_offset: 17
    bit_size: 1
    description: SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock)
    name: PLLSAI2P
  - bit_offset: 20
    bit_size: 1
    description: PLLSAI2 division factor for PLLDISCLK
    name: PLLSAI2QEN
  - bit_offset: 21
    bit_size: 2
    description: SAI2PLL PLLSAI2CLK output enable
    name: PLLSAI2Q
  - bit_offset: 24
    bit_size: 1
    description: PLLSAI2 PLLADC2CLK output enable
    name: PLLSAI2REN
  - bit_offset: 25
    bit_size: 2
    description: PLLSAI2 division factor for PLLADC2CLK (ADC clock)
    name: PLLSAI2R
  - bit_offset: 27
    bit_size: 5
    description: PLLSAI2 division factor for PLLSAI2CLK
    name: PLLSAI2PDIV