495 lines
12 KiB
YAML
495 lines
12 KiB
YAML
---
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block/SDMMC:
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description: Secure digital input/output interface
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items:
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- name: POWER
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description: power control register
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byte_offset: 0
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fieldset: POWER
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- name: CLKCR
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description: SDI clock control register
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byte_offset: 4
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fieldset: CLKCR
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- name: ARGR
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description: argument register
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byte_offset: 8
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fieldset: ARGR
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- name: CMDR
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description: command register
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byte_offset: 12
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fieldset: CMDR
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- name: RESPCMDR
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description: command response register
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byte_offset: 16
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access: Read
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fieldset: RESPCMDR
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- name: RESPR
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description: response 1..4 register
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array:
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len: 4
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stride: 4
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byte_offset: 20
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access: Read
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fieldset: RESP1R
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- name: DTIMER
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description: data timer register
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byte_offset: 36
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fieldset: DTIMER
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- name: DLENR
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description: data length register
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byte_offset: 40
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fieldset: DLENR
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- name: DCTRL
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description: data control register
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byte_offset: 44
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fieldset: DCTRL
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- name: DCNTR
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description: data counter register
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byte_offset: 48
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access: Read
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fieldset: DCNTR
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- name: STAR
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description: status register
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byte_offset: 52
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access: Read
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fieldset: STAR
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- name: ICR
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description: interrupt clear register
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byte_offset: 56
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fieldset: ICR
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- name: MASKR
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description: mask register
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byte_offset: 60
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fieldset: MASKR
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- name: FIFOCNT
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description: FIFO counter register
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byte_offset: 72
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access: Read
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fieldset: FIFOCNT
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- name: FIFOR
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description: data FIFO register
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byte_offset: 128
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fieldset: FIFOR
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fieldset/ARGR:
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description: argument register
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fields:
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- name: CMDARG
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description: Command argument
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bit_offset: 0
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bit_size: 32
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fieldset/CLKCR:
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description: SDI clock control register
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fields:
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- name: CLKDIV
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description: Clock divide factor
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bit_offset: 0
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bit_size: 8
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- name: CLKEN
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description: Clock enable bit
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bit_offset: 8
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bit_size: 1
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- name: PWRSAV
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description: Power saving configuration bit
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bit_offset: 9
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bit_size: 1
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- name: BYPASS
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description: Clock divider bypass enable bit
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bit_offset: 10
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bit_size: 1
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- name: WIDBUS
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description: Wide bus mode enable bit
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bit_offset: 11
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bit_size: 2
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- name: NEGEDGE
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description: SDIO_CK dephasing selection bit
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bit_offset: 13
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bit_size: 1
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- name: HWFC_EN
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description: HW Flow Control enable
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bit_offset: 14
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bit_size: 1
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fieldset/CMDR:
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description: command register
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fields:
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- name: CMDINDEX
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description: Command index
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bit_offset: 0
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bit_size: 6
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- name: WAITRESP
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description: Wait for response bits
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bit_offset: 6
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bit_size: 2
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- name: WAITINT
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description: CPSM waits for interrupt request
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bit_offset: 8
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bit_size: 1
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- name: WAITPEND
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description: CPSM Waits for ends of data transfer (CmdPend internal signal)
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bit_offset: 9
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bit_size: 1
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- name: CPSMEN
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description: Command path state machine (CPSM) Enable bit
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bit_offset: 10
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bit_size: 1
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- name: SDIOSuspend
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description: SD I/O suspend command
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bit_offset: 11
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bit_size: 1
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fieldset/DCNTR:
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description: data counter register
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fields:
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- name: DATACOUNT
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description: Data count value
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bit_offset: 0
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bit_size: 25
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fieldset/DCTRL:
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description: data control register
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fields:
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- name: DTEN
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description: DTEN
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bit_offset: 0
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bit_size: 1
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- name: DTDIR
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description: Data transfer direction selection
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bit_offset: 1
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bit_size: 1
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- name: DTMODE
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description: "Data transfer mode selection 1: Stream or SDIO multibyte data transfer"
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bit_offset: 2
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bit_size: 1
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- name: DMAEN
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description: DMA enable bit
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bit_offset: 3
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bit_size: 1
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- name: DBLOCKSIZE
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description: Data block size
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bit_offset: 4
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bit_size: 4
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- name: RWSTART
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description: Read wait start
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bit_offset: 8
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bit_size: 1
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- name: RWSTOP
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description: Read wait stop
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bit_offset: 9
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bit_size: 1
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- name: RWMOD
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description: Read wait mode
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bit_offset: 10
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bit_size: 1
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- name: SDIOEN
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description: SD I/O enable functions
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bit_offset: 11
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bit_size: 1
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fieldset/DLENR:
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description: data length register
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fields:
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- name: DATALENGTH
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description: Data length value
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bit_offset: 0
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bit_size: 25
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fieldset/DTIMER:
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description: data timer register
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fields:
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- name: DATATIME
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description: Data timeout period
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bit_offset: 0
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bit_size: 32
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fieldset/FIFOCNT:
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description: FIFO counter register
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fields:
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- name: FIFOCOUNT
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description: Remaining number of words to be written to or read from the FIFO
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bit_offset: 0
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bit_size: 24
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fieldset/FIFOR:
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description: data FIFO register
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fields:
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- name: FIFOData
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description: Receive and transmit FIFO data
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bit_offset: 0
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bit_size: 32
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fieldset/ICR:
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description: interrupt clear register
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fields:
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- name: CCRCFAILC
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description: CCRCFAIL flag clear bit
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bit_offset: 0
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bit_size: 1
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- name: DCRCFAILC
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description: DCRCFAIL flag clear bit
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bit_offset: 1
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bit_size: 1
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- name: CTIMEOUTC
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description: CTIMEOUT flag clear bit
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bit_offset: 2
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bit_size: 1
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- name: DTIMEOUTC
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description: DTIMEOUT flag clear bit
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bit_offset: 3
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bit_size: 1
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- name: TXUNDERRC
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description: TXUNDERR flag clear bit
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bit_offset: 4
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bit_size: 1
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- name: RXOVERRC
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description: RXOVERR flag clear bit
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bit_offset: 5
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bit_size: 1
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- name: CMDRENDC
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description: CMDREND flag clear bit
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bit_offset: 6
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bit_size: 1
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- name: CMDSENTC
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description: CMDSENT flag clear bit
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bit_offset: 7
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bit_size: 1
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- name: DATAENDC
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description: DATAEND flag clear bit
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bit_offset: 8
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bit_size: 1
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- name: STBITERRC
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description: STBITERR flag clear bit
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bit_offset: 9
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bit_size: 1
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- name: DBCKENDC
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description: DBCKEND flag clear bit
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bit_offset: 10
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bit_size: 1
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- name: SDIOITC
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description: SDIOIT flag clear bit
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bit_offset: 22
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bit_size: 1
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fieldset/MASKR:
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description: mask register
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fields:
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- name: CCRCFAILIE
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description: Command CRC fail interrupt enable
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bit_offset: 0
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bit_size: 1
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- name: DCRCFAILIE
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description: Data CRC fail interrupt enable
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bit_offset: 1
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bit_size: 1
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- name: CTIMEOUTIE
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description: Command timeout interrupt enable
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bit_offset: 2
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bit_size: 1
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- name: DTIMEOUTIE
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description: Data timeout interrupt enable
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bit_offset: 3
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bit_size: 1
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- name: TXUNDERRIE
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description: Tx FIFO underrun error interrupt enable
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bit_offset: 4
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bit_size: 1
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- name: RXOVERRIE
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description: Rx FIFO overrun error interrupt enable
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bit_offset: 5
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bit_size: 1
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- name: CMDRENDIE
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description: Command response received interrupt enable
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bit_offset: 6
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bit_size: 1
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- name: CMDSENTIE
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description: Command sent interrupt enable
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bit_offset: 7
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bit_size: 1
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- name: DATAENDIE
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description: Data end interrupt enable
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bit_offset: 8
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bit_size: 1
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- name: STBITERRE
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description: STBITERR interrupt enable
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bit_offset: 9
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bit_size: 1
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- name: DBCKENDIE
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description: Data block end interrupt enable
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bit_offset: 10
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bit_size: 1
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- name: CMDACTIE
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description: Command acting interrupt enable
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bit_offset: 11
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bit_size: 1
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- name: TXACTIE
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description: Data transmit acting interrupt enable
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bit_offset: 12
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bit_size: 1
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- name: RXACTIE
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description: Data receive acting interrupt enable
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bit_offset: 13
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bit_size: 1
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- name: TXFIFOHEIE
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description: Tx FIFO half empty interrupt enable
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bit_offset: 14
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bit_size: 1
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- name: RXFIFOHFIE
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description: Rx FIFO half full interrupt enable
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bit_offset: 15
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bit_size: 1
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- name: TXFIFOFIE
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description: Tx FIFO full interrupt enable
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bit_offset: 16
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bit_size: 1
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- name: RXFIFOFIE
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description: Rx FIFO full interrupt enable
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bit_offset: 17
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bit_size: 1
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- name: TXFIFOEIE
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description: Tx FIFO empty interrupt enable
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bit_offset: 18
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bit_size: 1
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- name: RXFIFOEIE
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description: Rx FIFO empty interrupt enable
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bit_offset: 19
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bit_size: 1
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- name: TXDAVLIE
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description: Data available in Tx FIFO interrupt enable
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bit_offset: 20
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bit_size: 1
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- name: RXDAVLIE
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description: Data available in Rx FIFO interrupt enable
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bit_offset: 21
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bit_size: 1
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- name: SDIOITIE
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description: SDIO mode interrupt received interrupt enable
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bit_offset: 22
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bit_size: 1
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fieldset/POWER:
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description: power control register
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fields:
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- name: PWRCTRL
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description: PWRCTRL
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bit_offset: 0
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bit_size: 2
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fieldset/RESP1R:
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description: response 1..4 register
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fields:
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- name: CARDSTATUS
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description: see Table 132
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bit_offset: 0
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bit_size: 32
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fieldset/RESP2R:
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description: response 1..4 register
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fields:
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- name: CARDSTATUS
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description: see Table 132
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bit_offset: 0
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bit_size: 32
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fieldset/RESP3R:
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description: response 1..4 register
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fields:
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- name: CARDSTATUS
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description: see Table 132
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bit_offset: 0
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bit_size: 32
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fieldset/RESP4R:
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description: response 1..4 register
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fields:
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- name: CARDSTATUS
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description: see Table 132
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bit_offset: 0
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bit_size: 32
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fieldset/RESPCMDR:
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description: command response register
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fields:
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- name: RESPCMD
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description: Response command index
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bit_offset: 0
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bit_size: 6
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fieldset/STAR:
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description: status register
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fields:
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- name: CCRCFAIL
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description: Command response received (CRC check failed)
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bit_offset: 0
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bit_size: 1
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- name: DCRCFAIL
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description: Data block sent/received (CRC check failed)
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bit_offset: 1
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bit_size: 1
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- name: CTIMEOUT
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description: Command response timeout
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bit_offset: 2
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bit_size: 1
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- name: DTIMEOUT
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description: Data timeout
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bit_offset: 3
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bit_size: 1
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- name: TXUNDERR
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description: Transmit FIFO underrun error
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bit_offset: 4
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bit_size: 1
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- name: RXOVERR
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description: Received FIFO overrun error
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bit_offset: 5
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bit_size: 1
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- name: CMDREND
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description: Command response received (CRC check passed)
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bit_offset: 6
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bit_size: 1
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- name: CMDSENT
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description: Command sent (no response required)
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bit_offset: 7
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bit_size: 1
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- name: DATAEND
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description: "Data end (data counter, SDIDCOUNT, is zero)"
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bit_offset: 8
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bit_size: 1
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- name: STBITERR
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description: " Start bit not detected on all data signals in wide bus mode"
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bit_offset: 9
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bit_size: 1
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- name: DBCKEND
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description: Data block sent/received (CRC check passed)
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bit_offset: 10
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bit_size: 1
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- name: CMDACT
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description: Command transfer in progress
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bit_offset: 11
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bit_size: 1
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- name: TXACT
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description: Data transmit in progress
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bit_offset: 12
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bit_size: 1
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- name: RXACT
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description: Data receive in progress
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bit_offset: 13
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bit_size: 1
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- name: TXFIFOHE
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description: "Transmit FIFO half empty: at least 8 words can be written into the FIFO"
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bit_offset: 14
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bit_size: 1
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- name: RXFIFOHF
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description: "Receive FIFO half full: there are at least 8 words in the FIFO"
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bit_offset: 15
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bit_size: 1
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- name: TXFIFOF
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description: Transmit FIFO full
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bit_offset: 16
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bit_size: 1
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- name: RXFIFOF
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description: Receive FIFO full
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bit_offset: 17
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bit_size: 1
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- name: TXFIFOE
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description: Transmit FIFO empty
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bit_offset: 18
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bit_size: 1
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- name: RXFIFOE
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description: Receive FIFO empty
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bit_offset: 19
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bit_size: 1
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- name: TXDAVL
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description: Data available in transmit FIFO
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bit_offset: 20
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bit_size: 1
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- name: RXDAVL
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description: Data available in receive FIFO
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bit_offset: 21
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bit_size: 1
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- name: SDIOIT
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description: SDIO interrupt received
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bit_offset: 22
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bit_size: 1
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