141 lines
4.4 KiB
YAML
141 lines
4.4 KiB
YAML
block/ADC_COMMON:
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description: ADC common registers
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items:
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- name: CCR
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description: common control register
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byte_offset: 8
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fieldset: CCR
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- name: HWCFGR0
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description: hardware configuration register
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byte_offset: 240
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fieldset: HWCFGR0
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- name: VERR
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description: version register
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byte_offset: 244
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fieldset: VERR
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- name: IPDR
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description: identification register
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byte_offset: 248
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- name: SIDR
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description: size identification register
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byte_offset: 252
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fieldset/CCR:
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description: common control register
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fields:
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- name: CKMODE
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description: 'ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).'
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bit_offset: 16
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bit_size: 2
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enum: CKMODE
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- name: PRESC
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description: 'ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. other: reserved Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00.'
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bit_offset: 18
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bit_size: 4
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enum: PRESC
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- name: VREFEN
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description: VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT channel
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bit_offset: 22
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bit_size: 1
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- name: TSEN
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description: VSENSE enable This bit is set and cleared by software to control VSENSE
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bit_offset: 23
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bit_size: 1
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- name: VBATEN
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description: VBAT enable This bit is set and cleared by software to control
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bit_offset: 24
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bit_size: 1
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fieldset/HWCFGR0:
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description: hardware configuration register
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fields:
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- name: ADCNUM
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description: Number of ADCs implemented
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bit_offset: 0
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bit_size: 4
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- name: MULPIPE
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description: Number of pipeline stages
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bit_offset: 4
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bit_size: 4
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- name: OPBITS
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description: 'Number of option bits 0002: 2 option bits implemented in the ADC option register (ADC_OR) at address offset 0xC8.'
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bit_offset: 8
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bit_size: 4
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- name: IDLEVALUE
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description: Idle value for non-selected channels
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bit_offset: 12
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bit_size: 4
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enum: IDLEVALUE
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fieldset/VERR:
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description: version register
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fields:
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- name: MINREV
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description: 'Minor revision These bits returns the ADC IP minor revision 0002: Major revision = X.2.'
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bit_offset: 0
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bit_size: 4
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- name: MAJREV
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description: Major revision These bits returns the ADC IP major revision
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bit_offset: 4
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bit_size: 4
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enum/CKMODE:
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bit_size: 2
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variants:
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- name: Asynchronous
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description: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock
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value: 0
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- name: SyncDiv1
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description: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck
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value: 1
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- name: SyncDiv2
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description: Use AHB clock rcc_hclk3 divided by 2
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value: 2
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- name: SyncDiv4
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description: Use AHB clock rcc_hclk3 divided by 4
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value: 3
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enum/IDLEVALUE:
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bit_size: 4
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variants:
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- name: H13
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description: Dummy channel selection is 0x13
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value: 0
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- name: H1F
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description: Dummy channel selection is 0x1F
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value: 1
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enum/PRESC:
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bit_size: 4
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variants:
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- name: Div1
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description: adc_ker_ck_input not divided
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value: 0
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- name: Div2
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description: adc_ker_ck_input divided by 2
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value: 1
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- name: Div4
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description: adc_ker_ck_input divided by 4
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value: 2
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- name: Div6
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description: adc_ker_ck_input divided by 6
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value: 3
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- name: Div8
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description: adc_ker_ck_input divided by 8
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value: 4
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- name: Div10
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description: adc_ker_ck_input divided by 10
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value: 5
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- name: Div12
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description: adc_ker_ck_input divided by 12
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value: 6
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- name: Div16
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description: adc_ker_ck_input divided by 16
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value: 7
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- name: Div32
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description: adc_ker_ck_input divided by 32
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value: 8
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- name: Div64
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description: adc_ker_ck_input divided by 64
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value: 9
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- name: Div128
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description: adc_ker_ck_input divided by 128
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value: 10
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- name: Div256
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description: adc_ker_ck_input divided by 256
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value: 11
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