276 lines
3.9 KiB
YAML
276 lines
3.9 KiB
YAML
PA0:
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CM4_EVENTOUT: 15
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COMP1_OUT: 12
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DEBUG_PWR-REGLP1S: 13
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I2C3_SMBA: 4
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I2S_CKIN: 5
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TIM2_CH1: 1
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TIM2_ETR: 14
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USART2_CTS: 7
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USART2_NSS: 7
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PA1:
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CM4_EVENTOUT: 15
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DEBUG_PWR-REGLP2S: 13
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I2C1_SMBA: 4
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LPTIM3_OUT: 3
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LPUART1_RTS: 8
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SPI1_SCK: 5
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TIM2_CH2: 1
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USART2_DE: 7
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USART2_RTS: 7
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PA10:
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CM4_EVENTOUT: 15
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DEBUG_RF-HSE32RDY: 13
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I2C1_SDA: 4
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I2S2_SD: 5
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RTC_REFIN: 0
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SPI2_MOSI: 5
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TIM17_BKIN: 14
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TIM1_CH3: 1
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USART1_RX: 7
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PA11:
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CM4_EVENTOUT: 15
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DEBUG_RF-NRESET: 13
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I2C2_SDA: 4
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LPTIM3_ETR: 3
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SPI1_MISO: 5
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TIM1_BKIN2: 12
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TIM1_CH4: 1
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USART1_CTS: 7
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USART1_NSS: 7
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PA12:
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CM4_EVENTOUT: 15
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I2C2_SCL: 4
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LPTIM3_IN1: 3
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RF_BUSY: 6
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SPI1_MOSI: 5
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TIM1_ETR: 1
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USART1_DE: 7
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USART1_RTS: 7
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PA13:
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CM4_EVENTOUT: 15
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DEBUG_JTMS-SWDIO: 0
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I2C2_SMBA: 4
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IR_OUT: 8
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PA14:
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CM4_EVENTOUT: 15
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DEBUG_JTCK-SWCLK: 0
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I2C1_SMBA: 4
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LPTIM1_OUT: 1
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PA15:
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CM4_EVENTOUT: 15
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DEBUG_JTDI: 0
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I2C2_SDA: 4
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SPI1_NSS: 5
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TIM2_CH1: 1
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TIM2_ETR: 2
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PA2:
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CM4_EVENTOUT: 15
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COMP2_OUT: 12
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DEBUG_PWR-LDORDY: 13
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LPUART1_TX: 8
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RCC_LSCO: 0
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TIM2_CH3: 1
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USART2_TX: 7
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PA3:
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CM4_EVENTOUT: 15
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I2S2_MCK: 5
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LPUART1_RX: 8
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TIM2_CH4: 1
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USART2_RX: 7
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PA4:
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CM4_EVENTOUT: 15
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DEBUG_SUBGHZSPI-NSSOUT: 13
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LPTIM1_OUT: 1
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LPTIM2_OUT: 14
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SPI1_NSS: 5
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USART2_CK: 7
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PA5:
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CM4_EVENTOUT: 15
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DEBUG_SUBGHZSPI-SCKOUT: 13
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LPTIM2_ETR: 14
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SPI1_SCK: 5
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SPI2_MISO: 3
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TIM2_CH1: 1
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TIM2_ETR: 2
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PA6:
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CM4_EVENTOUT: 15
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DEBUG_SUBGHZSPI-MISOOUT: 13
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I2C2_SMBA: 4
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LPUART1_CTS: 8
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SPI1_MISO: 5
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TIM16_CH1: 14
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TIM1_BKIN: 12
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PA7:
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CM4_EVENTOUT: 15
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COMP2_OUT: 12
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DEBUG_SUBGHZSPI-MOSIOUT: 13
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I2C3_SCL: 4
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SPI1_MOSI: 5
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TIM17_CH1: 14
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TIM1_CH1N: 1
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PA8:
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CM4_EVENTOUT: 15
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I2S2_CK: 5
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LPTIM2_OUT: 14
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RCC_MCO: 0
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SPI2_SCK: 5
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TIM1_CH1: 1
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USART1_CK: 7
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PA9:
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CM4_EVENTOUT: 15
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I2C1_SCL: 4
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I2S2_CK: 5
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I2S2_WS: 3
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SPI2_NSS: 3
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SPI2_SCK: 5
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TIM1_CH2: 1
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USART1_TX: 7
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PB0:
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CM4_EVENTOUT: 15
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COMP1_OUT: 12
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PB1:
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CM4_EVENTOUT: 15
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LPTIM2_IN1: 14
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LPUART1_DE: 8
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LPUART1_RTS: 8
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PB10:
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CM4_EVENTOUT: 15
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COMP1_OUT: 12
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I2C3_SCL: 4
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I2S2_CK: 5
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LPUART1_RX: 8
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SPI2_SCK: 5
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TIM2_CH3: 1
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PB11:
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CM4_EVENTOUT: 15
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COMP2_OUT: 12
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I2C3_SDA: 4
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LPUART1_TX: 8
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TIM2_CH4: 1
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PB12:
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CM4_EVENTOUT: 15
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I2C3_SMBA: 4
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I2S2_WS: 5
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LPUART1_DE: 8
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LPUART1_RTS: 8
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SPI2_NSS: 5
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TIM1_BKIN: 3
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PB13:
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CM4_EVENTOUT: 15
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I2C3_SCL: 4
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I2S2_CK: 5
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LPUART1_CTS: 8
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SPI2_SCK: 5
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TIM1_CH1N: 1
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PB14:
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CM4_EVENTOUT: 15
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I2C3_SDA: 4
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I2S2_MCK: 3
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SPI2_MISO: 5
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TIM1_CH2N: 1
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PB15:
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CM4_EVENTOUT: 15
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I2C2_SCL: 4
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I2S2_SD: 5
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SPI2_MOSI: 5
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TIM1_CH3N: 1
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PB2:
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CM4_EVENTOUT: 15
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DEBUG_RF-SMPSRDY: 13
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I2C3_SMBA: 4
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LPTIM1_OUT: 1
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SPI1_NSS: 5
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PB3:
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CM4_EVENTOUT: 15
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DEBUG_JTDO-SWO: 0
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DEBUG_RF-DTB1: 13
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RF_IRQ0: 6
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SPI1_SCK: 5
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TIM2_CH2: 1
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USART1_DE: 7
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USART1_RTS: 7
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PB4:
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CM4_EVENTOUT: 15
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DEBUG_RF-LDORDY: 13
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I2C3_SDA: 4
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SPI1_MISO: 5
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SYS_JTRST: 0
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TIM17_BKIN: 14
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USART1_CTS: 7
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USART1_NSS: 7
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PB5:
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CM4_EVENTOUT: 15
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COMP2_OUT: 12
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I2C1_SMBA: 4
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LPTIM1_IN1: 1
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RF_IRQ1: 6
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SPI1_MOSI: 5
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TIM16_BKIN: 14
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USART1_CK: 7
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PB6:
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CM4_EVENTOUT: 15
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I2C1_SCL: 4
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LPTIM1_ETR: 1
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TIM16_CH1N: 14
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USART1_TX: 7
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PB7:
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CM4_EVENTOUT: 15
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I2C1_SDA: 4
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LPTIM1_IN2: 1
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TIM17_CH1N: 14
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TIM1_BKIN: 3
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USART1_RX: 7
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PB8:
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CM4_EVENTOUT: 15
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I2C1_SCL: 4
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RF_IRQ2: 6
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TIM16_CH1: 14
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TIM1_CH2N: 1
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PB9:
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CM4_EVENTOUT: 15
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I2C1_SDA: 4
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I2S2_WS: 5
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IR_OUT: 8
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SPI2_NSS: 5
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TIM17_CH1: 14
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TIM1_CH3N: 1
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PC0:
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CM4_EVENTOUT: 15
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I2C3_SCL: 4
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LPTIM1_IN1: 1
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LPTIM2_IN1: 14
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LPUART1_RX: 8
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PC1:
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CM4_EVENTOUT: 15
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I2C3_SDA: 4
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I2S2_SD: 3
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LPTIM1_OUT: 1
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LPUART1_TX: 8
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SPI2_MOSI: 3
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PC13:
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CM4_EVENTOUT: 15
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PC14:
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CM4_EVENTOUT: 15
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PC15:
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CM4_EVENTOUT: 15
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PC2:
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CM4_EVENTOUT: 15
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LPTIM1_IN2: 1
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SPI2_MISO: 5
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PC3:
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CM4_EVENTOUT: 15
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I2S2_SD: 5
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LPTIM1_ETR: 1
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LPTIM2_ETR: 14
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SPI2_MOSI: 5
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PC4:
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CM4_EVENTOUT: 15
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PC5:
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CM4_EVENTOUT: 15
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PC6:
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CM4_EVENTOUT: 15
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I2S2_MCK: 5
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PH3:
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CM4_EVENTOUT: 15
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