Torin Cooper-Bennun 27c71ac451 fdcan: generate register blocks for message RAM ...

this is a special case, as most data sources don't mention this as a
separate peripheral at all, and those that do don't handle the offsets
in the case of multiple FDCANS

H7 chips have a single 10KB block shared between all FDCANs

2023-11-21 10:45:51 +00:00

..

chips.rs

fdcan: generate register blocks for message RAM

2023-11-21 10:45:51 +00:00

dma.rs

Add STM32WBA support.

2023-09-16 02:34:03 +02:00

docs.rs

New repo structure: includes stm32-metapac, doesn't commit generated files.

2023-03-20 01:56:23 +01:00

gpio_af.rs

first working state with bad sorting

2023-09-14 16:26:53 +02:00

header.rs

fdcan: generate register blocks for message RAM

2023-11-21 10:45:51 +00:00

interrupts.rs

Fix G0 USB interrupts.

2023-11-18 01:39:07 +01:00

main.rs

Add H5, and newer U5s.

2023-03-27 12:17:53 +02:00

memory.rs

Switch to bender CI

2023-06-28 17:44:05 +02:00

rcc.rs

rcc: fix FDCAN: multiple FDCANs share the same RCC fields

2023-11-21 10:45:51 +00:00

registers.rs

data-gen: add some yaml validation

2023-07-01 17:18:40 -05:00