410 lines
15 KiB
YAML
410 lines
15 KiB
YAML
block/SYSCFG:
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description: SBS register block
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items:
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- name: HDPLCR
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description: SBS temporal isolation control register
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byte_offset: 16
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fieldset: HDPLCR
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- name: HDPLSR
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description: SBS temporal isolation status register
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byte_offset: 20
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fieldset: HDPLSR
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- name: NEXTHDPLCR
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description: SBS next HDPL control register
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byte_offset: 24
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fieldset: NEXTHDPLCR
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- name: DBGCR
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description: SBS debug control register
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byte_offset: 32
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fieldset: DBGCR
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- name: DBGLOCKR
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description: SBS debug lock register
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byte_offset: 36
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fieldset: DBGLOCKR
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- name: RSSCMDR
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description: SBS RSS command register
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byte_offset: 52
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fieldset: RSSCMDR
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- name: EPOCHSELCR
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description: SBS EPOCH selection control register
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byte_offset: 160
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fieldset: EPOCHSELCR
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- name: SECCFGR
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description: SBS security mode configuration control register
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byte_offset: 192
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fieldset: SECCFGR
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- name: PMCR
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description: SBS product mode and configuration register
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byte_offset: 256
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fieldset: PMCR
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- name: FPUIMR
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description: SBS FPU interrupt mask register
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byte_offset: 260
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fieldset: FPUIMR
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- name: MESR
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description: SBS memory erase status register
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byte_offset: 264
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fieldset: MESR
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- name: CCCSR
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description: SBS compensation cell for I/Os control and status register
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byte_offset: 272
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fieldset: CCCSR
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- name: CCVALR
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description: SBS compensation cell for I/Os value register
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byte_offset: 276
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fieldset: CCVALR
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- name: CCSWCR
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description: SBS compensation cell for I/Os software code register
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byte_offset: 280
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fieldset: CCSWCR
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- name: CFGR2
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description: SBS Class B register
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byte_offset: 288
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fieldset: CFGR2
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- name: CNSLCKR
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description: SBS CPU non-secure lock register
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byte_offset: 324
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fieldset: CNSLCKR
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- name: CSLCKR
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description: SBS CPU secure lock register
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byte_offset: 328
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fieldset: CSLCKR
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- name: ECCNMIR
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description: SBS flift ECC NMI mask register
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byte_offset: 332
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fieldset: ECCNMIR
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fieldset/CCCSR:
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description: SBS compensation cell for I/Os control and status register
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fields:
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- name: EN
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description: "enable compensation cell for VDDIO power rail\r This bit enables the I/O compensation cell."
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bit_offset: 0
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bit_size: 1
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array:
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len: 2
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stride: 2
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- name: CS
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description: "code selection for VDDIO power rail (reset value set to 1)\r This bit selects the code to be applied for the I/O compensation cell."
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bit_offset: 1
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bit_size: 1
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array:
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len: 2
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stride: 2
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enum: CS
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- name: RDY
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description: "VDDIO compensation cell ready flag\r This bit provides the status of the compensation cell."
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bit_offset: 8
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bit_size: 1
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array:
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len: 2
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stride: 1
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fieldset/CCSWCR:
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description: SBS compensation cell for I/Os software code register
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fields:
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- name: SW_ANSRC1
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description: "NMOS compensation code for VDD power rails\r This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR."
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bit_offset: 0
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bit_size: 4
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- name: SW_APSRC1
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description: "PMOS compensation code for the VDD power rails\r This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR."
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bit_offset: 4
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bit_size: 4
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- name: SW_ANSRC2
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description: "NMOS compensation code for VDDIO power rails\r This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR."
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bit_offset: 8
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bit_size: 4
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- name: SW_APSRC2
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description: "PMOS compensation code for the VDDIO power rails\r This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR."
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bit_offset: 12
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bit_size: 4
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fieldset/CCVALR:
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description: SBS compensation cell for I/Os value register
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fields:
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- name: ANSRC1
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description: "compensation value for the NMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range."
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bit_offset: 0
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bit_size: 4
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- name: APSRC1
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description: "compensation value for the PMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range."
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bit_offset: 4
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bit_size: 4
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- name: ANSRC2
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description: "Compensation value for the NMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range."
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bit_offset: 8
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bit_size: 4
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- name: APSRC2
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description: "compensation value for the PMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range."
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bit_offset: 12
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bit_size: 4
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fieldset/CFGR2:
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description: SBS Class B register
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fields:
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- name: CLL
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description: "core lockup lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the lockup (HardFault) output of Cortex-M33 with TIM1/8/15/16/17 break inputs."
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bit_offset: 0
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bit_size: 1
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- name: SEL
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description: "SRAM ECC error lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM double ECC error signal with break input of TIM1/8/15/16/17."
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bit_offset: 1
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bit_size: 1
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- name: PVDL
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description: "PVD lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection with TIM1/8/15/16/17 break inputs."
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bit_offset: 2
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bit_size: 1
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- name: ECCL
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description: "ECC lock\r This bit is set and cleared by software. It can be used to enable and lock the Flash memory double ECC error with break input of TIM1/8/15/6/17."
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bit_offset: 3
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bit_size: 1
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fieldset/CNSLCKR:
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description: SBS CPU non-secure lock register
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fields:
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- name: LOCKNSVTOR
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description: "VTOR_NS register lock\r This bit is set by software and cleared only by a system reset."
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bit_offset: 0
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bit_size: 1
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- name: LOCKNSMPU
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description: "non-secure MPU register lock\r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to non-secure MPU_CTRL_NS, MPU_RNR_NS and MPU_RBAR_NS registers."
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bit_offset: 1
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bit_size: 1
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fieldset/CSLCKR:
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description: SBS CPU secure lock register
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fields:
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- name: LOCKSVTAIRCR
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description: "VTOR_S and AIRCR register lock\r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to VTOR_S register, PRIS and BFHFNMINS bits in the AIRCR register."
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bit_offset: 0
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bit_size: 1
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- name: LOCKSMPU
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description: "secure MPU registers lock\r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to secure MPU_CTRL, MPU_RNR and MPU_RBAR registers."
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bit_offset: 1
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bit_size: 1
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- name: LOCKSAU
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description: "SAU registers lock\r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers."
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bit_offset: 2
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bit_size: 1
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fieldset/DBGCR:
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description: SBS debug control register
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fields:
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- name: AP_UNLOCK
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description: "access port unlock\r Write 0xB4 to this bitfield to open the device access port."
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bit_offset: 0
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bit_size: 8
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- name: DBG_UNLOCK
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description: "debug unlock when DBG_AUTH_HDPL is reached\r Write 0xB4 to this bitfield to open the debug when HDPL in SBS_HDPLSR equals to DBG_AUTH_HDPL in this register."
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bit_offset: 8
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bit_size: 8
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- name: DBG_AUTH_HDPL
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description: "authenticated debug temporal isolation level\r Writing to this bitfield defines at which HDPL the authenticated debug opens.\r Note: Writing any other values is ignored. Reading any other value means the debug never opens."
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bit_offset: 16
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bit_size: 8
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enum: DBG_AUTH_HDPL
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- name: DBG_AUTH_SEC
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description: "control debug opening secure/non-secure\r Write 0xB4 to this bitfield to open debug for secure and non-secure.\r Writing any other values only open non-secure."
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bit_offset: 24
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bit_size: 8
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fieldset/DBGLOCKR:
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description: SBS debug lock register
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fields:
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- name: DBGCFG_LOCK
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description: "debug configuration lock\r Reading this bitfield returns 0x6A if the bitfield value is different from 0xB4.\r 0xC3 is the recommended value to lock the debug configuration using this bitfield.\r Other: Writes to SBS_DBGCR ignored"
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bit_offset: 0
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bit_size: 8
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enum: DBGCFG_LOCK
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fieldset/ECCNMIR:
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description: SBS flift ECC NMI mask register
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fields:
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- name: ECCNMI_MASK_EN
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description: NMI behavior setup when a double ECC error occurs on flitf data part
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bit_offset: 0
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bit_size: 1
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fieldset/EPOCHSELCR:
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description: SBS EPOCH selection control register
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fields:
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- name: EPOCH_SEL
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description: "select EPOCH value to be sent to the SAES\r 1x: EPOCH forced to zero (value used to retrieve PUF reference value at boot time)"
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bit_offset: 0
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bit_size: 2
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enum: EPOCH_SEL
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fieldset/FPUIMR:
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description: SBS FPU interrupt mask register
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fields:
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- name: FPU_IE
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description: "FPU interrupt enable\r Set and cleared by software to enable the Cortex-M33 FPU interrupts\r FPU_IE[5]: inexact interrupt enable (interrupt disabled at reset)\r FPU_IE[4]: input abnormal interrupt enable\r FPU_IE[3]: overflow interrupt enable\r FPU_IE[2]: underflow interrupt enable\r FPU_IE[1]: divide-by-zero interrupt enable\r FPU_IE[0]: invalid operation interrupt enable"
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bit_offset: 0
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bit_size: 6
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fieldset/HDPLCR:
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description: SBS temporal isolation control register
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fields:
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- name: INCR_HDPL
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description: "increment HDPL value\r Other: all other values allow a HDPL level increment."
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bit_offset: 0
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bit_size: 8
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enum: INCR_HDPL
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fieldset/HDPLSR:
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description: SBS temporal isolation status register
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fields:
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- name: HDPL
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description: "temporal isolation level\r This bitfield returns the current temporal isolation level."
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bit_offset: 0
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bit_size: 8
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enum: HDPL
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fieldset/MESR:
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description: SBS memory erase status register
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fields:
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- name: MCLR
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description: "erase after reset status\r This bit shows the status of the protection for SRAM2, BKPRAM, ICACHE, DCACHE, ICACHE and PKA. It is set by hardware and reset by software"
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bit_offset: 0
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bit_size: 1
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- name: IPMEE
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description: "end-of-erase status for ICACHE and PKA RAM\r This bit shows the status of the protection for ICACHE and PKA. It is set by hardware and reset by software."
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bit_offset: 16
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bit_size: 1
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fieldset/NEXTHDPLCR:
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description: SBS next HDPL control register
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fields:
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- name: NEXTHDPL
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description: "index to point to a higher HDPL than the current one\r Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas (OBK-HDPL = HDPL + NEXTHDPL). See for more details."
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bit_offset: 0
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bit_size: 2
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fieldset/PMCR:
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description: SBS product mode and configuration register
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fields:
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- name: BOOSTEN
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description: "booster enable\r Set this bit to reduce the total harmonic distortion of the analog switch when the processor supply is below 2.7 V. The booster can be activated to guaranty AC performance on analog switch when the supply is below 2.7 V. When the booster is activated, the analog switch performances are the same as with the full voltage range."
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bit_offset: 8
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bit_size: 1
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- name: BOOSTVDDSEL
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description: "booster VDD selection\r Note: Booster must not be used when VDDA < 2.7 V, but VDD > 2.7 V (add current consumption).\r When both VDD < 2.7 V and VDDA < 2.7 V, booster is needed to get full AC performances from I/O analog switches."
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bit_offset: 9
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bit_size: 1
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- name: PB6_FMPLUS
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description: Fast-mode Plus command on PB(6)
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bit_offset: 16
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bit_size: 1
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- name: PB7_FMPLUS
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description: Fast-mode Plus command on PB(7)
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bit_offset: 17
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bit_size: 1
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- name: PB8_FMPLUS
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description: Fast-mode Plus command on PB(8)
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bit_offset: 18
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bit_size: 1
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- name: PB9_FMPLUS
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description: Fast-mode Plus command on PB(9)
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bit_offset: 19
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bit_size: 1
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- name: ETH_SEL_PHY
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description: "Ethernet PHY interface selection\r Other: reserved"
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bit_offset: 21
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bit_size: 3
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enum: ETH_SEL_PHY
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fieldset/RSSCMDR:
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description: SBS RSS command register
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fields:
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- name: RSSCMD
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description: "RSS command\r The application can use this bitfield to pass on a command to the RSS, executed at the next reset.\r When RSSCMD ≠ 0 and PRODUCT_STATE is in Open, then the system always boots on RSS whatever is the boot pin value."
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bit_offset: 0
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bit_size: 16
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fieldset/SECCFGR:
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description: SBS security mode configuration control register
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fields:
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- name: SBSSEC
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description: SBS clock control, memory-erase status register and compensation cell register security enable
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bit_offset: 0
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bit_size: 1
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enum: SEC
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- name: CLASSBSEC
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description: ClassB security enable
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bit_offset: 1
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bit_size: 1
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enum: SEC
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- name: FPUSEC
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description: "FPU security enable\r Note: This bit can only be written through privilege transaction."
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bit_offset: 3
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bit_size: 1
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enum: SEC
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- name: SDCE_SEC_EN
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description: control accessibility of SMPS_DIV_CLOCK _EN in SBS_PMCR
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bit_offset: 31
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bit_size: 1
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enum/CS:
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bit_size: 1
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variants:
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- name: Cell
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description: Code from the cell (available in the SBS_CCVR)
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value: 0
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- name: Software
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description: Code from SBS_CCCR
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value: 1
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enum/DBGCFG_LOCK:
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bit_size: 8
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variants:
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- name: B_0xB4
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description: Writes to SBS_DBGCR allowed (default)
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value: 180
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enum/DBG_AUTH_HDPL:
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bit_size: 8
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variants:
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- name: B_0x51
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description: HDPL1
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value: 81
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- name: B_0x6F
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description: HDPL3
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value: 111
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- name: B_0x8A
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description: HDPL2
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value: 138
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enum/EPOCH_SEL:
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bit_size: 2
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variants:
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- name: B_0x0
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description: SEC_EPOCH counter input selected
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value: 0
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- name: B_0x1
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description: NS_EPOCH (non-secure) input selected
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value: 1
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enum/ETH_SEL_PHY:
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bit_size: 3
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variants:
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- name: B_0x0
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description: GMII or MII
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value: 0
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- name: B_0x1
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description: reserved (RGMII)
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value: 1
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- name: B_0x4
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description: RMII
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value: 4
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enum/HDPL:
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bit_size: 8
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variants:
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- name: B_0x51
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description: HDPL1, iRoT
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value: 81
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- name: B_0x6F
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description: HDPL3, application (secure/non-secure)
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value: 111
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- name: B_0x8A
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description: HDPL2, uRoT
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value: 138
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- name: B_0xB4
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description: HDPL0, RSS
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value: 180
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enum/INCR_HDPL:
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bit_size: 8
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variants:
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- name: B_0x6A
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description: recommended value to increment HDPL level by one
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value: 106
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- name: B_0xB4
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description: no increment
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value: 180
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enum/SEC:
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bit_size: 1
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variants:
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- name: B_0x0
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description: SBS_CFGR2 register accessible through secure or non-secure transaction
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value: 0
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- name: B_0x1
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description: SBS_CFGR2 register only accessible through secure transaction
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value: 1
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