599 lines
16 KiB
YAML
599 lines
16 KiB
YAML
block/SYSCFG:
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description: System configuration controller
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items:
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- name: CFGR1
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description: configuration register 1
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byte_offset: 0
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fieldset: CFGR1
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- name: RCR
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description: CCM SRAM protection register
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byte_offset: 4
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fieldset: RCR
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- name: EXTICR
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description: external interrupt configuration register
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array:
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len: 4
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stride: 4
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byte_offset: 8
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fieldset: EXTICR
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- name: CFGR2
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description: configuration register 2
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byte_offset: 24
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fieldset: CFGR2
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- name: CFGR4
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description: configuration register 4
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byte_offset: 72
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fieldset: CFGR4
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- name: CFGR3
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description: configuration register 3
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byte_offset: 80
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fieldset: CFGR3
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fieldset/CFGR1:
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description: configuration register 1
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fields:
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- name: MEM_MODE
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description: Memory mapping selection bits
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bit_offset: 0
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bit_size: 2
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enum: MEM_MODE
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- name: USB_IT_RMP
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description: |
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USB interrupt remap
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0: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 19, 20 and 42 respectively
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1: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 74, 75 and 76 respectively
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bit_offset: 5
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bit_size: 1
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- name: TIM1_ITR3_RMP
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description: |
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Timer 1 ITR3 selection
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0: Not remapped
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1: TIM1_ITR3 = TIM17_OC
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bit_offset: 6
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bit_size: 1
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- name: DAC1_TRIG_RMP
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description: |
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DAC trigger remap (when TSEL = 001)
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0: DAC trigger is TIM8_TRGO in STM32F303xB/C and STM32F358xC devices
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1: DAC trigger is TIM3_TRGO
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bit_offset: 7
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bit_size: 1
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- name: DAC_TRIG_RMP
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description: |
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DAC trigger remap (when TSEL = 001)
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0: Not remapped
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1: DAC trigger is TIM3_TRGO
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bit_offset: 7
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bit_size: 1
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- name: ADC2_DMA_RMP
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description: |
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ADC24 DMA remapping bit
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0: ADC24 DMA requests mapped on DMA2 channels 1 and 2
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1: ADC24 DMA requests mapped on DMA2 channels 3 and 4
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bit_offset: 8
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bit_size: 1
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- name: TIM16_DMA_RMP
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description: |
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TIM16 DMA request remapping bit
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0: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3
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1: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4
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bit_offset: 11
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bit_size: 1
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- name: TIM17_DMA_RMP
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description: |
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TIM17 DMA request remapping bit
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0: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1
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1: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2
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bit_offset: 12
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bit_size: 1
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- name: TIM6_DAC1_CH1_DMA_RMP
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description: |
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TIM6 and DAC1 DMA request remapping bit
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0: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3
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1: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3
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bit_offset: 13
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bit_size: 1
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- name: TIM6_DAC1_DMA_RMP
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description: |
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TIM6 and DAC1 DMA request remapping bit
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0: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3
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1: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3
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bit_offset: 13
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bit_size: 1
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- name: TIM6_DAC1_OUT1_DMA_RMP
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description: |
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TIM6 and DAC1 DMA request remapping bit
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0: TIM7 and DAC1_OUT1 DMA requests mapped on DMA2 channel 3
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1: TIM7 and DAC1_OUT1 DMA requests mapped on DMA1 channel 3
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bit_offset: 13
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bit_size: 1
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- name: TIM7_DAC1_CH2_DMA_RMP
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description: |
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TIM7 and DAC2 DMA request remapping bit
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0: Not remapped
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1: TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4
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bit_offset: 14
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bit_size: 1
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- name: TIM7_DAC1_OUT2_DMA_RMP
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description: |
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TIM7 and DAC2 DMA request remapping bit
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0: TIM7 and DAC1_OUT2 DMA requests mapped on DMA2 channel 4
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1: TIM7 and DAC1_OUT2 DMA requests mapped on DMA1 channel 4
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bit_offset: 14
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bit_size: 1
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- name: DAC2_CH1_DMA_RMP
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description: |
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DAC2 channel1 DMA remap
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0: Not remapped
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1: DAC2_CH1 DMA requests mapped on DMA1 channel 5
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bit_offset: 15
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bit_size: 1
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- name: TIM18_DAC2_OUT1_DMA_RMP
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description: |
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TIM18 and DAC2_OUT1 DMA request remapping bit
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0: TIM18 and DAC2_OUT1 DMA requests mapped on DMA2 channel 5
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1: TIM18 and DAC2_OUT1 DMA requests mapped on DMA1 channel 5
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bit_offset: 15
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bit_size: 1
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- name: I2C_PB6_FMP
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description: |
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Fast Mode Plus (FM+) driving capability activation bits.
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0: PB6 pin operate in standard mode
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1: I2C FM+ mode enabled on PB6 and the Speed control is bypassed
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bit_offset: 16
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bit_size: 1
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enum: FMP
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- name: I2C_PB7_FMP
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description: |
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Fast Mode Plus (FM+) driving capability activation bits.
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0: PB7 pin operate in standard mode
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1: I2C FM+ mode enabled on PB7 and the Speed control is bypassed
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bit_offset: 17
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bit_size: 1
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enum: FMP
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- name: I2C_PB8_FMP
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description: |
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Fast Mode Plus (FM+) driving capability activation bits.
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0: PB8 pin operate in standard mode
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1: I2C FM+ mode enabled on PB8 and the Speed control is bypassed
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bit_offset: 18
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bit_size: 1
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enum: FMP
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- name: I2C_PB9_FMP
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description: |
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Fast Mode Plus (FM+) driving capability activation bits.
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0: PB9 pin operate in standard mode
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1: I2C FM+ mode enabled on PB9 and the Speed control is bypassed
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bit_offset: 19
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bit_size: 1
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enum: FMP
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- name: I2C1_FMP
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description: |
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I2C1 Fast Mode Plus
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0: FM+ mode is controlled by I2C_Pxx_FMP bits only
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1: FM+ mode is enabled on all I2C1 pins selected through selection through IOPORT control registers AF selection bits
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bit_offset: 20
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bit_size: 1
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enum: FMP
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- name: I2C2_FMP
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description: |
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I2C2 Fast Mode Plus
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0: FM+ mode is controlled by I2C_Pxx_FMP bits only
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1: FM+ mode is enabled on all I2C2 pins selected through selection through IOPORT control registers AF selection bits
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bit_offset: 21
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bit_size: 1
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enum: FMP
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- name: ENCODER_MODE
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description: Encoder mode
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bit_offset: 22
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bit_size: 2
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enum: ENCODER_MODE
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- name: I2C3_FMP
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description: |
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I2C3 Fast Mode Plus
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0: FM+ mode is controlled by I2C_Pxx_FMP bits only
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1: FM+ mode is enabled on all I2C3 pins selected through selection trhough IOPORT control registers AF selection bits
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bit_offset: 24
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bit_size: 1
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enum: FMP
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- name: VBAT_MON
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description: Enable the power switch to deliver VBAT voltage on ADC channel 18 input
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bit_offset: 24
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bit_size: 1
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- name: FPU_IE
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description: |-
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Idx 0: Invalid operation interrupt enable;
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Idx 1: Devide-by-zero interrupt enable;
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Idx 2: Underflow interrupt enable;
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Idx 3: Overflow interrupt enable;
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Idx 4: Input denormal interrupt enable;
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Idx 5: Inexact interrupt enable
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bit_offset: 26
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bit_size: 1
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array:
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len: 6
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stride: 1
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fieldset/CFGR2:
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description: configuration register 2
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fields:
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- name: LOCKUP_LOCK
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description: Cortex-M0 LOCKUP bit enable bit
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bit_offset: 0
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bit_size: 1
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- name: SRAM_PARITY_LOCK
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description: SRAM parity lock bit
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bit_offset: 1
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bit_size: 1
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- name: PVD_LOCK
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description: PVD lock enable bit
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bit_offset: 2
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bit_size: 1
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- name: BYP_ADDR_PAR
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description: Bypass address bit 29 in parity calculation
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bit_offset: 4
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bit_size: 1
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- name: SRAM_PEF
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description: SRAM parity flag
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bit_offset: 8
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bit_size: 1
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fieldset/CFGR3:
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description: configuration register 3
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fields:
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- name: SPI1_RX_DMA_RMP
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description: SPI1_RX DMA remapping bit
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bit_offset: 0
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bit_size: 2
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enum: SPI1_RX_DMA_RMP
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- name: SPI1_TX_DMA_RMP
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description: SPI1_TX DMA remapping bit
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bit_offset: 2
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bit_size: 2
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enum: SPI1_TX_DMA_RMP
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- name: I2C1_RX_DMA_RMP
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description: I2C1_RX DMA remapping bit
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bit_offset: 4
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bit_size: 2
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enum: I2C1_RX_DMA_RMP
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- name: I2C1_TX_DMA_RMP
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description: I2C1_TX DMA remapping bit
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bit_offset: 6
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bit_size: 2
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enum: I2C1_TX_DMA_RMP
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- name: ADC2_DMA_RMP
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description: ADC2 DMA remapping bit
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bit_offset: 8
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bit_size: 2
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enum: ADC2_DMA_RMP_CFGR3
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- name: DAC1_TRIG3_RMP
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description: DAC1_CH1 / DAC1_CH2 Trigger remap
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bit_offset: 16
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bit_size: 1
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enum: DAC1_TRIG3_RMP
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- name: DAC1_TRIG5_RMP
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description: |
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DAC1_CH1 / DAC1_CH2 Trigger remap
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0: Not remapped
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1: DAC trigger is HRTIM1_DAC1_TRIG2
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bit_offset: 17
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bit_size: 1
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fieldset/CFGR4:
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description: configuration register 4
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fields:
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- name: ADC12_EXT2_RMP
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description: Controls the Input trigger of ADC12 regular channel EXT2
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bit_offset: 0
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bit_size: 1
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enum: ADC12_EXT2_RMP
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- name: ADC12_EXT3_RMP
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description: Controls the Input trigger of ADC12 regular channel EXT3
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bit_offset: 1
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bit_size: 1
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enum: ADC12_EXT3_RMP
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- name: ADC12_EXT5_RMP
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description: Controls the Input trigger of ADC12 regular channel EXT5
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bit_offset: 2
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bit_size: 1
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enum: ADC12_EXT5_RMP
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- name: ADC12_EXT13_RMP
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description: Controls the Input trigger of ADC12 regular channel EXT13
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bit_offset: 3
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bit_size: 1
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enum: ADC12_EXT13_RMP
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- name: ADC12_EXT15_RMP
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description: Controls the Input trigger of ADC12 regular channel EXT15
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bit_offset: 4
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bit_size: 1
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enum: ADC12_EXT15_RMP
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- name: ADC12_JEXT3_RMP
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description: Controls the Input trigger of ADC12 injected channel JEXT3
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bit_offset: 5
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bit_size: 1
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enum: ADC12_JEXT3_RMP
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- name: ADC12_JEXT6_RMP
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description: Controls the Input trigger of ADC12 injected channel JEXT6
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bit_offset: 6
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bit_size: 1
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enum: ADC12_JEXT6_RMP
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- name: ADC12_JEXT13_RMP
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description: Controls the Input trigger of ADC12 injected channel JEXT13
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bit_offset: 7
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bit_size: 1
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enum: ADC12_JEXT13_RMP
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- name: ADC34_EXT5_RMP
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description: Controls the Input trigger of ADC34 regular channel EXT5
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bit_offset: 8
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bit_size: 1
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enum: ADC34_EXT5_RMP
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- name: ADC34_EXT6_RMP
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description: Controls the Input trigger of ADC34 regular channel EXT6
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bit_offset: 9
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bit_size: 1
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enum: ADC34_EXT6_RMP
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- name: ADC34_EXT15_RMP
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description: Controls the Input trigger of ADC34 regular channel EXT15
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bit_offset: 10
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bit_size: 1
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enum: ADC34_EXT15_RMP
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- name: ADC34_JEXT5_RMP
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description: Controls the Input trigger of ADC34 injected channel JEXT5
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bit_offset: 11
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bit_size: 1
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enum: ADC34_JEXT5_RMP
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- name: ADC34_JEXT11_RMP
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description: Controls the Input trigger of ADC34 injected channel JEXT11
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bit_offset: 12
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bit_size: 1
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enum: ADC34_JEXT11_RMP
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- name: ADC34_JEXT14_RMP
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description: Controls the Input trigger of ADC34 injected channel JEXT14
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bit_offset: 13
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bit_size: 1
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enum: ADC34_JEXT14_RMP
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fieldset/EXTICR:
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description: external interrupt configuration register
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fields:
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- name: EXTI
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description: EXTI x configuration
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bit_offset: 0
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bit_size: 4
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array:
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len: 4
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stride: 4
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fieldset/RCR:
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description: CCM SRAM protection register
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fields:
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- name: PAGE_WP
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description: CCM SRAM page x write protection enabled
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bit_offset: 0
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bit_size: 1
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array:
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len: 16
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stride: 1
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enum/ADC12_EXT13_RMP:
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bit_size: 1
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variants:
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- name: Tim6
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description: Trigger source is TIM6_TRGO
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value: 0
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- name: Tim20
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description: Trigger source is TIM20_CC2
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value: 1
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enum/ADC12_EXT15_RMP:
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bit_size: 1
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variants:
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- name: Tim3
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description: Trigger source is TIM3_CC4
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value: 0
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- name: Tim20
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description: Trigger source is TIM20_CC3
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value: 1
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enum/ADC12_EXT2_RMP:
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bit_size: 1
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variants:
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- name: Tim1
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description: Trigger source is TIM3_CC3
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value: 0
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- name: Tim20
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description: rigger source is TIM20_TRGO
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value: 1
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enum/ADC12_EXT3_RMP:
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bit_size: 1
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variants:
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- name: Tim2
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description: Trigger source is TIM2_CC2
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value: 0
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- name: Tim20
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description: rigger source is TIM20_TRGO2
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value: 1
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enum/ADC12_EXT5_RMP:
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bit_size: 1
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variants:
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- name: Tim4
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description: Trigger source is TIM4_CC4
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value: 0
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- name: Tim20
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description: Trigger source is TIM20_CC1
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value: 1
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enum/ADC12_JEXT13_RMP:
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bit_size: 1
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variants:
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- name: Tim3
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description: Trigger source is TIM3_CC1
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value: 0
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- name: Tim20
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description: Trigger source is TIM20_CC4
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value: 1
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enum/ADC12_JEXT3_RMP:
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bit_size: 1
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variants:
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- name: Tim2
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description: Trigger source is TIM2_CC1
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value: 0
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- name: Tim20
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description: Trigger source is TIM20_TRGO
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value: 1
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enum/ADC12_JEXT6_RMP:
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bit_size: 1
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variants:
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- name: Exti15
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description: Trigger source is EXTI line 15
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value: 0
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- name: Tim20
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description: Trigger source is TIM20_TRGO2
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value: 1
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enum/ADC2_DMA_RMP_CFGR3:
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bit_size: 2
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variants:
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- name: MapDma1Ch2
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description: ADC2 mapped on DMA1 channel 2
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value: 2
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- name: MapDma1Ch4
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description: ADC2 mapped on DMA1 channel 4
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value: 3
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enum/ADC34_EXT15_RMP:
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bit_size: 1
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variants:
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- name: Tim2
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description: Trigger source is TIM2_CC1
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value: 0
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- name: Tim20
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description: Trigger source is TIM20_CC1
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value: 1
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enum/ADC34_EXT5_RMP:
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bit_size: 1
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variants:
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- name: Exti2
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description: Trigger source is EXTI line 2 when reset at 0
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value: 0
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- name: Tim20
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description: Trigger source is TIM20_TRGO
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value: 1
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enum/ADC34_EXT6_RMP:
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bit_size: 1
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variants:
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- name: Tim4
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description: Trigger source is TIM4_CC1
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value: 0
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- name: Tim20
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description: Trigger source is TIM20_TRGO2
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value: 1
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enum/ADC34_JEXT11_RMP:
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bit_size: 1
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variants:
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- name: Tim1
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description: Trigger source is TIM1_CC3
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value: 0
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- name: Tim20
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description: Trigger source is TIM20_TRGO2
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value: 1
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enum/ADC34_JEXT14_RMP:
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bit_size: 1
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variants:
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- name: Tim7
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description: Trigger source is TIM7_TRGO
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value: 0
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- name: Tim20
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description: Trigger source is TIM20_CC2
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value: 1
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enum/ADC34_JEXT5_RMP:
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bit_size: 1
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variants:
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- name: Tim4
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description: Trigger source is TIM4_CC3
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value: 0
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- name: Tim20
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description: Trigger source is TIM20_TRGO
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value: 1
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enum/DAC1_TRIG3_RMP:
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bit_size: 1
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variants:
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- name: Tim15
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description: DAC trigger is TIM15_TRGO
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value: 0
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- name: HrTim1
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description: DAC trigger is HRTIM1_DAC1_TRIG1
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value: 1
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enum/ENCODER_MODE:
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bit_size: 2
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variants:
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- name: NoRedirection
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description: No redirection
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|
value: 0
|
|
- name: MapTim2Tim15
|
|
description: TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
|
|
value: 1
|
|
- name: MapTim3Tim15
|
|
description: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
|
|
value: 2
|
|
enum/FMP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Standard
|
|
description: PB6 pin operate in standard mode
|
|
value: 0
|
|
- name: FMP
|
|
description: I2C FM+ mode enabled on PB6 and the Speed control is bypassed
|
|
value: 1
|
|
enum/I2C1_RX_DMA_RMP:
|
|
bit_size: 2
|
|
variants:
|
|
- name: MapDma1Ch7
|
|
description: I2C1_RX mapped on DMA1 CH7
|
|
value: 0
|
|
- name: MapDma1Ch3
|
|
description: I2C1_RX mapped on DMA1 CH3
|
|
value: 1
|
|
- name: MapDma1Ch5
|
|
description: I2C1_RX mapped on DMA1 CH5
|
|
value: 2
|
|
enum/I2C1_TX_DMA_RMP:
|
|
bit_size: 2
|
|
variants:
|
|
- name: MapDma1Ch6
|
|
description: I2C1_TX mapped on DMA1 CH6
|
|
value: 0
|
|
- name: MapDma1Ch2
|
|
description: I2C1_TX mapped on DMA1 CH2
|
|
value: 1
|
|
- name: MapDma1Ch4
|
|
description: I2C1_TX mapped on DMA1 CH4
|
|
value: 2
|
|
enum/MEM_MODE:
|
|
bit_size: 2
|
|
variants:
|
|
- name: MainFlash
|
|
description: Main Flash memory mapped at 0x0000_0000
|
|
value: 0
|
|
- name: SystemFlash
|
|
description: System Flash memory mapped at 0x0000_0000
|
|
value: 1
|
|
- name: MainFlash2
|
|
description: Main Flash memory mapped at 0x0000_0000
|
|
value: 2
|
|
- name: SRAM
|
|
description: Embedded SRAM mapped at 0x0000_0000
|
|
value: 3
|
|
enum/SPI1_RX_DMA_RMP:
|
|
bit_size: 2
|
|
variants:
|
|
- name: MapDma1Ch3
|
|
description: SPI1_RX mapped on DMA1 CH2
|
|
value: 0
|
|
- name: MapDma1Ch5
|
|
description: SPI1_RX mapped on DMA1 CH4
|
|
value: 1
|
|
- name: MapDma1Ch7
|
|
description: SPI1_RX mapped on DMA1 CH6
|
|
value: 2
|
|
enum/SPI1_TX_DMA_RMP:
|
|
bit_size: 2
|
|
variants:
|
|
- name: MapDma1Ch3
|
|
description: SPI1_TX mapped on DMA1 CH3
|
|
value: 0
|
|
- name: MapDma1Ch5
|
|
description: SPI1_TX mapped on DMA1 CH5
|
|
value: 1
|
|
- name: MapDma1Ch7
|
|
description: SPI1_TX mapped on DMA1 CH7
|
|
value: 2
|