579 lines
12 KiB
YAML
579 lines
12 KiB
YAML
block/OCTOSPI:
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description: OctoSPI
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items:
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- name: CR
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description: control register
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byte_offset: 0
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fieldset: CR
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- name: DCR1
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description: device configuration register 1
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byte_offset: 8
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fieldset: DCR1
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- name: DCR2
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description: device configuration register 2
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byte_offset: 12
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fieldset: DCR2
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- name: DCR3
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description: device configuration register 3
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byte_offset: 16
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fieldset: DCR3
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- name: DCR4
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description: DCR4
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byte_offset: 20
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fieldset: DCR4
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- name: SR
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description: status register
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byte_offset: 32
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access: Read
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fieldset: SR
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- name: FCR
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description: flag clear register
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byte_offset: 36
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access: Write
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fieldset: FCR
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- name: DLR
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description: data length register
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byte_offset: 64
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fieldset: DLR
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- name: AR
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description: address register
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byte_offset: 72
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fieldset: AR
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- name: DR
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description: data register
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byte_offset: 80
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fieldset: DR
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- name: PSMKR
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description: polling status mask register
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byte_offset: 128
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fieldset: PSMKR
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- name: PSMAR
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description: polling status match register
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byte_offset: 136
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fieldset: PSMAR
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- name: PIR
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description: polling interval register
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byte_offset: 144
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fieldset: PIR
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- name: CCR
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description: communication configuration register
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byte_offset: 256
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fieldset: CCR
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- name: TCR
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description: timing configuration register
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byte_offset: 264
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fieldset: TCR
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- name: IR
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description: instruction register
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byte_offset: 272
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fieldset: IR
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- name: ABR
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description: alternate bytes register
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byte_offset: 288
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fieldset: ABR
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- name: LPTR
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description: low-power timeout register
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byte_offset: 304
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fieldset: LPTR
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- name: WPCCR
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description: wrap communication configuration register
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byte_offset: 320
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fieldset: WPCCR
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- name: WPTCR
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description: wrap timing configuration register
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byte_offset: 328
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fieldset: WPTCR
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- name: WPIR
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description: wrap instruction register
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byte_offset: 336
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fieldset: WPIR
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- name: WPABR
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description: wrap alternate bytes register
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byte_offset: 352
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fieldset: WPABR
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- name: WCCR
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description: write communication configuration register
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byte_offset: 384
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fieldset: WCCR
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- name: WTCR
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description: write timing configuration register
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byte_offset: 392
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fieldset: WTCR
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- name: WIR
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description: write instruction register
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byte_offset: 400
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fieldset: WIR
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- name: WABR
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description: write alternate bytes register
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byte_offset: 416
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fieldset: WABR
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- name: HLCR
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description: HyperBusTM latency configuration register
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byte_offset: 512
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fieldset: HLCR
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fieldset/ABR:
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description: alternate bytes register
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fields:
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- name: TIMEOUT
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description: Timeout period
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bit_offset: 0
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bit_size: 16
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fieldset/AR:
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description: address register
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fields:
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- name: DATA
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description: Data
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bit_offset: 0
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bit_size: 32
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fieldset/CCR:
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description: communication configuration register
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fields:
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- name: DCYC
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description: Number of dummy cycles
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bit_offset: 0
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bit_size: 5
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- name: DHQC
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description: Delay hold quarter cycle
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bit_offset: 28
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bit_size: 1
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- name: SSHIFT
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description: Sample shift
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bit_offset: 30
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bit_size: 1
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fieldset/CR:
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description: control register
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fields:
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- name: EN
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description: Enable
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bit_offset: 0
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bit_size: 1
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- name: ABORT
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description: Abort request
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bit_offset: 1
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bit_size: 1
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- name: DMAEN
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description: DMA enable
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bit_offset: 2
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bit_size: 1
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- name: TCEN
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description: Timeout counter enable
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bit_offset: 3
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bit_size: 1
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- name: DQM
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description: Dual-quad mode
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bit_offset: 6
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bit_size: 1
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- name: FSEL
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description: FLASH memory selection
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bit_offset: 7
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bit_size: 1
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- name: FTHRES
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description: IFO threshold level
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bit_offset: 8
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bit_size: 5
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- name: TEIE
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description: Transfer error interrupt enable
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bit_offset: 16
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bit_size: 1
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- name: TCIE
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description: Transfer complete interrupt enable
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bit_offset: 17
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bit_size: 1
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- name: FTIE
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description: FIFO threshold interrupt enable
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bit_offset: 18
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bit_size: 1
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- name: SMIE
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description: Status match interrupt enable
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bit_offset: 19
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bit_size: 1
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- name: TOIE
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description: TimeOut interrupt enable
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bit_offset: 20
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bit_size: 1
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- name: APMS
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description: Automatic poll mode stop
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bit_offset: 22
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bit_size: 1
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- name: PMM
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description: Polling match mode
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bit_offset: 23
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bit_size: 1
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- name: FMODE
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description: Functional mode
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bit_offset: 28
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bit_size: 2
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fieldset/DCR1:
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description: device configuration register
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fields:
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- name: CKMODE
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description: Mode 0 / mode 3
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bit_offset: 0
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bit_size: 1
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- name: FRCK
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description: Free running clock
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bit_offset: 1
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bit_size: 1
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- name: CSHT
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description: Chip-select high time
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bit_offset: 8
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bit_size: 3
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- name: DEVSIZE
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description: Device size
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bit_offset: 16
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bit_size: 5
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- name: MTYP
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description: Memory type
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bit_offset: 24
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bit_size: 2
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fieldset/DCR2:
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description: device configuration register 2
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fields:
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- name: PRESCALER
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description: Clock prescaler
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bit_offset: 0
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bit_size: 8
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- name: WRAPSIZE
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description: Wrap size
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bit_offset: 16
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bit_size: 3
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fieldset/DCR3:
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description: device configuration register 3
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fields:
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- name: CSBOUND
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description: CS boundary
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bit_offset: 16
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bit_size: 5
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fieldset/DCR4:
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description: DCR4
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fields:
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- name: TEF
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description: Transfer error flag
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bit_offset: 0
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bit_size: 1
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- name: TCF
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description: Transfer complete flag
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bit_offset: 1
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bit_size: 1
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- name: FTF
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description: FIFO threshold flag
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bit_offset: 2
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bit_size: 1
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- name: SMF
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description: Status match flag
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bit_offset: 3
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bit_size: 1
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- name: TOF
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description: Timeout flag
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bit_offset: 4
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bit_size: 1
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- name: BUSY
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description: Busy
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bit_offset: 5
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bit_size: 1
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- name: FLEVEL
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description: FIFO level
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bit_offset: 8
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bit_size: 6
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fieldset/DLR:
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description: data length register
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fields:
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- name: ADDRESS
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description: ADDRESS
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bit_offset: 0
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bit_size: 32
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fieldset/DR:
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description: data register
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fields:
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- name: MASK
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description: Status mask
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bit_offset: 0
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bit_size: 32
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fieldset/FCR:
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description: flag clear register
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fields:
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- name: DL
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description: Data length
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bit_offset: 0
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bit_size: 32
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fieldset/HLCR:
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description: HyperBusTM latency configuration register
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fields:
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- name: ALTERNATE
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description: Alternate bytes
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bit_offset: 0
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bit_size: 32
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fieldset/IR:
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description: instruction register
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fields:
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- name: ALTERNATE
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description: Alternate bytes
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bit_offset: 0
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bit_size: 32
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fieldset/LPTR:
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description: low-power timeout register
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fields:
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- name: IMODE
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description: Instruction mode
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bit_offset: 0
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bit_size: 3
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- name: IDTR
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description: Instruction double transfer rate
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bit_offset: 2
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bit_size: 1
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- name: ISIZE
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description: Instruction size
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bit_offset: 4
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bit_size: 2
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- name: ADMODE
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description: Address mode
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bit_offset: 8
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bit_size: 3
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- name: ADDTR
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description: Address double transfer rate
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bit_offset: 11
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bit_size: 1
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- name: ADSIZE
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description: Address size
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bit_offset: 12
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bit_size: 2
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- name: ABMODE
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description: Alternate-byte mode
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bit_offset: 16
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bit_size: 3
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- name: ABDTR
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description: Alternate bytes double transfer rate
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bit_offset: 19
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bit_size: 1
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- name: ABSIZE
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description: Alternate bytes size
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bit_offset: 20
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bit_size: 2
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- name: DMODE
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description: Data mode
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bit_offset: 24
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bit_size: 3
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- name: DDTR
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description: alternate bytes double transfer rate
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bit_offset: 27
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bit_size: 1
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- name: DQSE
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description: DQS enable
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bit_offset: 29
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bit_size: 1
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fieldset/PIR:
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description: polling interval register
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fields:
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- name: IMODE
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description: Instruction mode
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bit_offset: 0
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bit_size: 3
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- name: IDTR
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description: Instruction double transfer rate
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bit_offset: 3
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bit_size: 1
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- name: ISIZE
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description: Instruction size
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bit_offset: 4
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bit_size: 2
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- name: ADMODE
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description: Address mode
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bit_offset: 8
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bit_size: 3
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- name: ADDTR
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description: Address double transfer rate
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bit_offset: 11
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bit_size: 1
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- name: ADSIZE
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description: Address size
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bit_offset: 12
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bit_size: 2
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- name: ABMODE
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description: Alternate byte mode
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bit_offset: 16
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bit_size: 3
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- name: ABDTR
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description: Alternate bytes double transfer rate
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bit_offset: 19
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bit_size: 1
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- name: ABSIZE
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description: Alternate bytes size
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bit_offset: 20
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bit_size: 2
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- name: DMODE
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description: Data mode
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bit_offset: 24
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bit_size: 3
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- name: DDTR
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description: alternate bytes double transfer rate
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bit_offset: 27
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bit_size: 1
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- name: DQSE
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description: DQS enable
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bit_offset: 29
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bit_size: 1
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- name: SIOO
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description: Send instruction only once mode
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bit_offset: 31
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bit_size: 1
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fieldset/PSMAR:
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description: polling status match register
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fields:
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- name: INTERVAL
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description: Polling interval
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bit_offset: 0
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bit_size: 16
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fieldset/PSMKR:
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description: polling status mask register
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fields:
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- name: MATCH
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description: Status match
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bit_offset: 0
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bit_size: 32
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fieldset/SR:
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description: status register
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fields:
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- name: CTEF
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description: Clear transfer error flag
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bit_offset: 0
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bit_size: 1
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- name: CTCF
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description: Clear transfer complete flag
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bit_offset: 1
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bit_size: 1
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- name: CSMF
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description: Clear status match flag
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bit_offset: 3
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bit_size: 1
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- name: CTOF
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description: Clear timeout flag
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bit_offset: 4
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bit_size: 1
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fieldset/TCR:
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description: timing configuration register
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fields:
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- name: INSTRUCTION
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description: INSTRUCTION
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bit_offset: 0
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bit_size: 32
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fieldset/WABR:
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description: WABR
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fields:
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- name: INSTRUCTION
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description: INSTRUCTION
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bit_offset: 0
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bit_size: 32
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fieldset/WCCR:
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description: WCCR
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fields:
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- name: REFRESH
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description: REFRESH
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bit_offset: 0
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bit_size: 16
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fieldset/WIR:
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description: WIR
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fields:
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- name: DCYC
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description: DCYC
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bit_offset: 0
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bit_size: 5
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fieldset/WPABR:
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description: write alternate bytes register
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fields:
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- name: LM
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description: Latency mode
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bit_offset: 0
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bit_size: 1
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- name: WZL
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description: Write zero latency
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bit_offset: 1
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bit_size: 1
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- name: TACC
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description: Access time
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bit_offset: 8
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bit_size: 8
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- name: TRWR
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description: Read write recovery time
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bit_offset: 16
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bit_size: 8
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fieldset/WPCCR:
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description: write communication configuration register
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fields:
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- name: DCYC
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description: Number of dummy cycles
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bit_offset: 0
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bit_size: 5
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- name: DHQC
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description: Delay hold quarter cycle
|
|
bit_offset: 28
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|
bit_size: 1
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- name: SSHIFT
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description: Sample shift
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|
bit_offset: 30
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|
bit_size: 1
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|
fieldset/WPIR:
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description: write instruction register
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|
fields:
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- name: ALTERNATE
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description: Alternate bytes
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bit_offset: 0
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|
bit_size: 32
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|
fieldset/WPTCR:
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description: write timing configuration register
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fields:
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- name: INSTRUCTION
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description: INSTRUCTION
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bit_offset: 0
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bit_size: 32
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fieldset/WTCR:
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description: write timing configuration register
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fields:
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- name: IMODE
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description: IMODE
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bit_offset: 0
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|
bit_size: 3
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|
- name: IDTR
|
|
description: IDTR
|
|
bit_offset: 3
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|
bit_size: 1
|
|
- name: ISIZE
|
|
description: ISIZE
|
|
bit_offset: 4
|
|
bit_size: 2
|
|
- name: ADMODE
|
|
description: ADMODE
|
|
bit_offset: 8
|
|
bit_size: 3
|
|
- name: ADDTR
|
|
description: ADDTR
|
|
bit_offset: 11
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|
bit_size: 1
|
|
- name: ADSIZE
|
|
description: ADSIZE
|
|
bit_offset: 12
|
|
bit_size: 2
|
|
- name: ABMODE
|
|
description: ABMODE
|
|
bit_offset: 16
|
|
bit_size: 3
|
|
- name: ABDTR
|
|
description: ABDTR
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: ABSIZE
|
|
description: ABSIZE
|
|
bit_offset: 20
|
|
bit_size: 2
|
|
- name: DMODE
|
|
description: DMODE
|
|
bit_offset: 24
|
|
bit_size: 3
|
|
- name: DDTR
|
|
description: DDTR
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: DQSE
|
|
description: DQSE
|
|
bit_offset: 29
|
|
bit_size: 1
|