427 lines
11 KiB
YAML
427 lines
11 KiB
YAML
---
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block/ETHERNET_DMA:
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description: "Ethernet: DMA mode register (DMA)"
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items:
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- name: DMAMR
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description: DMA mode register
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byte_offset: 0
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fieldset: DMAMR
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- name: DMASBMR
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description: System bus mode register
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byte_offset: 4
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fieldset: DMASBMR
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- name: DMAISR
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description: Interrupt status register
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byte_offset: 8
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access: Read
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fieldset: DMAISR
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- name: DMADSR
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description: Debug status register
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byte_offset: 12
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access: Read
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fieldset: DMADSR
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- name: DMACCR
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description: Channel control register
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byte_offset: 256
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fieldset: DMACCR
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- name: DMACTxCR
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description: Channel transmit control register
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byte_offset: 260
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fieldset: DMACTxCR
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- name: DMACRxCR
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description: Channel receive control register
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byte_offset: 264
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fieldset: DMACRxCR
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- name: DMACTxDLAR
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description: Channel Tx descriptor list address register
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byte_offset: 276
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fieldset: DMACTxDLAR
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- name: DMACRxDLAR
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description: Channel Rx descriptor list address register
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byte_offset: 284
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fieldset: DMACRxDLAR
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- name: DMACTxDTPR
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description: Channel Tx descriptor tail pointer register
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byte_offset: 288
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fieldset: DMACTxDTPR
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- name: DMACRxDTPR
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description: Channel Rx descriptor tail pointer register
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byte_offset: 296
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fieldset: DMACRxDTPR
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- name: DMACTxRLR
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description: Channel Tx descriptor ring length register
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byte_offset: 300
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fieldset: DMACTxRLR
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- name: DMACRxRLR
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description: Channel Rx descriptor ring length register
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byte_offset: 304
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fieldset: DMACRxRLR
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- name: DMACIER
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description: Channel interrupt enable register
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byte_offset: 308
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fieldset: DMACIER
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- name: DMACRxIWTR
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description: Channel Rx interrupt watchdog timer register
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byte_offset: 312
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fieldset: DMACRxIWTR
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- name: DMACCATxDR
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description: Channel current application transmit descriptor register
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byte_offset: 324
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access: Read
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fieldset: DMACCATxDR
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- name: DMACCARxDR
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description: Channel current application receive descriptor register
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byte_offset: 332
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access: Read
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fieldset: DMACCARxDR
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- name: DMACCATxBR
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description: Channel current application transmit buffer register
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byte_offset: 340
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access: Read
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fieldset: DMACCATxBR
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- name: DMACCARxBR
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description: Channel current application receive buffer register
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byte_offset: 348
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access: Read
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fieldset: DMACCARxBR
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- name: DMACSR
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description: Channel status register
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byte_offset: 352
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fieldset: DMACSR
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- name: DMACMFCR
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description: Channel missed frame count register
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byte_offset: 364
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access: Read
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fieldset: DMACMFCR
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fieldset/DMACCARxBR:
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description: Channel current application receive buffer register
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fields:
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- name: CURRBUFAPTR
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description: Application Receive Buffer Address Pointer
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bit_offset: 0
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bit_size: 32
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fieldset/DMACCARxDR:
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description: Channel current application receive descriptor register
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fields:
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- name: CURRDESAPTR
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description: Application Receive Descriptor Address Pointer
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bit_offset: 0
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bit_size: 32
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fieldset/DMACCATxBR:
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description: Channel current application transmit buffer register
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fields:
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- name: CURTBUFAPTR
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description: Application Transmit Buffer Address Pointer
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bit_offset: 0
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bit_size: 32
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fieldset/DMACCATxDR:
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description: Channel current application transmit descriptor register
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fields:
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- name: CURTDESAPTR
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description: Application Transmit Descriptor Address Pointer
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bit_offset: 0
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bit_size: 32
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fieldset/DMACCR:
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description: Channel control register
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fields:
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- name: MSS
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description: Maximum Segment Size
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bit_offset: 0
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bit_size: 14
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- name: PBLX8
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description: 8xPBL mode
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bit_offset: 16
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bit_size: 1
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- name: DSL
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description: Descriptor Skip Length
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bit_offset: 18
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bit_size: 3
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fieldset/DMACIER:
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description: Channel interrupt enable register
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fields:
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- name: TIE
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description: Transmit Interrupt Enable
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bit_offset: 0
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bit_size: 1
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- name: TXSE
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description: Transmit Stopped Enable
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bit_offset: 1
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bit_size: 1
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- name: TBUE
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description: Transmit Buffer Unavailable Enable
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bit_offset: 2
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bit_size: 1
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- name: RIE
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description: Receive Interrupt Enable
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bit_offset: 6
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bit_size: 1
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- name: RBUE
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description: Receive Buffer Unavailable Enable
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bit_offset: 7
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bit_size: 1
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- name: RSE
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description: Receive Stopped Enable
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bit_offset: 8
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bit_size: 1
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- name: RWTE
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description: Receive Watchdog Timeout Enable
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bit_offset: 9
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bit_size: 1
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- name: ETIE
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description: Early Transmit Interrupt Enable
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bit_offset: 10
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bit_size: 1
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- name: ERIE
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description: Early Receive Interrupt Enable
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bit_offset: 11
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bit_size: 1
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- name: FBEE
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description: Fatal Bus Error Enable
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bit_offset: 12
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bit_size: 1
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- name: CDEE
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description: Context Descriptor Error Enable
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bit_offset: 13
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bit_size: 1
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- name: AIE
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description: Abnormal Interrupt Summary Enable
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bit_offset: 14
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bit_size: 1
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- name: NIE
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description: Normal Interrupt Summary Enable
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bit_offset: 15
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bit_size: 1
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fieldset/DMACMFCR:
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description: Channel missed frame count register
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fields:
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- name: MFC
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description: Dropped Packet Counters
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bit_offset: 0
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bit_size: 11
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- name: MFCO
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description: Overflow status of the MFC Counter
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bit_offset: 15
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bit_size: 1
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fieldset/DMACRxCR:
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description: Channel receive control register
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fields:
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- name: SR
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description: Start or Stop Receive Command
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bit_offset: 0
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bit_size: 1
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- name: RBSZ
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description: Receive Buffer size
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bit_offset: 1
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bit_size: 14
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- name: RXPBL
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description: RXPBL
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bit_offset: 16
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bit_size: 6
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- name: RPF
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description: DMA Rx Channel Packet Flush
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bit_offset: 31
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bit_size: 1
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fieldset/DMACRxDLAR:
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description: Channel Rx descriptor list address register
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fields:
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- name: RDESLA
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description: Start of Receive List
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bit_offset: 2
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bit_size: 30
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fieldset/DMACRxDTPR:
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description: Channel Rx descriptor tail pointer register
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fields:
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- name: RDT
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description: Receive Descriptor Tail Pointer
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bit_offset: 2
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bit_size: 30
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fieldset/DMACRxIWTR:
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description: Channel Rx interrupt watchdog timer register
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fields:
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- name: RWT
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description: Receive Interrupt Watchdog Timer Count
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bit_offset: 0
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bit_size: 8
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fieldset/DMACRxRLR:
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description: Channel Rx descriptor ring length register
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fields:
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- name: RDRL
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description: Receive Descriptor Ring Length
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bit_offset: 0
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bit_size: 10
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fieldset/DMACSR:
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description: Channel status register
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fields:
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- name: TI
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description: Transmit Interrupt
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bit_offset: 0
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bit_size: 1
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- name: TPS
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description: Transmit Process Stopped
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bit_offset: 1
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bit_size: 1
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- name: TBU
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description: Transmit Buffer Unavailable
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bit_offset: 2
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bit_size: 1
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- name: RI
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description: Receive Interrupt
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bit_offset: 6
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bit_size: 1
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- name: RBU
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description: Receive Buffer Unavailable
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bit_offset: 7
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bit_size: 1
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- name: RPS
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description: Receive Process Stopped
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bit_offset: 8
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bit_size: 1
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- name: RWT
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description: Receive Watchdog Timeout
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bit_offset: 9
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bit_size: 1
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- name: ET
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description: Early Transmit Interrupt
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bit_offset: 10
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bit_size: 1
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- name: ER
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description: Early Receive Interrupt
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bit_offset: 11
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bit_size: 1
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- name: FBE
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description: Fatal Bus Error
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bit_offset: 12
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bit_size: 1
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- name: CDE
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description: Context Descriptor Error
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bit_offset: 13
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bit_size: 1
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- name: AIS
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description: Abnormal Interrupt Summary
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bit_offset: 14
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bit_size: 1
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- name: NIS
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description: Normal Interrupt Summary
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bit_offset: 15
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bit_size: 1
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- name: TEB
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description: Tx DMA Error Bits
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bit_offset: 16
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bit_size: 3
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- name: REB
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description: Rx DMA Error Bits
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bit_offset: 19
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bit_size: 3
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fieldset/DMACTxCR:
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description: Channel transmit control register
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fields:
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- name: ST
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description: Start or Stop Transmission Command
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bit_offset: 0
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bit_size: 1
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- name: OSF
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description: Operate on Second Packet
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bit_offset: 4
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bit_size: 1
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- name: TSE
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description: TCP Segmentation Enabled
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bit_offset: 12
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bit_size: 1
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- name: TXPBL
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description: Transmit Programmable Burst Length
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bit_offset: 16
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bit_size: 6
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fieldset/DMACTxDLAR:
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description: Channel Tx descriptor list address register
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fields:
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- name: TDESLA
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description: Start of Transmit List
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bit_offset: 2
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bit_size: 30
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fieldset/DMACTxDTPR:
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description: Channel Tx descriptor tail pointer register
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fields:
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- name: TDT
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description: Transmit Descriptor Tail Pointer
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bit_offset: 2
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bit_size: 30
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fieldset/DMACTxRLR:
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description: Channel Tx descriptor ring length register
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fields:
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- name: TDRL
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description: Transmit Descriptor Ring Length
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bit_offset: 0
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bit_size: 10
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fieldset/DMADSR:
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description: Debug status register
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fields:
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- name: AXWHSTS
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description: AHB Master Write Channel
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bit_offset: 0
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bit_size: 1
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- name: RPS0
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description: DMA Channel Receive Process State
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bit_offset: 8
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bit_size: 4
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- name: TPS0
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description: DMA Channel Transmit Process State
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bit_offset: 12
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bit_size: 4
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fieldset/DMAISR:
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description: Interrupt status register
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fields:
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- name: DC0IS
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description: DMA Channel Interrupt Status
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bit_offset: 0
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bit_size: 1
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- name: MTLIS
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description: MTL Interrupt Status
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bit_offset: 16
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bit_size: 1
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- name: MACIS
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description: MAC Interrupt Status
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bit_offset: 17
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bit_size: 1
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fieldset/DMAMR:
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description: DMA mode register
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fields:
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- name: SWR
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description: Software Reset
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bit_offset: 0
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bit_size: 1
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- name: DA
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description: DMA Tx or Rx Arbitration Scheme
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bit_offset: 1
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bit_size: 1
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- name: TXPR
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description: Transmit priority
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bit_offset: 11
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bit_size: 1
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- name: PR
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description: Priority ratio
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bit_offset: 12
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bit_size: 3
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- name: INTM
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description: Interrupt Mode
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bit_offset: 16
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bit_size: 2
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fieldset/DMASBMR:
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description: System bus mode register
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fields:
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- name: FB
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description: Fixed Burst Length
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bit_offset: 0
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bit_size: 1
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- name: AAL
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description: Address-Aligned Beats
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bit_offset: 12
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bit_size: 1
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- name: MB
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description: Mixed Burst
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bit_offset: 14
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bit_size: 1
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- name: RB
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description: Rebuild INCRx Burst
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bit_offset: 15
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bit_size: 1
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