178 lines
4.3 KiB
YAML
178 lines
4.3 KiB
YAML
block/TIM_BASIC:
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description: Basic timers
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items:
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- name: CR1
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description: control register 1
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byte_offset: 0
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fieldset: CR1_BASIC
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- name: CR2
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description: control register 2
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byte_offset: 4
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fieldset: CR2_BASIC
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- name: DIER
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description: DMA/Interrupt enable register
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byte_offset: 12
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fieldset: DIER_BASIC
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- name: SR
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description: status register
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byte_offset: 16
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fieldset: SR_BASIC
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- name: EGR
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description: event generation register
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byte_offset: 20
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access: Write
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fieldset: EGR_BASIC
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- name: CNT
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description: counter
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byte_offset: 36
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fieldset: CNT_BASIC
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- name: PSC
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description: prescaler
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byte_offset: 40
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fieldset: PSC_BASIC
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- name: ARR
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description: auto-reload register (Dither mode disabled)
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byte_offset: 44
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fieldset: ARR_BASIC
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- name: ARR_DITHER
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description: auto-reload register (Dither mode enabled)
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byte_offset: 44
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fieldset: ARR_DITHER_BASIC
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fieldset/ARR_BASIC:
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description: auto-reload register (Dither mode disabled)
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fields:
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- name: ARR
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description: Auto-reload value
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bit_offset: 0
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bit_size: 16
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fieldset/ARR_DITHER_BASIC:
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description: auto-reload register (Dither mode enabled)
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fields:
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- name: DITHER
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description: Dither value
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bit_offset: 0
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bit_size: 4
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- name: ARR
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description: Auto-reload value
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bit_offset: 4
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bit_size: 16
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fieldset/CNT_BASIC:
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description: counter
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fields:
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- name: CNT
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description: counter value
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bit_offset: 0
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bit_size: 16
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- name: UIFCPY
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description: UIF copy
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bit_offset: 31
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bit_size: 1
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fieldset/CR1_BASIC:
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description: control register 1
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fields:
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- name: CEN
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description: Counter enable
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bit_offset: 0
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bit_size: 1
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- name: UDIS
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description: Update disable
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bit_offset: 1
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bit_size: 1
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- name: URS
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description: Update request source
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bit_offset: 2
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bit_size: 1
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enum: URS
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- name: OPM
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description: One-pulse mode enbaled
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bit_offset: 3
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bit_size: 1
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- name: ARPE
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description: Auto-reload preload enable
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bit_offset: 7
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bit_size: 1
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- name: UIFREMAP
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description: UIF status bit remapping enable
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bit_offset: 11
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bit_size: 1
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- name: DITHEN
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description: Dithering enable
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bit_offset: 12
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bit_size: 1
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fieldset/CR2_BASIC:
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description: control register 2
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fields:
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- name: MMS
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description: Master mode selection
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bit_offset: 4
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bit_size: 3
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enum: MMS
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fieldset/DIER_BASIC:
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description: DMA/Interrupt enable register
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fields:
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- name: UIE
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description: Update interrupt enable
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bit_offset: 0
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bit_size: 1
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- name: UDE
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description: Update DMA request enable
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bit_offset: 8
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bit_size: 1
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fieldset/EGR_BASIC:
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description: event generation register
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fields:
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- name: UG
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description: Update generation
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bit_offset: 0
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bit_size: 1
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fieldset/PSC_BASIC:
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description: prescaler
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fields:
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- name: PSC
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description: Prescaler value
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bit_offset: 0
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bit_size: 16
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fieldset/SR_BASIC:
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description: status register
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fields:
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- name: UIF
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description: Update interrupt flag
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bit_offset: 0
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bit_size: 1
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enum/MMS:
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bit_size: 3
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variants:
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- name: Reset
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description: The UG bit from the TIMx_EGR register is used as trigger output
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value: 0
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- name: Enable
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description: The counter enable signal, CNT_EN, is used as trigger output
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value: 1
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- name: Update
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description: The update event is selected as trigger output
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value: 2
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- name: ComparePulse
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description: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
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value: 3
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- name: CompareOC1
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description: OC1REF signal is used as trigger output
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value: 4
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- name: CompareOC2
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description: OC2REF signal is used as trigger output
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value: 5
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- name: CompareOC3
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description: OC3REF signal is used as trigger output
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value: 6
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- name: CompareOC4
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description: OC4REF signal is used as trigger output
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value: 7
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enum/URS:
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bit_size: 1
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variants:
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- name: AnyEvent
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description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
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value: 0
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- name: CounterOnly
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description: Only counter overflow/underflow generates an update interrupt or DMA request
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value: 1
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