143 lines
3.3 KiB
YAML
143 lines
3.3 KiB
YAML
---
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block/IPCC:
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description: IPCC
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items:
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- name: CPU
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description: CPU specific registers
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byte_offset: 0
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array:
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len: 2
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stride: 16
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block/IPCC_CPU:
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description: IPCC
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items:
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- name: CR
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description: Control register CPUx
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byte_offset: 0
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fieldset: C1CR
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- name: MR
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description: Mask register CPUx
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byte_offset: 4
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fieldset: C1MR
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- name: SCR
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description: Status Set or Clear register CPU1
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byte_offset: 8
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access: Write
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fieldset: C1SCR
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- name: SR
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description: CPU1 to CPU2 status register
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byte_offset: 12
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access: Read
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fieldset: C1TO2SR
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fieldset/C1CR:
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description: Control register CPU1
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fields:
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- name: RXOIE
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description: processor 1 Receive channel occupied interrupt enable
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bit_offset: 0
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bit_size: 1
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- name: TXFIE
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description: processor 1 Transmit channel free interrupt enable
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bit_offset: 16
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bit_size: 1
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fieldset/C1MR:
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description: Mask register CPU1
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fields:
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- name: CHOM
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description: processor 1 Receive channel x occupied interrupt enable
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bit_offset: 0
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bit_size: 1
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array:
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len: 6
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stride: 1
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- name: CHFM
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description: processor 1 Transmit channel x free interrupt mask
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bit_offset: 16
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bit_size: 1
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array:
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len: 6
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stride: 1
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fieldset/C1SCR:
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description: Status Set or Clear register CPU1
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fields:
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- name: CHC
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description: processor 1 Receive channel x status clear
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bit_offset: 0
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bit_size: 1
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array:
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len: 6
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stride: 1
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- name: CHS
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description: processor 1 Transmit channel x status set
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bit_offset: 16
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bit_size: 1
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array:
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len: 6
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stride: 1
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fieldset/C1TO2SR:
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description: CPU1 to CPU2 status register
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fields:
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- name: CHF
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description: processor 1 transmit to process 2 Receive channel x status flag
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bit_offset: 0
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bit_size: 1
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array:
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len: 6
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stride: 1
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fieldset/C2CR:
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description: Control register CPU2
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fields:
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- name: RXOIE
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description: processor 2 Receive channel occupied interrupt enable
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bit_offset: 0
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bit_size: 1
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- name: TXFIE
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description: processor 2 Transmit channel free interrupt enable
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bit_offset: 16
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bit_size: 1
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fieldset/C2MR:
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description: Mask register CPU2
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fields:
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- name: CHOM
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description: processor 2 Receive channel x occupied interrupt enable
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bit_offset: 0
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bit_size: 1
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array:
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len: 6
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stride: 1
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- name: CHFM
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description: processor 2 Transmit channel 1 free interrupt mask
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bit_offset: 16
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bit_size: 1
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array:
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len: 6
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stride: 1
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fieldset/C2SCR:
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description: Status Set or Clear register CPU2
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fields:
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- name: CHC
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description: processor 2 Receive channel x status clear
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bit_offset: 0
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bit_size: 1
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array:
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len: 6
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stride: 1
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- name: CHS
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description: processor 2 Transmit channel 1 status set
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bit_offset: 16
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bit_size: 1
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array:
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len: 6
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stride: 1
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fieldset/C2TOC1SR:
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description: CPU2 to CPU1 status register
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fields:
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- name: CHF
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description: processor 2 transmit to process 1 Receive channel x status flag
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bit_offset: 0
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bit_size: 1
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array:
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len: 6
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stride: 1
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