160 lines
2.1 KiB
YAML
160 lines
2.1 KiB
YAML
PA0:
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COMP1_OUT: 7
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LPTIM1_IN1: 1
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LPUART1_RX: 6
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TIM2_CH1: 2
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TIM2_ETR: 5
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USART2_CTS: 4
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USART2_RX: 0
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PA1:
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EVENTOUT: 0
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I2C1_SMBA: 3
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LPTIM1_IN2: 1
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LPUART1_TX: 6
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TIM21_ETR: 5
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TIM2_CH2: 2
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USART2_DE: 4
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USART2_RTS: 4
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PA10:
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COMP1_OUT: 7
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I2C1_SDA: 1
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RTC_REFIN: 2
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TIM21_CH1: 0
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TIM2_CH3: 5
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USART2_RX: 4
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PA11:
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COMP1_OUT: 7
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EVENTOUT: 2
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LPTIM1_OUT: 1
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SPI1_MISO: 0
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TIM21_CH2: 5
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USART2_CTS: 4
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PA12:
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COMP2_OUT: 7
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EVENTOUT: 2
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SPI1_MOSI: 0
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USART2_DE: 4
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USART2_RTS: 4
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PA13:
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COMP1_OUT: 7
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I2C1_SDA: 3
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LPTIM1_ETR: 1
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LPUART1_RX: 6
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SPI1_SCK: 5
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SYS_SWDIO: 0
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PA14:
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COMP2_OUT: 7
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I2C1_SMBA: 3
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LPTIM1_OUT: 1
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LPUART1_TX: 6
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SPI1_MISO: 5
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SYS_SWCLK: 0
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USART2_TX: 4
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PA15:
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EVENTOUT: 3
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SPI1_NSS: 0
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TIM2_CH1: 5
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TIM2_ETR: 2
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USART2_RX: 4
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PA2:
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COMP2_OUT: 7
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LPUART1_TX: 6
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TIM21_CH1: 0
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TIM2_CH3: 2
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USART2_TX: 4
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PA3:
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LPUART1_RX: 6
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TIM21_CH2: 0
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TIM2_CH4: 2
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USART2_RX: 4
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PA4:
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COMP2_OUT: 7
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I2C1_SCL: 3
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LPTIM1_ETR: 2
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LPTIM1_IN1: 1
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LPUART1_TX: 6
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SPI1_NSS: 0
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TIM2_ETR: 5
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USART2_CK: 4
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PA5:
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LPTIM1_IN2: 1
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SPI1_SCK: 0
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TIM2_CH1: 5
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TIM2_ETR: 2
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PA6:
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COMP1_OUT: 7
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EVENTOUT: 6
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LPTIM1_ETR: 1
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LPUART1_CTS: 4
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SPI1_MISO: 0
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PA7:
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COMP2_OUT: 7
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EVENTOUT: 6
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LPTIM1_OUT: 1
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SPI1_MOSI: 0
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TIM21_ETR: 5
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USART2_CTS: 4
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PA8:
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EVENTOUT: 3
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LPTIM1_IN1: 2
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RCC_MCO: 0
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TIM2_CH1: 5
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USART2_CK: 4
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PA9:
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COMP1_OUT: 7
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I2C1_SCL: 1
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LPTIM1_OUT: 2
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RCC_MCO: 0
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TIM21_CH2: 5
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USART2_TX: 4
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PB0:
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EVENTOUT: 0
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SPI1_MISO: 1
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TIM2_CH2: 2
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TIM2_CH3: 5
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USART2_DE: 4
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USART2_RTS: 4
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PB1:
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LPTIM1_IN1: 2
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LPUART1_DE: 4
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LPUART1_RTS: 4
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SPI1_MOSI: 1
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TIM2_CH4: 5
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USART2_CK: 0
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PB2:
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LPTIM1_OUT: 2
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PB3:
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EVENTOUT: 4
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SPI1_SCK: 0
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TIM2_CH2: 2
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PB4:
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EVENTOUT: 2
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SPI1_MISO: 0
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PB5:
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I2C1_SMBA: 3
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LPTIM1_IN1: 2
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SPI1_MOSI: 0
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TIM21_CH1: 5
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PB6:
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I2C1_SCL: 1
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LPTIM1_ETR: 2
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LPUART1_TX: 6
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TIM2_CH3: 5
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USART2_TX: 0
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PB7:
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I2C1_SDA: 1
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LPTIM1_IN2: 2
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LPUART1_RX: 6
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TIM2_CH4: 5
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USART2_RX: 0
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PB8:
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EVENTOUT: 2
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I2C1_SCL: 4
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SPI1_NSS: 5
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USART2_TX: 0
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PB9: {}
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PC13: {}
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PC14: {}
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PC15: {}
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PI8: {}
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