1717 lines
39 KiB
YAML
1717 lines
39 KiB
YAML
block/DSIHOST:
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description: DSIHOST1.
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items:
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- name: VR
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description: DSI Host version register.
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byte_offset: 0
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access: Read
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fieldset: VR
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- name: CR
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description: DSI Host control register.
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byte_offset: 4
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fieldset: CR
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- name: CCR
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description: DSI Host clock control register.
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byte_offset: 8
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fieldset: CCR
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- name: LVCIDR
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description: DSI Host LTDC VCID register.
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byte_offset: 12
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fieldset: LVCIDR
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- name: LCOLCR
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description: DSI Host LTDC color coding register.
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byte_offset: 16
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fieldset: LCOLCR
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- name: LPCR
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description: DSI Host LTDC polarity configuration register.
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byte_offset: 20
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fieldset: LPCR
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- name: LPMCR
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description: DSI Host low-power mode configuration register.
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byte_offset: 24
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fieldset: LPMCR
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- name: PCR
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description: DSI Host protocol configuration register.
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byte_offset: 44
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fieldset: PCR
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- name: GVCIDR
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description: DSI Host generic VCID register.
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byte_offset: 48
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access: Read
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fieldset: GVCIDR
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- name: MCR
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description: DSI Host mode configuration register.
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byte_offset: 52
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fieldset: MCR
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- name: VMCR
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description: DSI Host video mode configuration register.
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byte_offset: 56
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fieldset: VMCR
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- name: VPCR
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description: DSI Host video packet configuration register.
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byte_offset: 60
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fieldset: VPCR
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- name: VCCR
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description: DSI Host video chunks configuration register.
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byte_offset: 64
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fieldset: VCCR
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- name: VNPCR
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description: DSI Host video null packet configuration register.
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byte_offset: 68
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fieldset: VNPCR
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- name: VHSACR
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description: DSI Host video HSA configuration register.
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byte_offset: 72
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fieldset: VHSACR
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- name: VHBPCR
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description: DSI Host video HBP configuration register.
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byte_offset: 76
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fieldset: VHBPCR
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- name: VLCR
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description: DSI Host video line configuration register.
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byte_offset: 80
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fieldset: VLCR
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- name: VVSACR
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description: DSI Host video VSA configuration register.
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byte_offset: 84
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fieldset: VVSACR
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- name: VVBPCR
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description: DSI Host video VBP configuration register.
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byte_offset: 88
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fieldset: VVBPCR
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- name: VVFPCR
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description: DSI Host video VFP configuration register.
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byte_offset: 92
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fieldset: VVFPCR
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- name: VVACR
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description: DSI Host video VA configuration register.
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byte_offset: 96
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fieldset: VVACR
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- name: LCCR
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description: DSI Host LTDC command configuration register.
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byte_offset: 100
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fieldset: LCCR
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- name: CMCR
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description: DSI Host command mode configuration register.
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byte_offset: 104
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fieldset: CMCR
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- name: GHCR
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description: DSI Host generic header configuration register.
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byte_offset: 108
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fieldset: GHCR
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- name: GPDR
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description: DSI Host generic payload data register.
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byte_offset: 112
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fieldset: GPDR
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- name: GPSR
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description: DSI Host generic packet status register.
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byte_offset: 116
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access: Read
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fieldset: GPSR
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- name: TCCR0
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description: DSI Host timeout counter configuration register 0.
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byte_offset: 120
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fieldset: TCCR0
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- name: TCCR1
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description: DSI Host timeout counter configuration register 1.
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byte_offset: 124
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fieldset: TCCR1
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- name: TCCR2
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description: DSI Host timeout counter configuration register 2.
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byte_offset: 128
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fieldset: TCCR2
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- name: TCCR3
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description: DSI Host timeout counter configuration register 3.
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byte_offset: 132
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fieldset: TCCR3
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- name: TCCR4
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description: DSI Host timeout counter configuration register 4.
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byte_offset: 136
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fieldset: TCCR4
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- name: TCCR5
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description: DSI Host timeout counter configuration register 5.
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byte_offset: 140
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fieldset: TCCR5
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- name: CLCR
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description: DSI Host clock lane configuration register.
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byte_offset: 148
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fieldset: CLCR
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- name: CLTCR
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description: DSI Host clock lane timer configuration register.
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byte_offset: 152
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fieldset: CLTCR
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- name: DLTCR
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description: DSI Host data lane timer configuration register.
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byte_offset: 156
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fieldset: DLTCR
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- name: PCTLR
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description: DSI Host PHY control register.
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byte_offset: 160
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fieldset: PCTLR
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- name: PCONFR
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description: DSI Host PHY configuration register.
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byte_offset: 164
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fieldset: PCONFR
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- name: PUCR
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description: DSI Host PHY ULPS control register.
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byte_offset: 168
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fieldset: PUCR
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- name: PTTCR
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description: DSI Host PHY TX triggers configuration register.
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byte_offset: 172
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fieldset: PTTCR
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- name: PSR
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description: DSI Host PHY status register.
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byte_offset: 176
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access: Read
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fieldset: PSR
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- name: ISR0
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description: DSI Host interrupt and status register 0.
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byte_offset: 188
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access: Read
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fieldset: ISR0
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- name: ISR1
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description: DSI Host interrupt and status register 1.
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byte_offset: 192
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access: Read
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fieldset: ISR1
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- name: IER0
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description: DSI Host interrupt enable register 0.
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byte_offset: 196
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fieldset: IER0
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- name: IER1
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description: DSI Host interrupt enable register 1.
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byte_offset: 200
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fieldset: IER1
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- name: FIR0
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description: DSI Host force interrupt register 0.
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byte_offset: 216
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access: Write
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fieldset: FIR0
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- name: FIR1
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description: DSI Host force interrupt register 1.
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byte_offset: 220
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access: Write
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fieldset: FIR1
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- name: DLTRCR
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description: DSI Host data lane timer read configuration register.
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byte_offset: 244
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fieldset: DLTRCR
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- name: VSCR
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description: DSI Host video shadow control register.
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byte_offset: 256
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fieldset: VSCR
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- name: LCVCIDR
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description: DSI Host LTDC current VCID register.
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byte_offset: 268
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fieldset: LCVCIDR
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- name: LCCCR
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description: DSI Host LTDC current color coding register.
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byte_offset: 272
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access: Read
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fieldset: LCCCR
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- name: LPMCCR
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description: DSI Host low-power mode current configuration register.
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byte_offset: 280
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access: Read
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fieldset: LPMCCR
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- name: VMCCR
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description: DSI Host video mode current configuration register.
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byte_offset: 312
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access: Read
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fieldset: VMCCR
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- name: VPCCR
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description: DSI Host video packet current configuration register.
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byte_offset: 316
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access: Read
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fieldset: VPCCR
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- name: VCCCR
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description: DSI Host video chunks current configuration register.
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byte_offset: 320
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access: Read
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fieldset: VCCCR
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- name: VNPCCR
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description: DSI Host video null packet current configuration register.
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byte_offset: 324
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access: Read
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fieldset: VNPCCR
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- name: VHSACCR
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description: DSI Host video HSA current configuration register.
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byte_offset: 328
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access: Read
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fieldset: VHSACCR
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- name: VHBPCCR
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description: DSI Host video HBP current configuration register.
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byte_offset: 332
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access: Read
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fieldset: VHBPCCR
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- name: VLCCR
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description: DSI Host video line current configuration register.
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byte_offset: 336
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access: Read
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fieldset: VLCCR
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- name: VVSACCR
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description: DSI Host video VSA current configuration register.
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byte_offset: 340
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access: Read
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fieldset: VVSACCR
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- name: VVBPCCR
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description: DSI Host video VBP current configuration register.
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byte_offset: 344
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access: Read
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fieldset: VVBPCCR
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- name: VVFPCCR
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description: DSI Host video VFP current configuration register.
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byte_offset: 348
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access: Read
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fieldset: VVFPCCR
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- name: VVACCR
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description: DSI Host video VA current configuration register.
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byte_offset: 352
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access: Read
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fieldset: VVACCR
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- name: WCFGR
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description: DSI wrapper configuration register.
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byte_offset: 1024
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fieldset: WCFGR
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- name: WCR
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description: DSI wrapper control register.
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byte_offset: 1028
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fieldset: WCR
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- name: WIER
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description: DSI wrapper interrupt enable register.
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byte_offset: 1032
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fieldset: WIER
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- name: WISR
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description: DSI wrapper interrupt and status register.
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byte_offset: 1036
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access: Read
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fieldset: WISR
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- name: WIFCR
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description: DSI wrapper interrupt flag clear register.
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byte_offset: 1040
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access: Write
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fieldset: WIFCR
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- name: WPCR0
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description: DSI wrapper PHY configuration register 0.
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byte_offset: 1048
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fieldset: WPCR0
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- name: WPCR1
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description: This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and CR.EN = 0).
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byte_offset: 1052
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fieldset: WPCR1
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- name: WRPCR
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description: DSI wrapper regulator and PLL control register.
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byte_offset: 1072
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fieldset: WRPCR
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- name: HWCFGR
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description: DSI Host hardware configuration register.
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byte_offset: 2032
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access: Read
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fieldset: HWCFGR
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- name: VERR
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description: DSI Host version register.
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byte_offset: 2036
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access: Read
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fieldset: VERR
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- name: IPIDR
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description: DSI Host identification register.
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byte_offset: 2040
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access: Read
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fieldset: IPIDR
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- name: SIDR
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description: DSI Host size identification register.
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byte_offset: 2044
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access: Read
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fieldset: SIDR
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fieldset/CCR:
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description: DSI Host clock control register.
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fields:
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- name: TXECKDIV
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description: TXECKDIV.
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bit_offset: 0
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bit_size: 8
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- name: TOCKDIV
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description: TOCKDIV.
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bit_offset: 8
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bit_size: 8
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fieldset/CLCR:
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description: DSI Host clock lane configuration register.
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fields:
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- name: DPCC
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description: DPCC.
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bit_offset: 0
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bit_size: 1
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- name: ACR
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description: ACR.
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bit_offset: 1
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bit_size: 1
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fieldset/CLTCR:
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description: DSI Host clock lane timer configuration register.
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fields:
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- name: LP2HS_TIME
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description: LP2HS_TIME.
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bit_offset: 0
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bit_size: 10
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- name: HS2LP_TIME
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description: HS2LP_TIME.
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bit_offset: 16
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bit_size: 10
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fieldset/CMCR:
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description: DSI Host command mode configuration register.
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fields:
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- name: TEARE
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description: TEARE.
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bit_offset: 0
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bit_size: 1
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- name: ARE
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description: ARE.
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bit_offset: 1
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bit_size: 1
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- name: GSW0TX
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description: GSW0TX.
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bit_offset: 8
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bit_size: 1
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- name: GSW1TX
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description: GSW1TX.
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bit_offset: 9
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bit_size: 1
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- name: GSW2TX
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description: GSW2TX.
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bit_offset: 10
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bit_size: 1
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- name: GSR0TX
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description: GSR0TX.
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bit_offset: 11
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bit_size: 1
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- name: GSR1TX
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description: GSR1TX.
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bit_offset: 12
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bit_size: 1
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- name: GSR2TX
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description: GSR2TX.
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bit_offset: 13
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bit_size: 1
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- name: GLWTX
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description: GLWTX.
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bit_offset: 14
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bit_size: 1
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- name: DSW0TX
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description: DSW0TX.
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bit_offset: 16
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bit_size: 1
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- name: DSW1TX
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description: DSW1TX.
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bit_offset: 17
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bit_size: 1
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- name: DSR0TX
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description: DSR0TX.
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bit_offset: 18
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bit_size: 1
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- name: DLWTX
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description: DLWTX.
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bit_offset: 19
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bit_size: 1
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- name: MRDPS
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description: MRDPS.
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bit_offset: 24
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bit_size: 1
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fieldset/CR:
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description: DSI Host control register.
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fields:
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- name: EN
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description: EN.
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bit_offset: 0
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bit_size: 1
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fieldset/DLTCR:
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description: DSI Host data lane timer configuration register.
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fields:
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- name: LP2HS_TIME
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description: LP2HS_TIME.
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bit_offset: 0
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bit_size: 10
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- name: HS2LP_TIME
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description: HS2LP_TIME.
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bit_offset: 16
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bit_size: 10
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fieldset/DLTRCR:
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description: DSI Host data lane timer read configuration register.
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fields:
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- name: MRD_TIME
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description: MRD_TIME.
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bit_offset: 0
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bit_size: 15
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fieldset/FIR0:
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description: DSI Host force interrupt register 0.
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fields:
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- name: FAE0
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description: FAE0.
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bit_offset: 0
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bit_size: 1
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- name: FAE1
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description: FAE1.
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bit_offset: 1
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bit_size: 1
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- name: FAE2
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description: FAE2.
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bit_offset: 2
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bit_size: 1
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- name: FAE3
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description: FAE3.
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bit_offset: 3
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bit_size: 1
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- name: FAE4
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description: FAE4.
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bit_offset: 4
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bit_size: 1
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- name: FAE5
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description: FAE5.
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bit_offset: 5
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bit_size: 1
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- name: FAE6
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description: FAE6.
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bit_offset: 6
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bit_size: 1
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- name: FAE7
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description: FAE7.
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bit_offset: 7
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bit_size: 1
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- name: FAE8
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description: FAE8.
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bit_offset: 8
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bit_size: 1
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- name: FAE9
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description: FAE9.
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bit_offset: 9
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bit_size: 1
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- name: FAE10
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description: FAE10.
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bit_offset: 10
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bit_size: 1
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- name: FAE11
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description: FAE11.
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bit_offset: 11
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bit_size: 1
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- name: FAE12
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description: FAE12.
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bit_offset: 12
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bit_size: 1
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- name: FAE13
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description: FAE13.
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bit_offset: 13
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bit_size: 1
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- name: FAE14
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description: FAE14.
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bit_offset: 14
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bit_size: 1
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- name: FAE15
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description: FAE15.
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bit_offset: 15
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bit_size: 1
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- name: FPE0
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description: FPE0.
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bit_offset: 16
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bit_size: 1
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- name: FPE1
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description: FPE1.
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bit_offset: 17
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bit_size: 1
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- name: FPE2
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description: FPE2.
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bit_offset: 18
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bit_size: 1
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- name: FPE3
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description: FPE3.
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bit_offset: 19
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bit_size: 1
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- name: FPE4
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description: FPE4.
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bit_offset: 20
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bit_size: 1
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fieldset/FIR1:
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description: DSI Host force interrupt register 1.
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fields:
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- name: FTOHSTX
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description: FTOHSTX.
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bit_offset: 0
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bit_size: 1
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- name: FTOLPRX
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description: FTOLPRX.
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bit_offset: 1
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bit_size: 1
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- name: FECCSE
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description: FECCSE.
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bit_offset: 2
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bit_size: 1
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- name: FECCME
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description: FECCME.
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bit_offset: 3
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bit_size: 1
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- name: FCRCE
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description: FCRCE.
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bit_offset: 4
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bit_size: 1
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- name: FPSE
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description: FPSE.
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bit_offset: 5
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bit_size: 1
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- name: FEOTPE
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description: FEOTPE.
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bit_offset: 6
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bit_size: 1
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- name: FLPWRE
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description: FLPWRE.
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bit_offset: 7
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bit_size: 1
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- name: FGCWRE
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description: FGCWRE.
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bit_offset: 8
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bit_size: 1
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- name: FGPWRE
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description: FGPWRE.
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bit_offset: 9
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bit_size: 1
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- name: FGPTXE
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description: FGPTXE.
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|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: FGPRDE
|
|
description: FGPRDE.
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: FGPRXE
|
|
description: FGPRXE.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
fieldset/GHCR:
|
|
description: DSI Host generic header configuration register.
|
|
fields:
|
|
- name: DT
|
|
description: DT.
|
|
bit_offset: 0
|
|
bit_size: 6
|
|
- name: VCID
|
|
description: VCID.
|
|
bit_offset: 6
|
|
bit_size: 2
|
|
- name: WCLSB
|
|
description: WCLSB.
|
|
bit_offset: 8
|
|
bit_size: 8
|
|
- name: WCMSB
|
|
description: WCMSB.
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
fieldset/GPDR:
|
|
description: DSI Host generic payload data register.
|
|
fields:
|
|
- name: DATA1
|
|
description: DATA1.
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
- name: DATA2
|
|
description: DATA2.
|
|
bit_offset: 8
|
|
bit_size: 8
|
|
- name: DATA3
|
|
description: DATA3.
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
- name: DATA4
|
|
description: DATA4.
|
|
bit_offset: 24
|
|
bit_size: 8
|
|
fieldset/GPSR:
|
|
description: DSI Host generic packet status register.
|
|
fields:
|
|
- name: CMDFE
|
|
description: CMDFE.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: CMDFF
|
|
description: CMDFF.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: PWRFE
|
|
description: PWRFE.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: PWRFF
|
|
description: PWRFF.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: PRDFE
|
|
description: PRDFE.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: PRDFF
|
|
description: PRDFF.
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: RCB
|
|
description: RCB.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
fieldset/GVCIDR:
|
|
description: DSI Host generic VCID register.
|
|
fields:
|
|
- name: VCID
|
|
description: VCID.
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
fieldset/HWCFGR:
|
|
description: DSI Host hardware configuration register.
|
|
fields:
|
|
- name: TECHNO
|
|
description: TECHNO.
|
|
bit_offset: 0
|
|
bit_size: 4
|
|
- name: FIFOSIZE
|
|
description: FIFOSIZE.
|
|
bit_offset: 4
|
|
bit_size: 12
|
|
fieldset/IER0:
|
|
description: DSI Host interrupt enable register 0.
|
|
fields:
|
|
- name: AE0IE
|
|
description: AE0IE.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: AE1IE
|
|
description: AE1IE.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: AE2IE
|
|
description: AE2IE.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: AE3IE
|
|
description: AE3IE.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: AE4IE
|
|
description: AE4IE.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: AE5IE
|
|
description: AE5IE.
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: AE6IE
|
|
description: AE6IE.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: AE7IE
|
|
description: AE7IE.
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: AE8IE
|
|
description: AE8IE.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: AE9IE
|
|
description: AE9IE.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: AE10IE
|
|
description: AE10IE.
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: AE11IE
|
|
description: AE11IE.
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: AE12IE
|
|
description: AE12IE.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: AE13IE
|
|
description: AE13IE.
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: AE14IE
|
|
description: AE14IE.
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: AE15IE
|
|
description: AE15IE.
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: PE0IE
|
|
description: PE0IE.
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: PE1IE
|
|
description: PE1IE.
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: PE2IE
|
|
description: PE2IE.
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: PE3IE
|
|
description: PE3IE.
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: PE4IE
|
|
description: PE4IE.
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
fieldset/IER1:
|
|
description: DSI Host interrupt enable register 1.
|
|
fields:
|
|
- name: TOHSTXIE
|
|
description: TOHSTXIE.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: TOLPRXIE
|
|
description: TOLPRXIE.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: ECCSEIE
|
|
description: ECCSEIE.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: ECCMEIE
|
|
description: ECCMEIE.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: CRCEIE
|
|
description: CRCEIE.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: PSEIE
|
|
description: PSEIE.
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: EOTPEIE
|
|
description: EOTPEIE.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: LPWREIE
|
|
description: LPWREIE.
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: GCWREIE
|
|
description: GCWREIE.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: GPWREIE
|
|
description: GPWREIE.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: GPTXEIE
|
|
description: GPTXEIE.
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: GPRDEIE
|
|
description: GPRDEIE.
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: GPRXEIE
|
|
description: GPRXEIE.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
fieldset/IPIDR:
|
|
description: DSI Host identification register.
|
|
fields:
|
|
- name: ID
|
|
description: ID.
|
|
bit_offset: 0
|
|
bit_size: 32
|
|
fieldset/ISR0:
|
|
description: DSI Host interrupt and status register 0.
|
|
fields:
|
|
- name: AE0
|
|
description: AE0.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: AE1
|
|
description: AE1.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: AE2
|
|
description: AE2.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: AE3
|
|
description: AE3.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: AE4
|
|
description: AE4.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: AE5
|
|
description: AE5.
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: AE6
|
|
description: AE6.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: AE7
|
|
description: AE7.
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: AE8
|
|
description: AE8.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: AE9
|
|
description: AE9.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: AE10
|
|
description: AE10.
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: AE11
|
|
description: AE11.
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: AE12
|
|
description: AE12.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: AE13
|
|
description: AE13.
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: AE14
|
|
description: AE14.
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: AE15
|
|
description: AE15.
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: PE0
|
|
description: PE0.
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: PE1
|
|
description: PE1.
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: PE2
|
|
description: PE2.
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: PE3
|
|
description: PE3.
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: PE4
|
|
description: PE4.
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
fieldset/ISR1:
|
|
description: DSI Host interrupt and status register 1.
|
|
fields:
|
|
- name: TOHSTX
|
|
description: TOHSTX.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: TOLPRX
|
|
description: TOLPRX.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: ECCSE
|
|
description: ECCSE.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: ECCME
|
|
description: ECCME.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: CRCE
|
|
description: CRCE.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: PSE
|
|
description: PSE.
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: EOTPE
|
|
description: EOTPE.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: LPWRE
|
|
description: LPWRE.
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: GCWRE
|
|
description: GCWRE.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: GPWRE
|
|
description: GPWRE.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: GPTXE
|
|
description: GPTXE.
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: GPRDE
|
|
description: GPRDE.
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: GPRXE
|
|
description: GPRXE.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
fieldset/LCCCR:
|
|
description: DSI Host LTDC current color coding register.
|
|
fields:
|
|
- name: COLC
|
|
description: COLC.
|
|
bit_offset: 0
|
|
bit_size: 4
|
|
- name: LPE
|
|
description: LPE.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
fieldset/LCCR:
|
|
description: DSI Host LTDC command configuration register.
|
|
fields:
|
|
- name: CMDSIZE
|
|
description: CMDSIZE.
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/LCOLCR:
|
|
description: DSI Host LTDC color coding register.
|
|
fields:
|
|
- name: COLC
|
|
description: COLC.
|
|
bit_offset: 0
|
|
bit_size: 4
|
|
- name: LPE
|
|
description: LPE.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
fieldset/LCVCIDR:
|
|
description: DSI Host LTDC current VCID register.
|
|
fields:
|
|
- name: VCID
|
|
description: VCID.
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
fieldset/LPCR:
|
|
description: DSI Host LTDC polarity configuration register.
|
|
fields:
|
|
- name: DEP
|
|
description: DEP.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: VSP
|
|
description: VSP.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: HSP
|
|
description: HSP.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
fieldset/LPMCCR:
|
|
description: DSI Host low-power mode current configuration register.
|
|
fields:
|
|
- name: VLPSIZE
|
|
description: VLPSIZE.
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
- name: LPSIZE
|
|
description: LPSIZE.
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
fieldset/LPMCR:
|
|
description: DSI Host low-power mode configuration register.
|
|
fields:
|
|
- name: VLPSIZE
|
|
description: VLPSIZE.
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
- name: LPSIZE
|
|
description: LPSIZE.
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
fieldset/LVCIDR:
|
|
description: DSI Host LTDC VCID register.
|
|
fields:
|
|
- name: VCID
|
|
description: VCID.
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
fieldset/MCR:
|
|
description: DSI Host mode configuration register.
|
|
fields:
|
|
- name: CMDM
|
|
description: CMDM.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
fieldset/PCONFR:
|
|
description: DSI Host PHY configuration register.
|
|
fields:
|
|
- name: NL
|
|
description: NL.
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: SW_TIME
|
|
description: SW_TIME.
|
|
bit_offset: 8
|
|
bit_size: 8
|
|
fieldset/PCR:
|
|
description: DSI Host protocol configuration register.
|
|
fields:
|
|
- name: ETTXE
|
|
description: ETTXE.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: ETRXE
|
|
description: ETRXE.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: BTAE
|
|
description: BTAE.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: ECCRXE
|
|
description: ECCRXE.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: CRCRXE
|
|
description: CRCRXE.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
fieldset/PCTLR:
|
|
description: DSI Host PHY control register.
|
|
fields:
|
|
- name: DEN
|
|
description: DEN.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: CKE
|
|
description: CKE.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
fieldset/PSR:
|
|
description: DSI Host PHY status register.
|
|
fields:
|
|
- name: PD
|
|
description: PD.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: PSSC
|
|
description: PSSC.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: UANC
|
|
description: UANC.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: PSS0
|
|
description: PSS0.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: UAN0
|
|
description: UAN0.
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: RUE0
|
|
description: RUE0.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: PSS1
|
|
description: PSS1.
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: UAN1
|
|
description: UAN1.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
fieldset/PTTCR:
|
|
description: DSI Host PHY TX triggers configuration register.
|
|
fields:
|
|
- name: TX_TRIG
|
|
description: TX_TRIG.
|
|
bit_offset: 0
|
|
bit_size: 4
|
|
fieldset/PUCR:
|
|
description: DSI Host PHY ULPS control register.
|
|
fields:
|
|
- name: URCL
|
|
description: URCL.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: UECL
|
|
description: UECL.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: URDL
|
|
description: URDL.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: UEDL
|
|
description: UEDL.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
fieldset/SIDR:
|
|
description: DSI Host size identification register.
|
|
fields:
|
|
- name: SID
|
|
description: SID.
|
|
bit_offset: 0
|
|
bit_size: 32
|
|
fieldset/TCCR0:
|
|
description: DSI Host timeout counter configuration register 0.
|
|
fields:
|
|
- name: LPRX_TOCNT
|
|
description: LPRX_TOCNT.
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
- name: HSTX_TOCNT
|
|
description: HSTX_TOCNT.
|
|
bit_offset: 16
|
|
bit_size: 16
|
|
fieldset/TCCR1:
|
|
description: DSI Host timeout counter configuration register 1.
|
|
fields:
|
|
- name: HSRD_TOCNT
|
|
description: HSRD_TOCNT.
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/TCCR2:
|
|
description: DSI Host timeout counter configuration register 2.
|
|
fields:
|
|
- name: LPRD_TOCNT
|
|
description: LPRD_TOCNT.
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/TCCR3:
|
|
description: DSI Host timeout counter configuration register 3.
|
|
fields:
|
|
- name: HSWR_TOCNT
|
|
description: HSWR_TOCNT.
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
- name: PM
|
|
description: PM.
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
fieldset/TCCR4:
|
|
description: DSI Host timeout counter configuration register 4.
|
|
fields:
|
|
- name: LPWR_TOCNT
|
|
description: LPWR_TOCNT.
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/TCCR5:
|
|
description: DSI Host timeout counter configuration register 5.
|
|
fields:
|
|
- name: BTA_TOCNT
|
|
description: BTA_TOCNT.
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/VCCCR:
|
|
description: DSI Host video chunks current configuration register.
|
|
fields:
|
|
- name: NUMC
|
|
description: NUMC.
|
|
bit_offset: 0
|
|
bit_size: 13
|
|
fieldset/VCCR:
|
|
description: DSI Host video chunks configuration register.
|
|
fields:
|
|
- name: NUMC
|
|
description: NUMC.
|
|
bit_offset: 0
|
|
bit_size: 13
|
|
fieldset/VERR:
|
|
description: DSI Host version register.
|
|
fields:
|
|
- name: MINREV
|
|
description: MINREV.
|
|
bit_offset: 0
|
|
bit_size: 4
|
|
- name: MAJREV
|
|
description: MAJREV.
|
|
bit_offset: 4
|
|
bit_size: 4
|
|
fieldset/VHBPCCR:
|
|
description: DSI Host video HBP current configuration register.
|
|
fields:
|
|
- name: HBP
|
|
description: HBP.
|
|
bit_offset: 0
|
|
bit_size: 12
|
|
fieldset/VHBPCR:
|
|
description: DSI Host video HBP configuration register.
|
|
fields:
|
|
- name: HBP
|
|
description: HBP.
|
|
bit_offset: 0
|
|
bit_size: 12
|
|
fieldset/VHSACCR:
|
|
description: DSI Host video HSA current configuration register.
|
|
fields:
|
|
- name: HSA
|
|
description: HSA.
|
|
bit_offset: 0
|
|
bit_size: 12
|
|
fieldset/VHSACR:
|
|
description: DSI Host video HSA configuration register.
|
|
fields:
|
|
- name: HSA
|
|
description: HSA.
|
|
bit_offset: 0
|
|
bit_size: 12
|
|
fieldset/VLCCR:
|
|
description: DSI Host video line current configuration register.
|
|
fields:
|
|
- name: HLINE
|
|
description: HLINE.
|
|
bit_offset: 0
|
|
bit_size: 15
|
|
fieldset/VLCR:
|
|
description: DSI Host video line configuration register.
|
|
fields:
|
|
- name: HLINE
|
|
description: HLINE.
|
|
bit_offset: 0
|
|
bit_size: 15
|
|
fieldset/VMCCR:
|
|
description: DSI Host video mode current configuration register.
|
|
fields:
|
|
- name: VMT
|
|
description: VMT.
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: LPVSAE
|
|
description: LPVSAE.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: LPVBPE
|
|
description: LPVBPE.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: LPVFPE
|
|
description: LPVFPE.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: LPVAE
|
|
description: LPVAE.
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: LPHBPE
|
|
description: LPHBPE.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: LPHFE
|
|
description: LPHFE.
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: FBTAAE
|
|
description: FBTAAE.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LPCE
|
|
description: LPCE.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
fieldset/VMCR:
|
|
description: DSI Host video mode configuration register.
|
|
fields:
|
|
- name: VMT
|
|
description: VMT.
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: LPVSAE
|
|
description: LPVSAE.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LPVBPE
|
|
description: LPVBPE.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: LPVFPE
|
|
description: LPVFPE.
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: LPVAE
|
|
description: LPVAE.
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: LPHBPE
|
|
description: LPHBPE.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: LPHFPE
|
|
description: LPHFPE.
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: FBTAAE
|
|
description: FBTAAE.
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: LPCE
|
|
description: LPCE.
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: PGE
|
|
description: PGE.
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: PGM
|
|
description: PGM.
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: PGO
|
|
description: PGO.
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
fieldset/VNPCCR:
|
|
description: DSI Host video null packet current configuration register.
|
|
fields:
|
|
- name: NPSIZE
|
|
description: NPSIZE.
|
|
bit_offset: 0
|
|
bit_size: 13
|
|
fieldset/VNPCR:
|
|
description: DSI Host video null packet configuration register.
|
|
fields:
|
|
- name: NPSIZE
|
|
description: NPSIZE.
|
|
bit_offset: 0
|
|
bit_size: 13
|
|
fieldset/VPCCR:
|
|
description: DSI Host video packet current configuration register.
|
|
fields:
|
|
- name: VPSIZE
|
|
description: VPSIZE.
|
|
bit_offset: 0
|
|
bit_size: 14
|
|
fieldset/VPCR:
|
|
description: DSI Host video packet configuration register.
|
|
fields:
|
|
- name: VPSIZE
|
|
description: VPSIZE.
|
|
bit_offset: 0
|
|
bit_size: 14
|
|
fieldset/VR:
|
|
description: DSI Host version register.
|
|
fields:
|
|
- name: VERSION
|
|
description: VERSION.
|
|
bit_offset: 0
|
|
bit_size: 32
|
|
fieldset/VSCR:
|
|
description: DSI Host video shadow control register.
|
|
fields:
|
|
- name: EN
|
|
description: EN.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: UR
|
|
description: UR.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
fieldset/VVACCR:
|
|
description: DSI Host video VA current configuration register.
|
|
fields:
|
|
- name: VA
|
|
description: VA.
|
|
bit_offset: 0
|
|
bit_size: 14
|
|
fieldset/VVACR:
|
|
description: DSI Host video VA configuration register.
|
|
fields:
|
|
- name: VA
|
|
description: VA.
|
|
bit_offset: 0
|
|
bit_size: 14
|
|
fieldset/VVBPCCR:
|
|
description: DSI Host video VBP current configuration register.
|
|
fields:
|
|
- name: VBP
|
|
description: VBP.
|
|
bit_offset: 0
|
|
bit_size: 10
|
|
fieldset/VVBPCR:
|
|
description: DSI Host video VBP configuration register.
|
|
fields:
|
|
- name: VBP
|
|
description: VBP.
|
|
bit_offset: 0
|
|
bit_size: 10
|
|
fieldset/VVFPCCR:
|
|
description: DSI Host video VFP current configuration register.
|
|
fields:
|
|
- name: VFP
|
|
description: VFP.
|
|
bit_offset: 0
|
|
bit_size: 10
|
|
fieldset/VVFPCR:
|
|
description: DSI Host video VFP configuration register.
|
|
fields:
|
|
- name: VFP
|
|
description: VFP.
|
|
bit_offset: 0
|
|
bit_size: 10
|
|
fieldset/VVSACCR:
|
|
description: DSI Host video VSA current configuration register.
|
|
fields:
|
|
- name: VSA
|
|
description: VSA.
|
|
bit_offset: 0
|
|
bit_size: 10
|
|
fieldset/VVSACR:
|
|
description: DSI Host video VSA configuration register.
|
|
fields:
|
|
- name: VSA
|
|
description: VSA.
|
|
bit_offset: 0
|
|
bit_size: 10
|
|
fieldset/WCFGR:
|
|
description: DSI wrapper configuration register.
|
|
fields:
|
|
- name: DSIM
|
|
description: DSIM.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: COLMUX
|
|
description: COLMUX.
|
|
bit_offset: 1
|
|
bit_size: 3
|
|
- name: TESRC
|
|
description: TESRC.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: TEPOL
|
|
description: TEPOL.
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: AR
|
|
description: AR.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: VSPOL
|
|
description: VSPOL.
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
fieldset/WCR:
|
|
description: DSI wrapper control register.
|
|
fields:
|
|
- name: COLM
|
|
description: COLM.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: SHTDN
|
|
description: SHTDN.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: LTDCEN
|
|
description: LTDCEN.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: DSIEN
|
|
description: DSIEN.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
fieldset/WIER:
|
|
description: DSI wrapper interrupt enable register.
|
|
fields:
|
|
- name: TEIE
|
|
description: TEIE.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: ERIE
|
|
description: ERIE.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: PLLLIE
|
|
description: PLLLIE.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: PLLUIE
|
|
description: PLLUIE.
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: RRIE
|
|
description: RRIE.
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
fieldset/WIFCR:
|
|
description: DSI wrapper interrupt flag clear register.
|
|
fields:
|
|
- name: CTEIF
|
|
description: CTEIF.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: CERIF
|
|
description: CERIF.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: CPLLLIF
|
|
description: CPLLLIF.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: CPLLUIF
|
|
description: CPLLUIF.
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: CRRIF
|
|
description: CRRIF.
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
fieldset/WISR:
|
|
description: DSI wrapper interrupt and status register.
|
|
fields:
|
|
- name: TEIF
|
|
description: TEIF.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: ERIF
|
|
description: ERIF.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: BUSY
|
|
description: BUSY.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: PLLLS
|
|
description: PLLLS.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: PLLLIF
|
|
description: PLLLIF.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: PLLUIF
|
|
description: PLLUIF.
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: RRS
|
|
description: RRS.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: RRIF
|
|
description: RRIF.
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
fieldset/WPCR0:
|
|
description: DSI wrapper PHY configuration register 0.
|
|
fields:
|
|
- name: UIX4
|
|
description: UIX4.
|
|
bit_offset: 0
|
|
bit_size: 6
|
|
- name: SWCL
|
|
description: SWCL.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: SWDL0
|
|
description: SWDL0.
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: SWDL1
|
|
description: SWDL1.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: HSICL
|
|
description: HSICL.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HSIDL0
|
|
description: HSIDL0.
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: HSIDL1
|
|
description: HSIDL1.
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: FTXSMCL
|
|
description: FTXSMCL.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: FTXSMDL
|
|
description: FTXSMDL.
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: CDOFFDL
|
|
description: CDOFFDL.
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TDDL
|
|
description: TDDL.
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
fieldset/WPCR1:
|
|
description: This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and CR.EN = 0).
|
|
fields:
|
|
- name: SKEWCL
|
|
description: SKEWCL.
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: SKEWDL
|
|
description: SKEWDL.
|
|
bit_offset: 2
|
|
bit_size: 2
|
|
- name: LPTXSRCL
|
|
description: LPTXSRCL.
|
|
bit_offset: 6
|
|
bit_size: 2
|
|
- name: LPTXSRDL
|
|
description: LPTXSRDL.
|
|
bit_offset: 8
|
|
bit_size: 2
|
|
- name: SDDCCL
|
|
description: SDDCCL.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: SDDCDL
|
|
description: SDDCDL.
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: HSTXSRUCL
|
|
description: HSTXSRUCL.
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: HSTXSRDCL
|
|
description: HSTXSRDCL.
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: HSTXSRUDL
|
|
description: HSTXSRUDL.
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: HSTXSRDDL
|
|
description: HSTXSRDDL.
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
fieldset/WRPCR:
|
|
description: DSI wrapper regulator and PLL control register.
|
|
fields:
|
|
- name: PLLEN
|
|
description: PLLEN.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: NDIV
|
|
description: NDIV.
|
|
bit_offset: 2
|
|
bit_size: 7
|
|
- name: IDF
|
|
description: IDF.
|
|
bit_offset: 11
|
|
bit_size: 4
|
|
- name: ODF
|
|
description: ODF.
|
|
bit_offset: 16
|
|
bit_size: 2
|
|
- name: REGEN
|
|
description: REGEN.
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: BGREN
|
|
description: BGREN.
|
|
bit_offset: 28
|
|
bit_size: 1
|