1742 lines
46 KiB
YAML
1742 lines
46 KiB
YAML
block/DSIHOST:
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description: DSI Host.
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items:
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- name: VR
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description: DSI Host Version Register.
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byte_offset: 0
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access: Read
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fieldset: VR
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- name: CR
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description: DSI Host Control Register.
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byte_offset: 4
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fieldset: CR
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- name: CCR
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description: DSI HOST Clock Control Register.
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byte_offset: 8
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fieldset: CCR
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- name: LVCIDR
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description: DSI Host LTDC VCID Register.
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byte_offset: 12
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fieldset: LVCIDR
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- name: LCOLCR
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description: DSI Host LTDC Color Coding Register.
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byte_offset: 16
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fieldset: LCOLCR
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- name: LPCR
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description: DSI Host LTDC Polarity Configuration Register.
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byte_offset: 20
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fieldset: LPCR
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- name: LPMCR
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description: DSI Host Low-Power mode Configuration Register.
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byte_offset: 24
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fieldset: LPMCR
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- name: PCR
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description: DSI Host Protocol Configuration Register.
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byte_offset: 44
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fieldset: PCR
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- name: GVCIDR
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description: DSI Host Generic VCID Register.
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byte_offset: 48
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fieldset: GVCIDR
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- name: MCR
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description: DSI Host mode Configuration Register.
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byte_offset: 52
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fieldset: MCR
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- name: VMCR
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description: DSI Host Video mode Configuration Register.
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byte_offset: 56
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fieldset: VMCR
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- name: VPCR
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description: DSI Host Video Packet Configuration Register.
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byte_offset: 60
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fieldset: VPCR
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- name: VCCR
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description: DSI Host Video Chunks Configuration Register.
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byte_offset: 64
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fieldset: VCCR
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- name: VNPCR
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description: DSI Host Video Null Packet Configuration Register.
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byte_offset: 68
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fieldset: VNPCR
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- name: VHSACR
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description: DSI Host Video HSA Configuration Register.
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byte_offset: 72
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fieldset: VHSACR
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- name: VHBPCR
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description: DSI Host Video HBP Configuration Register.
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byte_offset: 76
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fieldset: VHBPCR
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- name: VLCR
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description: DSI Host Video Line Configuration Register.
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byte_offset: 80
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fieldset: VLCR
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- name: VVSACR
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description: DSI Host Video VSA Configuration Register.
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byte_offset: 84
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fieldset: VVSACR
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- name: VVBPCR
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description: DSI Host Video VBP Configuration Register.
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byte_offset: 88
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fieldset: VVBPCR
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- name: VVFPCR
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description: DSI Host Video VFP Configuration Register.
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byte_offset: 92
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fieldset: VVFPCR
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- name: VVACR
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description: DSI Host Video VA Configuration Register.
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byte_offset: 96
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fieldset: VVACR
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- name: LCCR
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description: DSI Host LTDC Command Configuration Register.
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byte_offset: 100
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fieldset: LCCR
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- name: CMCR
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description: DSI Host Command mode Configuration Register.
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byte_offset: 104
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fieldset: CMCR
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- name: GHCR
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description: DSI Host Generic Header Configuration Register.
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byte_offset: 108
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fieldset: GHCR
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- name: GPDR
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description: DSI Host Generic Payload Data Register.
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byte_offset: 112
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fieldset: GPDR
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- name: GPSR
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description: DSI Host Generic Packet Status Register.
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byte_offset: 116
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access: Read
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fieldset: GPSR
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- name: TCCR0
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description: DSI Host Timeout Counter Configuration Register 0.
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byte_offset: 120
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fieldset: TCCR0
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- name: TCCR1
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description: DSI Host Timeout Counter Configuration Register 1.
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byte_offset: 124
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fieldset: TCCR1
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- name: TCCR2
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description: DSI Host Timeout Counter Configuration Register 2.
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byte_offset: 128
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fieldset: TCCR2
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- name: TCCR3
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description: DSI Host Timeout Counter Configuration Register 3.
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byte_offset: 132
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fieldset: TCCR3
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- name: TCCR4
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description: DSI Host Timeout Counter Configuration Register 4.
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byte_offset: 136
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fieldset: TCCR4
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- name: TCCR5
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description: DSI Host Timeout Counter Configuration Register 5.
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byte_offset: 140
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fieldset: TCCR5
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- name: CLCR
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description: DSI Host Clock Lane Configuration Register.
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byte_offset: 148
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fieldset: CLCR
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- name: CLTCR
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description: DSI Host Clock Lane Timer Configuration Register.
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byte_offset: 152
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fieldset: CLTCR
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- name: DLTCR
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description: DSI Host Data Lane Timer Configuration Register.
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byte_offset: 156
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fieldset: DLTCR
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- name: PCTLR
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description: DSI Host PHY Control Register.
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byte_offset: 160
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fieldset: PCTLR
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- name: PCONFR
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description: DSI Host PHY Configuration Register.
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byte_offset: 164
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fieldset: PCONFR
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- name: PUCR
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description: DSI Host PHY ULPS Control Register.
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byte_offset: 168
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fieldset: PUCR
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- name: PTTCR
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description: DSI Host PHY TX Triggers Configuration Register.
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byte_offset: 172
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fieldset: PTTCR
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- name: PSR
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description: DSI Host PHY Status Register.
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byte_offset: 176
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access: Read
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fieldset: PSR
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- name: ISR0
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description: DSI Host Interrupt & Status Register 0.
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byte_offset: 188
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access: Read
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fieldset: ISR0
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- name: ISR1
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description: DSI Host Interrupt & Status Register 1.
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byte_offset: 192
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access: Read
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fieldset: ISR1
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- name: IER0
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description: DSI Host Interrupt Enable Register 0.
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byte_offset: 196
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fieldset: IER0
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- name: IER1
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description: DSI Host Interrupt Enable Register 1.
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byte_offset: 200
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fieldset: IER1
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- name: FIR0
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description: DSI Host Force Interrupt Register 0.
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byte_offset: 216
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access: Write
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fieldset: FIR0
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- name: FIR1
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description: DSI Host Force Interrupt Register 1.
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byte_offset: 220
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access: Write
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fieldset: FIR1
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- name: VSCR
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description: DSI Host Video Shadow Control Register.
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byte_offset: 256
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fieldset: VSCR
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- name: LCVCIDR
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description: DSI Host LTDC Current VCID Register.
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byte_offset: 268
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access: Read
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fieldset: LCVCIDR
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- name: LCCCR
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description: DSI Host LTDC Current Color Coding Register.
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byte_offset: 272
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access: Read
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fieldset: LCCCR
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- name: LPMCCR
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description: DSI Host Low-Power mode Current Configuration Register.
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byte_offset: 280
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access: Read
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fieldset: LPMCCR
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- name: VMCCR
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description: DSI Host Video mode Current Configuration Register.
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byte_offset: 312
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access: Read
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fieldset: VMCCR
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- name: VPCCR
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description: DSI Host Video Packet Current Configuration Register.
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byte_offset: 316
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access: Read
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fieldset: VPCCR
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- name: VCCCR
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description: DSI Host Video Chunks Current Configuration Register.
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byte_offset: 320
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access: Read
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fieldset: VCCCR
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- name: VNPCCR
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description: DSI Host Video Null Packet Current Configuration Register.
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byte_offset: 324
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access: Read
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fieldset: VNPCCR
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- name: VHSACCR
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description: DSI Host Video HSA Current Configuration Register.
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byte_offset: 328
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access: Read
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fieldset: VHSACCR
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- name: VHBPCCR
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description: DSI Host Video HBP Current Configuration Register.
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byte_offset: 332
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access: Read
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fieldset: VHBPCCR
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- name: VLCCR
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description: DSI Host Video Line Current Configuration Register.
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byte_offset: 336
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access: Read
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fieldset: VLCCR
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- name: VVSACCR
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description: DSI Host Video VSA Current Configuration Register.
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byte_offset: 340
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access: Read
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fieldset: VVSACCR
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- name: VVBPCCR
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description: DSI Host Video VBP Current Configuration Register.
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byte_offset: 344
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access: Read
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fieldset: VVBPCCR
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- name: VVFPCCR
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description: DSI Host Video VFP Current Configuration Register.
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byte_offset: 348
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access: Read
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fieldset: VVFPCCR
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- name: VVACCR
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description: DSI Host Video VA Current Configuration Register.
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byte_offset: 352
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access: Read
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fieldset: VVACCR
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- name: WCFGR
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description: DSI Wrapper Configuration Register.
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byte_offset: 1024
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fieldset: WCFGR
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- name: WCR
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description: DSI Wrapper Control Register.
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byte_offset: 1028
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fieldset: WCR
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- name: WIER
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description: DSI Wrapper Interrupt Enable Register.
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byte_offset: 1032
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fieldset: WIER
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- name: WISR
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description: DSI Wrapper Interrupt & Status Register.
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byte_offset: 1036
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access: Read
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fieldset: WISR
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- name: WIFCR
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description: DSI Wrapper Interrupt Flag Clear Register.
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byte_offset: 1040
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fieldset: WIFCR
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- name: WPCR0
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description: DSI Wrapper PHY Configuration Register 0.
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byte_offset: 1048
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fieldset: WPCR0
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- name: WPCR1
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description: DSI Wrapper PHY Configuration Register 1.
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byte_offset: 1052
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fieldset: WPCR1
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- name: WPCR2
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description: DSI Wrapper PHY Configuration Register 2.
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byte_offset: 1056
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fieldset: WPCR2
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- name: WPCR3
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description: DSI Wrapper PHY Configuration Register 3.
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byte_offset: 1060
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fieldset: WPCR3
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- name: WPCR4
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description: DSI Wrapper PHY Configuration Register 4.
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byte_offset: 1064
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fieldset: WPCR4
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- name: WRPCR
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description: DSI Wrapper Regulator and PLL Control Register.
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byte_offset: 1072
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fieldset: WRPCR
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fieldset/CCR:
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description: DSI HOST Clock Control Register.
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fields:
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- name: TXECKDIV
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description: TX Escape Clock Division.
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bit_offset: 0
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bit_size: 8
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- name: TOCKDIV
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description: Timeout Clock Division.
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bit_offset: 8
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bit_size: 8
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fieldset/CLCR:
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description: DSI Host Clock Lane Configuration Register.
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fields:
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- name: DPCC
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description: D-PHY Clock Control.
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bit_offset: 0
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bit_size: 1
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- name: ACR
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description: Automatic Clock lane Control.
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bit_offset: 1
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bit_size: 1
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fieldset/CLTCR:
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description: DSI Host Clock Lane Timer Configuration Register.
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fields:
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- name: LP2HS_TIME
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description: Low-Power to High-Speed Time.
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bit_offset: 0
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bit_size: 10
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- name: HS2LP_TIME
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description: High-Speed to Low-Power Time.
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bit_offset: 16
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bit_size: 10
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fieldset/CMCR:
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description: DSI Host Command mode Configuration Register.
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fields:
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- name: TEARE
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description: Tearing Effect Acknowledge Request Enable.
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bit_offset: 0
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bit_size: 1
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- name: ARE
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description: Acknowledge Request Enable.
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bit_offset: 1
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bit_size: 1
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- name: GSW0TX
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description: Generic Short Write Zero parameters Transmission.
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bit_offset: 8
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bit_size: 1
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- name: GSW1TX
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description: Generic Short Write One parameters Transmission.
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bit_offset: 9
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bit_size: 1
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- name: GSW2TX
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description: Generic Short Write Two parameters Transmission.
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bit_offset: 10
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bit_size: 1
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- name: GSR0TX
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description: Generic Short Read Zero parameters Transmission.
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bit_offset: 11
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bit_size: 1
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- name: GSR1TX
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description: Generic Short Read One parameters Transmission.
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bit_offset: 12
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bit_size: 1
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- name: GSR2TX
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description: Generic Short Read Two parameters Transmission.
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bit_offset: 13
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bit_size: 1
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- name: GLWTX
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description: Generic Long Write Transmission.
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bit_offset: 14
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bit_size: 1
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- name: DSW0TX
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description: DCS Short Write Zero parameter Transmission.
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bit_offset: 16
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bit_size: 1
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- name: DSW1TX
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description: DCS Short Read One parameter Transmission.
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bit_offset: 17
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bit_size: 1
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- name: DSR0TX
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description: DCS Short Read Zero parameter Transmission.
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bit_offset: 18
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bit_size: 1
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- name: DLWTX
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description: DCS Long Write Transmission.
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bit_offset: 19
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bit_size: 1
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- name: MRDPS
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description: Maximum Read Packet Size.
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bit_offset: 24
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bit_size: 1
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fieldset/CR:
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description: DSI Host Control Register.
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fields:
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- name: EN
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description: Enable.
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bit_offset: 0
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bit_size: 1
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fieldset/DLTCR:
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description: DSI Host Data Lane Timer Configuration Register.
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fields:
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- name: MRD_TIME
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description: Maximum Read Time.
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bit_offset: 0
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bit_size: 15
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- name: LP2HS_TIME
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description: Low-Power To High-Speed Time.
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bit_offset: 16
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bit_size: 8
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- name: HS2LP_TIME
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description: High-Speed To Low-Power Time.
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bit_offset: 24
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bit_size: 8
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fieldset/FIR0:
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description: DSI Host Force Interrupt Register 0.
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fields:
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- name: FAE0
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description: Force Acknowledge Error 0.
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bit_offset: 0
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bit_size: 1
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- name: FAE1
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description: Force Acknowledge Error 1.
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bit_offset: 1
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bit_size: 1
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- name: FAE2
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description: Force Acknowledge Error 2.
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bit_offset: 2
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bit_size: 1
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- name: FAE3
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description: Force Acknowledge Error 3.
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bit_offset: 3
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bit_size: 1
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- name: FAE4
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description: Force Acknowledge Error 4.
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bit_offset: 4
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bit_size: 1
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- name: FAE5
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description: Force Acknowledge Error 5.
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bit_offset: 5
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bit_size: 1
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- name: FAE6
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description: Force Acknowledge Error 6.
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bit_offset: 6
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bit_size: 1
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- name: FAE7
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description: Force Acknowledge Error 7.
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bit_offset: 7
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bit_size: 1
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- name: FAE8
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description: Force Acknowledge Error 8.
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bit_offset: 8
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bit_size: 1
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- name: FAE9
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description: Force Acknowledge Error 9.
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bit_offset: 9
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bit_size: 1
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- name: FAE10
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description: Force Acknowledge Error 10.
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bit_offset: 10
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bit_size: 1
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- name: FAE11
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description: Force Acknowledge Error 11.
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bit_offset: 11
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bit_size: 1
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- name: FAE12
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description: Force Acknowledge Error 12.
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bit_offset: 12
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bit_size: 1
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- name: FAE13
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description: Force Acknowledge Error 13.
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bit_offset: 13
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bit_size: 1
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- name: FAE14
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description: Force Acknowledge Error 14.
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bit_offset: 14
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bit_size: 1
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- name: FAE15
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description: Force Acknowledge Error 15.
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bit_offset: 15
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bit_size: 1
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- name: FPE0
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description: Force PHY Error 0.
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bit_offset: 16
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bit_size: 1
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- name: FPE1
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description: Force PHY Error 1.
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bit_offset: 17
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bit_size: 1
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- name: FPE2
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description: Force PHY Error 2.
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bit_offset: 18
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bit_size: 1
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- name: FPE3
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description: Force PHY Error 3.
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bit_offset: 19
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bit_size: 1
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- name: FPE4
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description: Force PHY Error 4.
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bit_offset: 20
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bit_size: 1
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fieldset/FIR1:
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description: DSI Host Force Interrupt Register 1.
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fields:
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- name: FTOHSTX
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description: Force Timeout High-Speed Transmission.
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bit_offset: 0
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bit_size: 1
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- name: FTOLPRX
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description: Force Timeout Low-Power Reception.
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bit_offset: 1
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bit_size: 1
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- name: FECCSE
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description: Force ECC Single-bit Error.
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bit_offset: 2
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bit_size: 1
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- name: FECCME
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description: Force ECC Multi-bit Error.
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bit_offset: 3
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bit_size: 1
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- name: FCRCE
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description: Force CRC Error.
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bit_offset: 4
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bit_size: 1
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- name: FPSE
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description: Force Packet Size Error.
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bit_offset: 5
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bit_size: 1
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- name: FEOTPE
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description: Force EoTp Error.
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bit_offset: 6
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bit_size: 1
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- name: FLPWRE
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description: Force LTDC Payload Write Error.
|
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bit_offset: 7
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bit_size: 1
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- name: FGCWRE
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description: Force Generic Command Write Error.
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bit_offset: 8
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bit_size: 1
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- name: FGPWRE
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description: Force Generic Payload Write Error.
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bit_offset: 9
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bit_size: 1
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- name: FGPTXE
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description: Force Generic Payload Transmit Error.
|
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bit_offset: 10
|
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bit_size: 1
|
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- name: FGPRDE
|
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description: Force Generic Payload Read Error.
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: FGPRXE
|
|
description: Force Generic Payload Receive Error.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
fieldset/GHCR:
|
|
description: DSI Host Generic Header Configuration Register.
|
|
fields:
|
|
- name: DT
|
|
description: Type.
|
|
bit_offset: 0
|
|
bit_size: 6
|
|
- name: VCID
|
|
description: Channel.
|
|
bit_offset: 6
|
|
bit_size: 2
|
|
- name: WCLSB
|
|
description: WordCount LSB.
|
|
bit_offset: 8
|
|
bit_size: 8
|
|
- name: WCMSB
|
|
description: WordCount MSB.
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
fieldset/GPDR:
|
|
description: DSI Host Generic Payload Data Register.
|
|
fields:
|
|
- name: DATA1
|
|
description: Payload Byte 1.
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
- name: DATA2
|
|
description: Payload Byte 2.
|
|
bit_offset: 8
|
|
bit_size: 8
|
|
- name: DATA3
|
|
description: Payload Byte 3.
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
- name: DATA4
|
|
description: Payload Byte 4.
|
|
bit_offset: 24
|
|
bit_size: 8
|
|
fieldset/GPSR:
|
|
description: DSI Host Generic Packet Status Register.
|
|
fields:
|
|
- name: CMDFE
|
|
description: Command FIFO Empty.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: CMDFF
|
|
description: Command FIFO Full.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: PWRFE
|
|
description: Payload Write FIFO Empty.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: PWRFF
|
|
description: Payload Write FIFO Full.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: PRDFE
|
|
description: Payload Read FIFO Empty.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: PRDFF
|
|
description: Payload Read FIFO Full.
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: RCB
|
|
description: Read Command Busy.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
fieldset/GVCIDR:
|
|
description: DSI Host Generic VCID Register.
|
|
fields:
|
|
- name: VCID
|
|
description: Virtual Channel ID.
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
fieldset/IER0:
|
|
description: DSI Host Interrupt Enable Register 0.
|
|
fields:
|
|
- name: AE0IE
|
|
description: Acknowledge Error 0 Interrupt Enable.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: AE1IE
|
|
description: Acknowledge Error 1 Interrupt Enable.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: AE2IE
|
|
description: Acknowledge Error 2 Interrupt Enable.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: AE3IE
|
|
description: Acknowledge Error 3 Interrupt Enable.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: AE4IE
|
|
description: Acknowledge Error 4 Interrupt Enable.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: AE5IE
|
|
description: Acknowledge Error 5 Interrupt Enable.
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: AE6IE
|
|
description: Acknowledge Error 6 Interrupt Enable.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: AE7IE
|
|
description: Acknowledge Error 7 Interrupt Enable.
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: AE8IE
|
|
description: Acknowledge Error 8 Interrupt Enable.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: AE9IE
|
|
description: Acknowledge Error 9 Interrupt Enable.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: AE10IE
|
|
description: Acknowledge Error 10 Interrupt Enable.
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: AE11IE
|
|
description: Acknowledge Error 11 Interrupt Enable.
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: AE12IE
|
|
description: Acknowledge Error 12 Interrupt Enable.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: AE13IE
|
|
description: Acknowledge Error 13 Interrupt Enable.
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: AE14IE
|
|
description: Acknowledge Error 14 Interrupt Enable.
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: AE15IE
|
|
description: Acknowledge Error 15 Interrupt Enable.
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: PE0IE
|
|
description: PHY Error 0 Interrupt Enable.
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: PE1IE
|
|
description: PHY Error 1 Interrupt Enable.
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: PE2IE
|
|
description: PHY Error 2 Interrupt Enable.
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: PE3IE
|
|
description: PHY Error 3 Interrupt Enable.
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: PE4IE
|
|
description: PHY Error 4 Interrupt Enable.
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
fieldset/IER1:
|
|
description: DSI Host Interrupt Enable Register 1.
|
|
fields:
|
|
- name: TOHSTXIE
|
|
description: Timeout High-Speed Transmission Interrupt Enable.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: TOLPRXIE
|
|
description: Timeout Low-Power Reception Interrupt Enable.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: ECCSEIE
|
|
description: ECC Single-bit Error Interrupt Enable.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: ECCMEIE
|
|
description: ECC Multi-bit Error Interrupt Enable.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: CRCEIE
|
|
description: CRC Error Interrupt Enable.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: PSEIE
|
|
description: Packet Size Error Interrupt Enable.
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: EOTPEIE
|
|
description: EoTp Error Interrupt Enable.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: LPWREIE
|
|
description: LTDC Payload Write Error Interrupt Enable.
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: GCWREIE
|
|
description: Generic Command Write Error Interrupt Enable.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: GPWREIE
|
|
description: Generic Payload Write Error Interrupt Enable.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: GPTXEIE
|
|
description: Generic Payload Transmit Error Interrupt Enable.
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: GPRDEIE
|
|
description: Generic Payload Read Error Interrupt Enable.
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: GPRXEIE
|
|
description: Generic Payload Receive Error Interrupt Enable.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
fieldset/ISR0:
|
|
description: DSI Host Interrupt & Status Register 0.
|
|
fields:
|
|
- name: AE0
|
|
description: Acknowledge Error 0.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: AE1
|
|
description: Acknowledge Error 1.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: AE2
|
|
description: Acknowledge Error 2.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: AE3
|
|
description: Acknowledge Error 3.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: AE4
|
|
description: Acknowledge Error 4.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: AE5
|
|
description: Acknowledge Error 5.
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: AE6
|
|
description: Acknowledge Error 6.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: AE7
|
|
description: Acknowledge Error 7.
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: AE8
|
|
description: Acknowledge Error 8.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: AE9
|
|
description: Acknowledge Error 9.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: AE10
|
|
description: Acknowledge Error 10.
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: AE11
|
|
description: Acknowledge Error 11.
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: AE12
|
|
description: Acknowledge Error 12.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: AE13
|
|
description: Acknowledge Error 13.
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: AE14
|
|
description: Acknowledge Error 14.
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: AE15
|
|
description: Acknowledge Error 15.
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: PE0
|
|
description: PHY Error 0.
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: PE1
|
|
description: PHY Error 1.
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: PE2
|
|
description: PHY Error 2.
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: PE3
|
|
description: PHY Error 3.
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: PE4
|
|
description: PHY Error 4.
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
fieldset/ISR1:
|
|
description: DSI Host Interrupt & Status Register 1.
|
|
fields:
|
|
- name: TOHSTX
|
|
description: Timeout High-Speed Transmission.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: TOLPRX
|
|
description: Timeout Low-Power Reception.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: ECCSE
|
|
description: ECC Single-bit Error.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: ECCME
|
|
description: ECC Multi-bit Error.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: CRCE
|
|
description: CRC Error.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: PSE
|
|
description: Packet Size Error.
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: EOTPE
|
|
description: EoTp Error.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: LPWRE
|
|
description: LTDC Payload Write Error.
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: GCWRE
|
|
description: Generic Command Write Error.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: GPWRE
|
|
description: Generic Payload Write Error.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: GPTXE
|
|
description: Generic Payload Transmit Error.
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: GPRDE
|
|
description: Generic Payload Read Error.
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: GPRXE
|
|
description: Generic Payload Receive Error.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
fieldset/LCCCR:
|
|
description: DSI Host LTDC Current Color Coding Register.
|
|
fields:
|
|
- name: COLC
|
|
description: Color Coding.
|
|
bit_offset: 0
|
|
bit_size: 4
|
|
- name: LPE
|
|
description: Loosely Packed Enable.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
fieldset/LCCR:
|
|
description: DSI Host LTDC Command Configuration Register.
|
|
fields:
|
|
- name: CMDSIZE
|
|
description: Command Size.
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/LCOLCR:
|
|
description: DSI Host LTDC Color Coding Register.
|
|
fields:
|
|
- name: COLC
|
|
description: Color Coding.
|
|
bit_offset: 0
|
|
bit_size: 4
|
|
- name: LPE
|
|
description: Loosely Packet Enable.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
fieldset/LCVCIDR:
|
|
description: DSI Host LTDC Current VCID Register.
|
|
fields:
|
|
- name: VCID
|
|
description: Virtual Channel ID.
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
fieldset/LPCR:
|
|
description: DSI Host LTDC Polarity Configuration Register.
|
|
fields:
|
|
- name: DEP
|
|
description: Data Enable Polarity.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: VSP
|
|
description: VSYNC Polarity.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: HSP
|
|
description: HSYNC Polarity.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
fieldset/LPMCCR:
|
|
description: DSI Host Low-Power mode Current Configuration Register.
|
|
fields:
|
|
- name: VLPSIZE
|
|
description: VACT Largest Packet Size.
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
- name: LPSIZE
|
|
description: Largest Packet Size.
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
fieldset/LPMCR:
|
|
description: DSI Host Low-Power mode Configuration Register.
|
|
fields:
|
|
- name: VLPSIZE
|
|
description: VACT Largest Packet Size.
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
- name: LPSIZE
|
|
description: Largest Packet Size.
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
fieldset/LVCIDR:
|
|
description: DSI Host LTDC VCID Register.
|
|
fields:
|
|
- name: VCID
|
|
description: Virtual Channel ID.
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
fieldset/MCR:
|
|
description: DSI Host mode Configuration Register.
|
|
fields:
|
|
- name: CMDM
|
|
description: Command mode.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
fieldset/PCONFR:
|
|
description: DSI Host PHY Configuration Register.
|
|
fields:
|
|
- name: NL
|
|
description: Number of Lanes.
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: SW_TIME
|
|
description: Stop Wait Time.
|
|
bit_offset: 8
|
|
bit_size: 8
|
|
fieldset/PCR:
|
|
description: DSI Host Protocol Configuration Register.
|
|
fields:
|
|
- name: ETTXE
|
|
description: EoTp Transmission Enable.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: ETRXE
|
|
description: EoTp Reception Enable.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: BTAE
|
|
description: Bus Turn Around Enable.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: ECCRXE
|
|
description: ECC Reception Enable.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: CRCRXE
|
|
description: CRC Reception Enable.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
fieldset/PCTLR:
|
|
description: DSI Host PHY Control Register.
|
|
fields:
|
|
- name: DEN
|
|
description: Digital Enable.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: CKE
|
|
description: Clock Enable.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
fieldset/PSR:
|
|
description: DSI Host PHY Status Register.
|
|
fields:
|
|
- name: PD
|
|
description: PHY Direction.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: PSSC
|
|
description: PHY Stop State Clock lane.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: UANC
|
|
description: ULPS Active Not Clock lane.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: PSS0
|
|
description: PHY Stop State lane 0.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: UAN0
|
|
description: ULPS Active Not lane 1.
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: RUE0
|
|
description: RX ULPS Escape lane 0.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: PSS1
|
|
description: PHY Stop State lane 1.
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: UAN1
|
|
description: ULPS Active Not lane 1.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
fieldset/PTTCR:
|
|
description: DSI Host PHY TX Triggers Configuration Register.
|
|
fields:
|
|
- name: TX_TRIG
|
|
description: Transmission Trigger.
|
|
bit_offset: 0
|
|
bit_size: 4
|
|
fieldset/PUCR:
|
|
description: DSI Host PHY ULPS Control Register.
|
|
fields:
|
|
- name: URCL
|
|
description: ULPS Request on Clock Lane.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: UECL
|
|
description: ULPS Exit on Clock Lane.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: URDL
|
|
description: ULPS Request on Data Lane.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: UEDL
|
|
description: ULPS Exit on Data Lane.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
fieldset/TCCR0:
|
|
description: DSI Host Timeout Counter Configuration Register 0.
|
|
fields:
|
|
- name: LPRX_TOCNT
|
|
description: Low-power Reception Timeout Counter.
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
- name: HSTX_TOCNT
|
|
description: High-Speed Transmission Timeout Counter.
|
|
bit_offset: 16
|
|
bit_size: 16
|
|
fieldset/TCCR1:
|
|
description: DSI Host Timeout Counter Configuration Register 1.
|
|
fields:
|
|
- name: HSRD_TOCNT
|
|
description: High-Speed Read Timeout Counter.
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/TCCR2:
|
|
description: DSI Host Timeout Counter Configuration Register 2.
|
|
fields:
|
|
- name: LPRD_TOCNT
|
|
description: Low-Power Read Timeout Counter.
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/TCCR3:
|
|
description: DSI Host Timeout Counter Configuration Register 3.
|
|
fields:
|
|
- name: HSWR_TOCNT
|
|
description: High-Speed Write Timeout Counter.
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
- name: PM
|
|
description: Presp mode.
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
fieldset/TCCR4:
|
|
description: DSI Host Timeout Counter Configuration Register 4.
|
|
fields:
|
|
- name: LSWR_TOCNT
|
|
description: Low-Power Write Timeout Counter.
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/TCCR5:
|
|
description: DSI Host Timeout Counter Configuration Register 5.
|
|
fields:
|
|
- name: BTA_TOCNT
|
|
description: Bus-Turn-Around Timeout Counter.
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/VCCCR:
|
|
description: DSI Host Video Chunks Current Configuration Register.
|
|
fields:
|
|
- name: NUMC
|
|
description: Number of Chunks.
|
|
bit_offset: 0
|
|
bit_size: 13
|
|
fieldset/VCCR:
|
|
description: DSI Host Video Chunks Configuration Register.
|
|
fields:
|
|
- name: NUMC
|
|
description: Number of Chunks.
|
|
bit_offset: 0
|
|
bit_size: 13
|
|
fieldset/VHBPCCR:
|
|
description: DSI Host Video HBP Current Configuration Register.
|
|
fields:
|
|
- name: HBP
|
|
description: Horizontal Back-Porch duration.
|
|
bit_offset: 0
|
|
bit_size: 12
|
|
fieldset/VHBPCR:
|
|
description: DSI Host Video HBP Configuration Register.
|
|
fields:
|
|
- name: HBP
|
|
description: Horizontal Back-Porch duration.
|
|
bit_offset: 0
|
|
bit_size: 12
|
|
fieldset/VHSACCR:
|
|
description: DSI Host Video HSA Current Configuration Register.
|
|
fields:
|
|
- name: HSA
|
|
description: Horizontal Synchronism Active duration.
|
|
bit_offset: 0
|
|
bit_size: 12
|
|
fieldset/VHSACR:
|
|
description: DSI Host Video HSA Configuration Register.
|
|
fields:
|
|
- name: HSA
|
|
description: Horizontal Synchronism Active duration.
|
|
bit_offset: 0
|
|
bit_size: 12
|
|
fieldset/VLCCR:
|
|
description: DSI Host Video Line Current Configuration Register.
|
|
fields:
|
|
- name: HLINE
|
|
description: Horizontal Line duration.
|
|
bit_offset: 0
|
|
bit_size: 15
|
|
fieldset/VLCR:
|
|
description: DSI Host Video Line Configuration Register.
|
|
fields:
|
|
- name: HLINE
|
|
description: Horizontal Line duration.
|
|
bit_offset: 0
|
|
bit_size: 15
|
|
fieldset/VMCCR:
|
|
description: DSI Host Video mode Current Configuration Register.
|
|
fields:
|
|
- name: VMT
|
|
description: Video mode Type.
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: LPVSAE
|
|
description: Low-Power Vertical Sync time Enable.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: LPVBPE
|
|
description: Low-power Vertical Back-Porch Enable.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: LPVFPE
|
|
description: Low-power Vertical Front-Porch Enable.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: LPVAE
|
|
description: Low-Power Vertical Active Enable.
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: LPHBPE
|
|
description: Low-power Horizontal Back-Porch Enable.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: LPHFE
|
|
description: Low-Power Horizontal Front-Porch Enable.
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: FBTAAE
|
|
description: Frame BTA Acknowledge Enable.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LPCE
|
|
description: Low-Power Command Enable.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
fieldset/VMCR:
|
|
description: DSI Host Video mode Configuration Register.
|
|
fields:
|
|
- name: VMT
|
|
description: Video mode Type.
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: LPVSAE
|
|
description: Low-Power Vertical Sync Active Enable.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LPVBPE
|
|
description: Low-power Vertical Back-Porch Enable.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: LPVFPE
|
|
description: Low-power Vertical Front-porch Enable.
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: LPVAE
|
|
description: Low-Power Vertical Active Enable.
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: LPHBPE
|
|
description: Low-Power Horizontal Back-Porch Enable.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: LPHFPE
|
|
description: Low-Power Horizontal Front-Porch Enable.
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: FBTAAE
|
|
description: Frame Bus-Turn-Around Acknowledge Enable.
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: LPCE
|
|
description: Low-Power Command Enable.
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: PGE
|
|
description: Pattern Generator Enable.
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: PGM
|
|
description: Pattern Generator mode.
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: PGO
|
|
description: Pattern Generator Orientation.
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
fieldset/VNPCCR:
|
|
description: DSI Host Video Null Packet Current Configuration Register.
|
|
fields:
|
|
- name: NPSIZE
|
|
description: Null Packet Size.
|
|
bit_offset: 0
|
|
bit_size: 13
|
|
fieldset/VNPCR:
|
|
description: DSI Host Video Null Packet Configuration Register.
|
|
fields:
|
|
- name: NPSIZE
|
|
description: Null Packet Size.
|
|
bit_offset: 0
|
|
bit_size: 13
|
|
fieldset/VPCCR:
|
|
description: DSI Host Video Packet Current Configuration Register.
|
|
fields:
|
|
- name: VPSIZE
|
|
description: Video Packet Size.
|
|
bit_offset: 0
|
|
bit_size: 14
|
|
fieldset/VPCR:
|
|
description: DSI Host Video Packet Configuration Register.
|
|
fields:
|
|
- name: VPSIZE
|
|
description: Video Packet Size.
|
|
bit_offset: 0
|
|
bit_size: 14
|
|
fieldset/VR:
|
|
description: DSI Host Version Register.
|
|
fields:
|
|
- name: VERSION
|
|
description: Version of the DSI Host.
|
|
bit_offset: 0
|
|
bit_size: 32
|
|
fieldset/VSCR:
|
|
description: DSI Host Video Shadow Control Register.
|
|
fields:
|
|
- name: EN
|
|
description: Enable.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: UR
|
|
description: Update Register.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
fieldset/VVACCR:
|
|
description: DSI Host Video VA Current Configuration Register.
|
|
fields:
|
|
- name: VA
|
|
description: Vertical Active duration.
|
|
bit_offset: 0
|
|
bit_size: 14
|
|
fieldset/VVACR:
|
|
description: DSI Host Video VA Configuration Register.
|
|
fields:
|
|
- name: VA
|
|
description: Vertical Active duration.
|
|
bit_offset: 0
|
|
bit_size: 14
|
|
fieldset/VVBPCCR:
|
|
description: DSI Host Video VBP Current Configuration Register.
|
|
fields:
|
|
- name: VBP
|
|
description: Vertical Back-Porch duration.
|
|
bit_offset: 0
|
|
bit_size: 10
|
|
fieldset/VVBPCR:
|
|
description: DSI Host Video VBP Configuration Register.
|
|
fields:
|
|
- name: VBP
|
|
description: Vertical Back-Porch duration.
|
|
bit_offset: 0
|
|
bit_size: 10
|
|
fieldset/VVFPCCR:
|
|
description: DSI Host Video VFP Current Configuration Register.
|
|
fields:
|
|
- name: VFP
|
|
description: Vertical Front-Porch duration.
|
|
bit_offset: 0
|
|
bit_size: 10
|
|
fieldset/VVFPCR:
|
|
description: DSI Host Video VFP Configuration Register.
|
|
fields:
|
|
- name: VFP
|
|
description: Vertical Front-Porch duration.
|
|
bit_offset: 0
|
|
bit_size: 10
|
|
fieldset/VVSACCR:
|
|
description: DSI Host Video VSA Current Configuration Register.
|
|
fields:
|
|
- name: VSA
|
|
description: Vertical Synchronism Active duration.
|
|
bit_offset: 0
|
|
bit_size: 10
|
|
fieldset/VVSACR:
|
|
description: DSI Host Video VSA Configuration Register.
|
|
fields:
|
|
- name: VSA
|
|
description: Vertical Synchronism Active duration.
|
|
bit_offset: 0
|
|
bit_size: 10
|
|
fieldset/WCFGR:
|
|
description: DSI Wrapper Configuration Register.
|
|
fields:
|
|
- name: DSIM
|
|
description: DSI Mode.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: COLMUX
|
|
description: Color Multiplexing.
|
|
bit_offset: 1
|
|
bit_size: 3
|
|
- name: TESRC
|
|
description: TE Source.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: TEPOL
|
|
description: TE Polarity.
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: AR
|
|
description: Automatic Refresh.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: VSPOL
|
|
description: VSync Polarity.
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
fieldset/WCR:
|
|
description: DSI Wrapper Control Register.
|
|
fields:
|
|
- name: COLM
|
|
description: Color Mode.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: SHTDN
|
|
description: Shutdown.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: LTDCEN
|
|
description: LTDC Enable.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: DSIEN
|
|
description: DSI Enable.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
fieldset/WIER:
|
|
description: DSI Wrapper Interrupt Enable Register.
|
|
fields:
|
|
- name: TEIE
|
|
description: Tearing Effect Interrupt Enable.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: ERIE
|
|
description: End of Refresh Interrupt Enable.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: PLLLIE
|
|
description: PLL Lock Interrupt Enable.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: PLLUIE
|
|
description: PLL Unlock Interrupt Enable.
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: RRIE
|
|
description: Regulator Ready Interrupt Enable.
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
fieldset/WIFCR:
|
|
description: DSI Wrapper Interrupt Flag Clear Register.
|
|
fields:
|
|
- name: CTEIF
|
|
description: Clear Tearing Effect Interrupt Flag.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: CERIF
|
|
description: Clear End of Refresh Interrupt Flag.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: CPLLLIF
|
|
description: Clear PLL Lock Interrupt Flag.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: CPLLUIF
|
|
description: Clear PLL Unlock Interrupt Flag.
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: CRRIF
|
|
description: Clear Regulator Ready Interrupt Flag.
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
fieldset/WISR:
|
|
description: DSI Wrapper Interrupt & Status Register.
|
|
fields:
|
|
- name: TEIF
|
|
description: Tearing Effect Interrupt Flag.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: ERIF
|
|
description: End of Refresh Interrupt Flag.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: BUSY
|
|
description: Busy Flag.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: PLLLS
|
|
description: PLL Lock Status.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: PLLLIF
|
|
description: PLL Lock Interrupt Flag.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: PLLUIF
|
|
description: PLL Unlock Interrupt Flag.
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: RRS
|
|
description: Regulator Ready Status.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: RRIF
|
|
description: Regulator Ready Interrupt Flag.
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
fieldset/WPCR0:
|
|
description: DSI Wrapper PHY Configuration Register 0.
|
|
fields:
|
|
- name: UIX4
|
|
description: Unit Interval multiplied by 4.
|
|
bit_offset: 0
|
|
bit_size: 6
|
|
- name: SWCL
|
|
description: Swap Clock Lane pins.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: SWDL0
|
|
description: Swap Data Lane 0 pins.
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: SWDL1
|
|
description: Swap Data Lane 1 pins.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: HSICL
|
|
description: Invert Hight-Speed data signal on Clock Lane.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HSIDL0
|
|
description: Invert the Hight-Speed data signal on Data Lane 0.
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: HSIDL1
|
|
description: Invert the High-Speed data signal on Data Lane 1.
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: FTXSMCL
|
|
description: Force in TX Stop Mode the Clock Lane.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: FTXSMDL
|
|
description: Force in TX Stop Mode the Data Lanes.
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: CDOFFDL
|
|
description: Contention Detection OFF on Data Lanes.
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TDDL
|
|
description: Turn Disable Data Lanes.
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: PDEN
|
|
description: Pull-Down Enable.
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: TCLKPREPEN
|
|
description: custom time for tCLK-PREPARE Enable.
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: TCLKZEROEN
|
|
description: custom time for tCLK-ZERO Enable.
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: THSPREPEN
|
|
description: custom time for tHS-PREPARE Enable.
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: THSTRAILEN
|
|
description: custom time for tHS-TRAIL Enable.
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: THSZEROEN
|
|
description: custom time for tHS-ZERO Enable.
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: TLPXDEN
|
|
description: custom time for tLPX for Data lanes Enable.
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: THSEXITEN
|
|
description: custom time for tHS-EXIT Enable.
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: TLPXCEN
|
|
description: custom time for tLPX for Clock lane Enable.
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: TCLKPOSTEN
|
|
description: custom time for tCLK-POST Enable.
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
fieldset/WPCR1:
|
|
description: DSI Wrapper PHY Configuration Register 1.
|
|
fields:
|
|
- name: HSTXDCL
|
|
description: High-Speed Transmission Delay on Clock Lane.
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: HSTXDLL
|
|
description: High-Speed Transmission Delay on Data Lanes.
|
|
bit_offset: 2
|
|
bit_size: 2
|
|
- name: LPSRCL
|
|
description: Low-Power transmission Slew Rate Compensation on Clock Lane.
|
|
bit_offset: 6
|
|
bit_size: 2
|
|
- name: LPSRDL
|
|
description: Low-Power transmission Slew Rate Compensation on Data Lanes.
|
|
bit_offset: 8
|
|
bit_size: 2
|
|
- name: SDCC
|
|
description: SDD Control.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: HSTXSRCCL
|
|
description: High-Speed Transmission Slew Rate Control on Clock Lane.
|
|
bit_offset: 16
|
|
bit_size: 2
|
|
- name: HSTXSRCDL
|
|
description: High-Speed Transmission Slew Rate Control on Data Lanes.
|
|
bit_offset: 18
|
|
bit_size: 2
|
|
- name: FLPRXLPM
|
|
description: Forces LP Receiver in Low-Power Mode.
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: LPRXFT
|
|
description: Low-Power RX low-pass Filtering Tuning.
|
|
bit_offset: 25
|
|
bit_size: 2
|
|
fieldset/WPCR2:
|
|
description: DSI Wrapper PHY Configuration Register 2.
|
|
fields:
|
|
- name: TCLKPREP
|
|
description: tCLK-PREPARE.
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
- name: TCLKZEO
|
|
description: tCLK-ZERO.
|
|
bit_offset: 8
|
|
bit_size: 8
|
|
- name: THSPREP
|
|
description: tHS-PREPARE.
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
- name: THSTRAIL
|
|
description: tHSTRAIL.
|
|
bit_offset: 24
|
|
bit_size: 8
|
|
fieldset/WPCR3:
|
|
description: DSI Wrapper PHY Configuration Register 3.
|
|
fields:
|
|
- name: THSZERO
|
|
description: tHS-ZERO.
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
- name: TLPXD
|
|
description: tLPX for Data lanes.
|
|
bit_offset: 8
|
|
bit_size: 8
|
|
- name: THSEXIT
|
|
description: tHSEXIT.
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
- name: TLPXC
|
|
description: tLPXC for Clock lane.
|
|
bit_offset: 24
|
|
bit_size: 8
|
|
fieldset/WPCR4:
|
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description: DSI Wrapper PHY Configuration Register 4.
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fields:
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- name: TCLKPOST
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description: tCLK-POST.
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bit_offset: 0
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bit_size: 8
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fieldset/WRPCR:
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description: DSI Wrapper Regulator and PLL Control Register.
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fields:
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- name: PLLEN
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description: PLL Enable.
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bit_offset: 0
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bit_size: 1
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- name: NDIV
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description: PLL Loop Division Factor.
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bit_offset: 2
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bit_size: 7
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- name: IDF
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description: PLL Input Division Factor.
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bit_offset: 11
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bit_size: 4
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- name: ODF
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description: PLL Output Division Factor.
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bit_offset: 16
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bit_size: 2
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- name: REGEN
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description: Regulator Enable.
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bit_offset: 24
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bit_size: 1
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