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stm32-data/data/registers/rcc_h7rs.yaml
Dario Nieuwenhuis 5d58d7ddda chiptool fmt.
2024-05-01 16:11:06 +02:00

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block/RCC:
description: Reset and clock control.
items:
- name: CR
description: RCC source control register.
byte_offset: 0
fieldset: CR
- name: HSICFGR
description: RCC HSI calibration register.
byte_offset: 4
fieldset: HSICFGR
- name: CRRCR
description: RCC clock recovery RC register.
byte_offset: 8
fieldset: CRRCR
- name: CSICFGR
description: RCC CSI calibration register.
byte_offset: 12
fieldset: CSICFGR
- name: CFGR
description: RCC clock configuration register.
byte_offset: 16
fieldset: CFGR
- name: CDCFGR
description: RCC CPU domain clock configuration register.
byte_offset: 24
fieldset: CDCFGR
- name: BMCFGR
description: RCC AHB clock configuration register.
byte_offset: 28
fieldset: BMCFGR
- name: APBCFGR
description: RCC APB clocks configuration register.
byte_offset: 32
fieldset: APBCFGR
- name: PLLCKSELR
description: RCC PLLs clock source selection register.
byte_offset: 40
fieldset: PLLCKSELR
- name: PLLCFGR
description: RCC PLLs configuration register.
byte_offset: 44
fieldset: PLLCFGR
- name: PLLDIVR
description: RCC PLL dividers configuration register 1.
array:
len: 3
stride: 8
byte_offset: 48
fieldset: PLLDIVR
- name: PLLFRACR
description: RCC PLL fractional divider register.
array:
len: 3
stride: 8
byte_offset: 52
fieldset: PLLFRACR
- name: AHBPERCKSELR
description: RCC AHB peripheral kernel clock selection register.
byte_offset: 76
fieldset: AHBPERCKSELR
- name: APB1PERCKSELR
description: RCC APB1 peripherals kernel clock selection register.
byte_offset: 80
fieldset: APB1PERCKSELR
- name: APB2PERCKSELR
description: RCC APB2 peripherals kernel clock selection register.
byte_offset: 84
fieldset: APB2PERCKSELR
- name: APB45PERCKSELR
description: RCC APB4,5 peripherals kernel clock selection register.
byte_offset: 88
fieldset: APB45PERCKSELR
- name: CIER
description: RCC clock source interrupt enable register.
byte_offset: 96
fieldset: CIER
- name: CIFR
description: RCC clock source interrupt flag register.
byte_offset: 100
fieldset: CIFR
- name: CICR
description: RCC clock source interrupt clear register.
byte_offset: 104
fieldset: CICR
- name: BDCR
description: RCC Backup domain control register.
byte_offset: 112
fieldset: BDCR
- name: CSR
description: RCC clock control and status register.
byte_offset: 116
fieldset: CSR
- name: AHB5RSTR
description: RCC AHB5 peripheral reset register.
byte_offset: 124
fieldset: AHB5RSTR
- name: AHB1RSTR
description: RCC AHB1 peripheral reset register.
byte_offset: 128
fieldset: AHB1RSTR
- name: AHB2RSTR
description: RCC AHB2 peripheral reset register.
byte_offset: 132
fieldset: AHB2RSTR
- name: AHB4RSTR
description: RCC AHB4 peripheral reset register.
byte_offset: 136
fieldset: AHB4RSTR
- name: APB5RSTR
description: RCC APB5 peripheral reset register.
byte_offset: 140
fieldset: APB5RSTR
- name: APB1RSTR1
description: RCC APB1 peripheral reset register 1.
byte_offset: 144
fieldset: APB1RSTR1
- name: APB1RSTR2
description: RCC APB1 peripheral reset register 2.
byte_offset: 148
fieldset: APB1RSTR2
- name: APB2RSTR
description: RCC APB2 peripheral reset register.
byte_offset: 152
fieldset: APB2RSTR
- name: APB4RSTR
description: RCC APB4 peripheral reset register.
byte_offset: 156
fieldset: APB4RSTR
- name: AHB3RSTR
description: RCC AHB3 peripheral reset register.
byte_offset: 164
fieldset: AHB3RSTR
- name: CKGDISR
description: RCC AXI clocks gating disable register.
byte_offset: 176
fieldset: CKGDISR
- name: PLLDIVR2
description: RCC PLL dividers configuration register 2.
array:
len: 3
stride: 4
byte_offset: 192
fieldset: PLLDIVR2
- name: PLLSSCGR
description: RCC PLL Spread Spectrum Clock Generator register.
array:
len: 3
stride: 4
byte_offset: 204
fieldset: PLLSSCGR
- name: CKPROTR
description: RCC clock protection register.
byte_offset: 256
fieldset: CKPROTR
- name: RSR
description: RCC Reset status register.
byte_offset: 304
fieldset: RSR
- name: AHB5ENR
description: RCC AHB5 clock enable register.
byte_offset: 308
fieldset: AHB5ENR
- name: AHB1ENR
description: RCC AHB1 clock enable register.
byte_offset: 312
fieldset: AHB1ENR
- name: AHB2ENR
description: RCC AHB2 clock enable register.
byte_offset: 316
fieldset: AHB2ENR
- name: AHB4ENR
description: RCC AHB4 clock enable register.
byte_offset: 320
fieldset: AHB4ENR
- name: APB5ENR
description: RCC APB5 clock enable register.
byte_offset: 324
fieldset: APB5ENR
- name: APB1ENR1
description: RCC APB1 clock enable register 1.
byte_offset: 328
fieldset: APB1ENR1
- name: APB1ENR2
description: RCC APB1 clock enable register 2.
byte_offset: 332
fieldset: APB1ENR2
- name: APB2ENR
description: RCC APB2 clock enable register.
byte_offset: 336
fieldset: APB2ENR
- name: APB4ENR
description: RCC APB4 clock enable register.
byte_offset: 340
fieldset: APB4ENR
- name: AHB3ENR
description: RCC AHB3 clock enable register.
byte_offset: 344
fieldset: AHB3ENR
- name: AHB5LPENR
description: RCC AHB5 low-power clock enable register.
byte_offset: 348
fieldset: AHB5LPENR
- name: AHB1LPENR
description: RCC AHB1 low-power clock enable register.
byte_offset: 352
fieldset: AHB1LPENR
- name: AHB2LPENR
description: RCC AHB2 low-power clock enable register.
byte_offset: 356
fieldset: AHB2LPENR
- name: AHB4LPENR
description: RCC AHB4 low-power clock enable register.
byte_offset: 360
fieldset: AHB4LPENR
- name: AHB3LPENR
description: RCC AHB3 low-power clock enable register.
byte_offset: 364
fieldset: AHB3LPENR
- name: APB1LPENR1
description: RCC APB1 low-power clock enable register 1.
byte_offset: 368
fieldset: APB1LPENR1
- name: APB1LPENR2
description: RCC APB1 low-power clock enable register 2.
byte_offset: 372
fieldset: APB1LPENR2
- name: APB2LPENR
description: RCC APB2 low-power clock enable register.
byte_offset: 376
fieldset: APB2LPENR
- name: APB4LPENR
description: RCC APB4 low-power clock enable register.
byte_offset: 380
fieldset: APB4LPENR
- name: APB5LPENR
description: RCC APB5 sleep clock register.
byte_offset: 384
fieldset: APB5LPENR
fieldset/AHB1ENR:
description: RCC AHB1 clock enable register.
fields:
- name: GPDMA1EN
description: GPDMA1 clock enable Set and reset by software.
bit_offset: 4
bit_size: 1
- name: ADC12EN
description: ADC1 and 2 peripheral clocks enable Set and reset by software. The peripheral clocks of the ADC1 and 2 are the kernel clock selected by ADCSEL and provided to ADCx_CK input, and the hclk1 bus interface clock.
bit_offset: 5
bit_size: 1
- name: ETHEN
description: ETH1 MAC peripheral clock enable Set and reset by software.
bit_offset: 15
bit_size: 1
- name: ETHTXEN
description: ETH1 transmission clock enable Set and reset by software.
bit_offset: 16
bit_size: 1
- name: ETHRXEN
description: ETH1 reception clock enable Set and reset by software.
bit_offset: 17
bit_size: 1
- name: USB_OTG_HSEN
description: OTGHS clocks enable Set and reset by software.
bit_offset: 25
bit_size: 1
- name: USBPHYCEN
description: USBPHYC clocks enable Set and reset by software.
bit_offset: 26
bit_size: 1
- name: USB_OTG_FSEN
description: OTGFS peripheral clocks enable Set and reset by software.
bit_offset: 27
bit_size: 1
- name: ADFEN
description: ADF clocks enable Set and reset by software.
bit_offset: 31
bit_size: 1
fieldset/AHB1LPENR:
description: RCC AHB1 low-power clock enable register.
fields:
- name: GPDMA1LPEN
description: GPDMA1 clock enable in low-power mode Set and reset by software.
bit_offset: 4
bit_size: 1
- name: ADC12LPEN
description: ADC1 and 2 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the ADC1 and 2 are the kernel clock selected by ADCSEL and provided to ADCx_CK input, and the rcc_hclk1 bus interface clock.
bit_offset: 5
bit_size: 1
- name: ETHLPEN
description: ETH1 MAC peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 15
bit_size: 1
- name: ETHTXLPEN
description: ETH1 transmission peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 16
bit_size: 1
- name: ETHRXLPEN
description: ETH1 reception peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 17
bit_size: 1
- name: USBPDCTRL
description: USBPHYC common block power-down control Set and reset by software.
bit_offset: 24
bit_size: 1
enum: USBPDCTRL
- name: USB_OTG_HSLPEN
description: OTGHS peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 25
bit_size: 1
- name: USBPHYCLPEN
description: USBPHYC peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 26
bit_size: 1
- name: USB_OTG_FSLPEN
description: OTGFS clock enable in low-power mode Set and reset by software.
bit_offset: 27
bit_size: 1
- name: ADFLPEN
description: ADF clock enable in low-power mode Set and reset by software.
bit_offset: 31
bit_size: 1
fieldset/AHB1RSTR:
description: RCC AHB1 peripheral reset register.
fields:
- name: GPDMA1RST
description: GPDMA1 blocks reset Set and reset by software.
bit_offset: 4
bit_size: 1
- name: ADC12RST
description: ADC1 and 2 blocks reset Set and reset by software.
bit_offset: 5
bit_size: 1
- name: ETHRST
description: ETH1 block reset Set and reset by software.
bit_offset: 15
bit_size: 1
- name: USB_OTG_HSRST
description: OTGHS block reset Set and reset by software.
bit_offset: 25
bit_size: 1
- name: USBPHYCRST
description: USBPHYC block reset Set and reset by software.
bit_offset: 26
bit_size: 1
- name: USB_OTG_FSRST
description: OTGFS block reset Set and reset by software.
bit_offset: 27
bit_size: 1
- name: ADFRST
description: ADF block reset Set and reset by software.
bit_offset: 31
bit_size: 1
fieldset/AHB2ENR:
description: RCC AHB2 clock enable register.
fields:
- name: PSSIEN
description: PSSI peripheral clocks enable Set and reset by software.
bit_offset: 1
bit_size: 1
- name: SDMMC2EN
description: SDMMC2 and SDMMC2 delay clock enable Set and reset by software.
bit_offset: 9
bit_size: 1
- name: CORDICEN
description: CORDIC clock enable Set and reset by software.
bit_offset: 14
bit_size: 1
- name: SRAM1EN
description: SRAM1 clock enable Set and reset by software.
bit_offset: 29
bit_size: 1
- name: SRAM2EN
description: SRAM2 clock enable Set and reset by software.
bit_offset: 30
bit_size: 1
fieldset/AHB2LPENR:
description: RCC AHB2 low-power clock enable register.
fields:
- name: PSSILPEN
description: PSSI peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 1
bit_size: 1
- name: SDMMC2LPEN
description: SDMMC2 and SDMMC2 delay clock enable in low-power mode Set and reset by software.
bit_offset: 9
bit_size: 1
- name: CORDICLPEN
description: CORDIC clock enable in low-power mode Set and reset by software.
bit_offset: 14
bit_size: 1
- name: SRAM1LPEN
description: SRAM1 clock enable in low-power mode Set and reset by software.
bit_offset: 29
bit_size: 1
- name: SRAM2LPEN
description: SRAM2 clock enable in low-power mode Set and reset by software.
bit_offset: 30
bit_size: 1
fieldset/AHB2RSTR:
description: RCC AHB2 peripheral reset register.
fields:
- name: PSSIRST
description: PSSI block reset Set and reset by software.
bit_offset: 1
bit_size: 1
- name: SDMMC2RST
description: SDMMC2 and SDMMC2 delay blocks reset Set and reset by software.
bit_offset: 9
bit_size: 1
- name: CORDICRST
description: CORDIC reset Set and reset by software.
bit_offset: 14
bit_size: 1
fieldset/AHB3ENR:
description: RCC AHB3 clock enable register.
fields:
- name: RNGEN
description: RNG peripheral clocks enable Set and reset by software.
bit_offset: 0
bit_size: 1
- name: HASHEN
description: HASH peripheral clock enable Set and reset by software.
bit_offset: 1
bit_size: 1
- name: CRYPEN
description: CRYP peripheral clock enable Set and reset by software.
bit_offset: 2
bit_size: 1
- name: SAESEN
description: SAES peripheral clock enable Set and reset by software. This bit controls the enable of the clock delivered to the SAES.
bit_offset: 4
bit_size: 1
- name: PKAEN
description: PKA peripheral clock enable Set and reset by software.
bit_offset: 6
bit_size: 1
fieldset/AHB3LPENR:
description: RCC AHB3 low-power clock enable register.
fields:
- name: RNGLPEN
description: RNG peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 0
bit_size: 1
- name: HASHLPEN
description: HASH peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 1
bit_size: 1
- name: CRYPLPEN
description: CRYP peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 2
bit_size: 1
- name: SAESLPEN
description: SAES peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 4
bit_size: 1
- name: PKALPEN
description: PKA peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 6
bit_size: 1
fieldset/AHB3RSTR:
description: RCC AHB3 peripheral reset register.
fields:
- name: RNGRST
description: random number generator block reset Set and reset by software.
bit_offset: 0
bit_size: 1
- name: HASHRST
description: HASH block reset Set and reset by software.
bit_offset: 1
bit_size: 1
- name: CRYPRST
description: CRYP block reset Set and reset by software.
bit_offset: 2
bit_size: 1
- name: SAESRST
description: SAES block reset Set and reset by software.
bit_offset: 4
bit_size: 1
- name: PKARST
description: PKA block reset Set and reset by software.
bit_offset: 6
bit_size: 1
fieldset/AHB4ENR:
description: RCC AHB4 clock enable register.
fields:
- name: GPIOAEN
description: GPIOA peripheral clock enable Set and reset by software.
bit_offset: 0
bit_size: 1
- name: GPIOBEN
description: GPIOB peripheral clock enable Set and reset by software.
bit_offset: 1
bit_size: 1
- name: GPIOCEN
description: GPIOC peripheral clock enable Set and reset by software.
bit_offset: 2
bit_size: 1
- name: GPIODEN
description: GPIOD peripheral clock enable Set and reset by software.
bit_offset: 3
bit_size: 1
- name: GPIOEEN
description: GPIOE peripheral clock enable Set and reset by software.
bit_offset: 4
bit_size: 1
- name: GPIOFEN
description: GPIOF peripheral clock enable Set and reset by software.
bit_offset: 5
bit_size: 1
- name: GPIOGEN
description: GPIOG peripheral clock enable Set and reset by software.
bit_offset: 6
bit_size: 1
- name: GPIOHEN
description: GPIOH peripheral clock enable Set and reset by software.
bit_offset: 7
bit_size: 1
- name: GPIOMEN
description: GPIOM peripheral clock enable Set and reset by software.
bit_offset: 12
bit_size: 1
- name: GPIONEN
description: GPION peripheral clock enable Set and reset by software.
bit_offset: 13
bit_size: 1
- name: GPIOOEN
description: GPIOO peripheral clock enable Set and reset by software.
bit_offset: 14
bit_size: 1
- name: GPIOPEN
description: GPIOP peripheral clock enable Set and reset by software.
bit_offset: 15
bit_size: 1
- name: CRCEN
description: CRC clock enable Set and reset by software.
bit_offset: 19
bit_size: 1
- name: BKPRAMEN
description: Backup RAM clock enable Set and reset by software.
bit_offset: 28
bit_size: 1
fieldset/AHB4LPENR:
description: RCC AHB4 low-power clock enable register.
fields:
- name: GPIOALPEN
description: GPIOA peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 0
bit_size: 1
- name: GPIOBLPEN
description: GPIOB peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 1
bit_size: 1
- name: GPIOCLPEN
description: GPIOC peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 2
bit_size: 1
- name: GPIODLPEN
description: GPIOD peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 3
bit_size: 1
- name: GPIOELPEN
description: GPIOE peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 4
bit_size: 1
- name: GPIOFLPEN
description: GPIOF peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 5
bit_size: 1
- name: GPIOGLPEN
description: GPIOG peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 6
bit_size: 1
- name: GPIOHLPEN
description: GPIOH peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 7
bit_size: 1
- name: GPIOMLPEN
description: GPIOM peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 12
bit_size: 1
- name: GPIONLPEN
description: GPION peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 13
bit_size: 1
- name: GPIOOLPEN
description: GPIOO peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 14
bit_size: 1
- name: GPIOPLPEN
description: GPIOP peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 15
bit_size: 1
- name: CRCLPEN
description: CRC clock enable in low-power mode Set and reset by software.
bit_offset: 19
bit_size: 1
- name: BKPRAMLPEN
description: Backup RAM clock enable in low-power mode Set and reset by software.
bit_offset: 28
bit_size: 1
fieldset/AHB4RSTR:
description: RCC AHB4 peripheral reset register.
fields:
- name: GPIOARST
description: GPIOA block reset Set and reset by software.
bit_offset: 0
bit_size: 1
- name: GPIOBRST
description: GPIOB block reset Set and reset by software.
bit_offset: 1
bit_size: 1
- name: GPIOCRST
description: GPIOC block reset Set and reset by software.
bit_offset: 2
bit_size: 1
- name: GPIODRST
description: GPIOD block reset Set and reset by software.
bit_offset: 3
bit_size: 1
- name: GPIOERST
description: GPIOE block reset Set and reset by software.
bit_offset: 4
bit_size: 1
- name: GPIOFRST
description: GPIOF block reset Set and reset by software.
bit_offset: 5
bit_size: 1
- name: GPIOGRST
description: GPIOG block reset Set and reset by software.
bit_offset: 6
bit_size: 1
- name: GPIOHRST
description: GPIOH block reset Set and reset by software.
bit_offset: 7
bit_size: 1
- name: GPIOMRST
description: GPIOM block reset Set and reset by software.
bit_offset: 12
bit_size: 1
- name: GPIONRST
description: GPION block reset Set and reset by software.
bit_offset: 13
bit_size: 1
- name: GPIOORST
description: GPIOO block reset Set and reset by software.
bit_offset: 14
bit_size: 1
- name: GPIOPRST
description: GPIOP block reset Set and reset by software.
bit_offset: 15
bit_size: 1
- name: CRCRST
description: CRC block reset Set and reset by software.
bit_offset: 19
bit_size: 1
fieldset/AHB5ENR:
description: RCC AHB5 clock enable register.
fields:
- name: HPDMA1EN
description: HPDMA1 peripheral clock enable Set and reset by software.
bit_offset: 0
bit_size: 1
- name: DMA2DEN
description: DMA2D peripheral clock enable Set and reset by software.
bit_offset: 1
bit_size: 1
- name: JPEGEN
description: JPEG peripheral clock enable Set and reset by software.
bit_offset: 3
bit_size: 1
- name: FMCEN
description: FMC and MCE3 peripheral clocks enable Set and reset by software. The hardware prevents writing this bit if FMCCKP = 1. The peripheral clocks of the FMC are the kernel clock selected by FMCSEL, and the hclk5 bus interface clock.
bit_offset: 4
bit_size: 1
- name: XSPI1EN
description: XSPI1 and MCE1 peripheral clocks enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1.
bit_offset: 5
bit_size: 1
- name: SDMMC1EN
description: SDMMC1 and DB_SDMMC1 peripheral clocks enable Set and reset by software.
bit_offset: 8
bit_size: 1
- name: XSPI2EN
description: XSPI2 and MCE2 peripheral clocks enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1.
bit_offset: 12
bit_size: 1
- name: IOMNGREN
description: XSPIM peripheral clock enable Set and reset by software.
bit_offset: 14
bit_size: 1
- name: GFXMMUEN
description: GFXMMU peripheral clock enable Set and reset by software.
bit_offset: 19
bit_size: 1
- name: GPUEN
description: GPU peripheral clock enable Set and reset by software.
bit_offset: 20
bit_size: 1
fieldset/AHB5LPENR:
description: RCC AHB5 low-power clock enable register.
fields:
- name: HPDMA1LPEN
description: HPDMA1 low-power peripheral clock enable Set and reset by software.
bit_offset: 0
bit_size: 1
- name: DMA2DLPEN
description: DMA2D low-power peripheral clock enable Set and reset by software.
bit_offset: 1
bit_size: 1
- name: FLITFLPEN
description: FLITF low-power peripheral clock enable Set and reset by software.
bit_offset: 2
bit_size: 1
- name: JPEGLPEN
description: JPEG clock enable during Sleep mode Set and reset by software.
bit_offset: 3
bit_size: 1
- name: FMCLPEN
description: FMC and MCE3 peripheral clocks enable during Sleep mode Set and reset by software. The hardware prevents writing this bit if FMCCKP = 1. The peripheral clocks of the FMC are the kernel clock selected by FMCSEL, and the hclk5 bus interface clock.
bit_offset: 4
bit_size: 1
- name: XSPI1LPEN
description: XSPI1 and MCE1 low-power peripheral clock enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1.
bit_offset: 5
bit_size: 1
- name: SDMMC1LPEN
description: SDMMC1 and SDMMC1 delay low-power peripheral clock enable Set and reset by software.
bit_offset: 8
bit_size: 1
- name: XSPI2LPEN
description: XSPI2 and MCE2 low-power peripheral clock enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1.
bit_offset: 12
bit_size: 1
- name: XSPIMLPEN
description: XSPIM low-power peripheral clock enable Set and reset by software.
bit_offset: 14
bit_size: 1
- name: GFXMMULPEN
description: GFXMMU low-power peripheral clock enable Set and reset by software.
bit_offset: 19
bit_size: 1
- name: GPULPEN
description: GPU low-power peripheral clock enable Set and reset by software.
bit_offset: 20
bit_size: 1
- name: DTCM1LPEN
description: DTCM1 low-power peripheral clock enable Set and reset by software.
bit_offset: 28
bit_size: 1
- name: DTCM2LPEN
description: DTCM2 low-power peripheral clock enable Set and reset by software.
bit_offset: 29
bit_size: 1
- name: ITCMLPEN
description: ITCM low-power peripheral clock enable Set and reset by software.
bit_offset: 30
bit_size: 1
- name: AXISRAMLPEN
description: AXISRAM[4:1] low-power peripheral clock enable Set and reset by software.
bit_offset: 31
bit_size: 1
fieldset/AHB5RSTR:
description: RCC AHB5 peripheral reset register.
fields:
- name: HPDMA1RST
description: HPDMA1 block reset Set and reset by software.
bit_offset: 0
bit_size: 1
- name: DMA2DRST
description: DMA2D block reset Set and reset by software.
bit_offset: 1
bit_size: 1
- name: JPEGRST
description: JPEG block reset Set and reset by software.
bit_offset: 3
bit_size: 1
- name: FMCRST
description: FMC and MCE3 blocks reset Set and reset by software. The hardware prevents writing this bit if FMCCKP = 1.
bit_offset: 4
bit_size: 1
- name: XSPI1RST
description: XSPI1 and MCE1 blocks reset Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1.
bit_offset: 5
bit_size: 1
- name: SDMMC1RST
description: SDMMC1 and DB_SDMMC1 blocks reset Set and reset by software.
bit_offset: 8
bit_size: 1
- name: XSPI2RST
description: XSPI2 and MCE2 blocks reset Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1.
bit_offset: 12
bit_size: 1
- name: IOMNGRRST
description: XSPIM reset Set and reset by software.
bit_offset: 14
bit_size: 1
- name: GFXMMURST
description: GFXMMU block reset Set and reset by software.
bit_offset: 19
bit_size: 1
- name: GPURST
description: GPU block reset Set and reset by software.
bit_offset: 20
bit_size: 1
fieldset/AHBPERCKSELR:
description: RCC AHB peripheral kernel clock selection register.
fields:
- name: FMCSEL
description: FMC kernel clock source selection Set and reset by software.
bit_offset: 0
bit_size: 2
enum: FMCSEL
- name: SDMMCSEL
description: SDMMC1 and SDMMC2 kernel clock source selection Set and reset by software.
bit_offset: 2
bit_size: 1
enum: SDMMCSEL
- name: OCTOSPI1SEL
description: 'XSPI1 kernel clock source selection Set and reset by software. 1x: pll2_t_ck selected as kernel peripheral clock.'
bit_offset: 4
bit_size: 2
enum: OCTOSPISEL
- name: OCTOSPI2SEL
description: 'XSPI2 kernel clock source selection Set and reset by software. 1x: pll2_t_ck selected as kernel peripheral clock.'
bit_offset: 6
bit_size: 2
enum: OCTOSPISEL
- name: USBREFCKSEL
description: 'USBPHYC kernel clock frequency selection Set and reset by software. This field is used to indicate to the USBPHYC, the frequency of the reference kernel clock provided to the USBPHYC. others: reserved.'
bit_offset: 8
bit_size: 4
enum: USBREFCKSEL
- name: USBPHYCSEL
description: USBPHYC kernel clock source selection Set and reset by software.
bit_offset: 12
bit_size: 2
enum: USBPHYCSEL
- name: USB_OTG_FSSEL
description: OTGFS kernel clock source selection Set and reset by software.
bit_offset: 14
bit_size: 2
enum: USB_OTG_FSSEL
- name: ETH_REF_CLK_SEL
description: 'Ethernet reference clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.'
bit_offset: 16
bit_size: 2
enum: ETH_REF_CLK_SEL
- name: ETHPHY_CLK_SEL
description: Clock source selection for external Ethernet PHY Set and reset by software.
bit_offset: 18
bit_size: 1
enum: ETHPHY_CLK_SEL
- name: ADFSEL
description: 'ADF kernel clock source selection Set and reset by software. Note: I2S_CKIN is an external clock taken from a pin.'
bit_offset: 20
bit_size: 3
enum: ADFSEL
- name: ADCSEL
description: 'SAR ADC kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.'
bit_offset: 24
bit_size: 2
enum: ADCSEL
- name: PSSISEL
description: PSSI kernel clock source selection Set and reset by software.
bit_offset: 27
bit_size: 1
enum: PSSISEL
- name: PERSEL
description: per_ck clock source selection.
bit_offset: 28
bit_size: 2
enum: PERSEL
fieldset/APB1ENR1:
description: RCC APB1 clock enable register 1.
fields:
- name: TIM2EN
description: TIM2 peripheral clock enable Set and reset by software.
bit_offset: 0
bit_size: 1
- name: TIM3EN
description: TIM3 peripheral clock enable Set and reset by software.
bit_offset: 1
bit_size: 1
- name: TIM4EN
description: TIM4 peripheral clock enable Set and reset by software.
bit_offset: 2
bit_size: 1
- name: TIM5EN
description: TIM5 peripheral clock enable Set and reset by software.
bit_offset: 3
bit_size: 1
- name: TIM6EN
description: TIM6 peripheral clock enable Set and reset by software.
bit_offset: 4
bit_size: 1
- name: TIM7EN
description: TIM7 peripheral clock enable Set and reset by software.
bit_offset: 5
bit_size: 1
- name: TIM12EN
description: TIM12 peripheral clock enable Set and reset by software.
bit_offset: 6
bit_size: 1
- name: TIM13EN
description: TIM13 peripheral clock enable Set and reset by software.
bit_offset: 7
bit_size: 1
- name: TIM14EN
description: TIM14 peripheral clock enable Set and reset by software.
bit_offset: 8
bit_size: 1
- name: LPTIM1EN
description: LPTIM1 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPTIM1 are the kernel clock selected by LPTIM1SEL and provided to clk_lpt input, and the rcc_pclk1 bus interface clock.
bit_offset: 9
bit_size: 1
- name: WWDGEN
description: WWDG clock enable Set by software, and reset by hardware when a system reset occurs.
bit_offset: 11
bit_size: 1
- name: SPI2EN
description: SPI2 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI2 are the kernel clock selected by I2S123SRC and provided to com_clk input, and the rcc_pclk1 bus interface clock.
bit_offset: 14
bit_size: 1
- name: SPI3EN
description: SPI3 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI3 are the kernel clock selected by I2S123SRC and provided to com_clk input, and the rcc_pclk1 bus interface clock.
bit_offset: 15
bit_size: 1
- name: SPDIFRXEN
description: SPDIFRX peripheral clocks enable Set and reset by software. The peripheral clocks of the SPDIFRX are the kernel clock selected by SPDIFRXSEL and provided to SPDIFRX_CLK input, and the rcc_pclk1 bus interface clock.
bit_offset: 16
bit_size: 1
- name: USART2EN
description: USART2peripheral clocks enable Set and reset by software. The peripheral clocks of the USART2 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock.
bit_offset: 17
bit_size: 1
- name: USART3EN
description: USART3 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART3 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock.
bit_offset: 18
bit_size: 1
- name: UART4EN
description: UART4 peripheral clocks enable Set and reset by software. The peripheral clocks of the UART4 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock.
bit_offset: 19
bit_size: 1
- name: UART5EN
description: UART5 peripheral clocks enable Set and reset by software.
bit_offset: 20
bit_size: 1
- name: I2C1_I3C1EN
description: I2C1/I3C1 peripheral clocks enable Set and reset by software.
bit_offset: 21
bit_size: 1
- name: I2C2EN
description: I2C2 peripheral clocks enable Set and reset by software.
bit_offset: 22
bit_size: 1
- name: I2C3EN
description: I2C3 peripheral clocks enable Set and reset by software.
bit_offset: 23
bit_size: 1
- name: CECEN
description: HDMI-CEC peripheral clock enable Set and reset by software.
bit_offset: 27
bit_size: 1
- name: UART7EN
description: UART7 peripheral clocks enable Set and reset by software.
bit_offset: 30
bit_size: 1
- name: UART8EN
description: UART8 peripheral clocks enable Set and reset by software.
bit_offset: 31
bit_size: 1
fieldset/APB1ENR2:
description: RCC APB1 clock enable register 2.
fields:
- name: CRSEN
description: clock recovery system peripheral clock enable Set and reset by software.
bit_offset: 1
bit_size: 1
- name: MDIOSEN
description: MDIOS peripheral clock enable Set and reset by software.
bit_offset: 5
bit_size: 1
- name: FDCANEN
description: FDCAN peripheral clock enable Set and reset by software.
bit_offset: 8
bit_size: 1
- name: UCPDEN
description: UCPD peripheral clock enable Set and reset by software.
bit_offset: 27
bit_size: 1
fieldset/APB1LPENR1:
description: RCC APB1 low-power clock enable register 1.
fields:
- name: TIM2LPEN
description: TIM2 peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 0
bit_size: 1
- name: TIM3LPEN
description: TIM3 peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 1
bit_size: 1
- name: TIM4LPEN
description: TIM4 peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 2
bit_size: 1
- name: TIM5LPEN
description: TIM5 peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 3
bit_size: 1
- name: TIM6LPEN
description: TIM6 peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 4
bit_size: 1
- name: TIM7LPEN
description: TIM7 peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 5
bit_size: 1
- name: TIM12LPEN
description: TIM12 peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 6
bit_size: 1
- name: TIM13LPEN
description: TIM13 peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 7
bit_size: 1
- name: TIM14LPEN
description: TIM14 peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 8
bit_size: 1
- name: LPTIM1LPEN
description: LPTIM1 peripheral clocks enable in low-power mode Set and reset by software.
bit_offset: 9
bit_size: 1
- name: WWDGLPEN
description: WWDG clock enable in low-power mode Set and reset by software.
bit_offset: 11
bit_size: 1
- name: SPI2LPEN
description: SPI2 peripheral clocks enable in low-power mode Set and reset by software.
bit_offset: 14
bit_size: 1
- name: SPI3LPEN
description: SPI3 peripheral clocks enable in low-power mode Set and reset by software.
bit_offset: 15
bit_size: 1
- name: SPDIFRXLPEN
description: SPDIFRX peripheral clocks enable in low-power mode Set and reset by software.
bit_offset: 16
bit_size: 1
- name: USART2LPEN
description: USART2 peripheral clocks enable in low-power mode Set and reset by software.
bit_offset: 17
bit_size: 1
- name: USART3LPEN
description: USART3 peripheral clocks enable in low-power mode Set and reset by software.
bit_offset: 18
bit_size: 1
- name: UART4LPEN
description: UART4 peripheral clocks enable in low-power mode Set and reset by software.
bit_offset: 19
bit_size: 1
- name: UART5LPEN
description: UART5 peripheral clocks enable in low-power mode Set and reset by software.
bit_offset: 20
bit_size: 1
- name: I2C1_I3C1LPEN
description: I2C1/I3C1 peripheral clocks enable in low-power mode Set and reset by software.
bit_offset: 21
bit_size: 1
- name: I2C2LPEN
description: I2C2 peripheral clocks enable in low-power mode Set and reset by software.
bit_offset: 22
bit_size: 1
- name: I2C3LPEN
description: I2C3 peripheral clocks enable in low-power mode Set and reset by software.
bit_offset: 23
bit_size: 1
- name: CECLPEN
description: HDMI-CEC peripheral clocks enable in low-power mode Set and reset by software.
bit_offset: 27
bit_size: 1
- name: UART7LPEN
description: UART7 peripheral clocks enable in low-power mode Set and reset by software.
bit_offset: 30
bit_size: 1
- name: UART8LPEN
description: UART8 peripheral clocks enable in low-power mode Set and reset by software.
bit_offset: 31
bit_size: 1
fieldset/APB1LPENR2:
description: RCC APB1 low-power clock enable register 2.
fields:
- name: CRSLPEN
description: clock recovery system peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 1
bit_size: 1
- name: MDIOSLPEN
description: MDIOS peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 5
bit_size: 1
- name: FDCANLPEN
description: FDCAN peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 8
bit_size: 1
- name: UCPDLPEN
description: UCPD peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 27
bit_size: 1
fieldset/APB1PERCKSELR:
description: RCC APB1 peripherals kernel clock selection register.
fields:
- name: USART234578SEL
description: 'USART2,3, UART4,5,7,8 (APB1) kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.'
bit_offset: 0
bit_size: 3
enum: USART234578SEL
- name: SPI23SEL
description: 'SPI/I2S2 and SPI/I2S3 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin.'
bit_offset: 4
bit_size: 3
enum: SPI123SEL
- name: I2C23SEL
description: I2C2, I2C3 kernel clock source selection Set and reset by software.
bit_offset: 8
bit_size: 2
enum: I2CSEL
- name: I2C1_I3C1SEL
description: I2C1 or I3C1 kernel clock source selection Set and reset by software.
bit_offset: 12
bit_size: 2
enum: I2C1_I3C1SEL
- name: LPTIM1SEL
description: 'LPTIM1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.'
bit_offset: 16
bit_size: 3
enum: LPTIM1SEL
- name: FDCANSEL
description: FDCAN kernel clock source selection.
bit_offset: 22
bit_size: 2
enum: FDCANSEL
- name: SPDIFRXSEL
description: SPDIFRX kernel clock source selection.
bit_offset: 24
bit_size: 2
enum: SPDIFRXSEL
- name: CECSEL
description: HDMI-CEC kernel clock source selection Set and reset by software.
bit_offset: 28
bit_size: 2
enum: CECSEL
fieldset/APB1RSTR1:
description: RCC APB1 peripheral reset register 1.
fields:
- name: TIM2RST
description: TIM2 block reset Set and reset by software.
bit_offset: 0
bit_size: 1
- name: TIM3RST
description: TIM3 block reset Set and reset by software.
bit_offset: 1
bit_size: 1
- name: TIM4RST
description: TIM4 block reset Set and reset by software.
bit_offset: 2
bit_size: 1
- name: TIM5RST
description: TIM5 block reset Set and reset by software.
bit_offset: 3
bit_size: 1
- name: TIM6RST
description: TIM6 block reset Set and reset by software.
bit_offset: 4
bit_size: 1
- name: TIM7RST
description: TIM7 block reset Set and reset by software.
bit_offset: 5
bit_size: 1
- name: TIM12RST
description: TIM12 block reset Set and reset by software.
bit_offset: 6
bit_size: 1
- name: TIM13RST
description: TIM13 block reset Set and reset by software.
bit_offset: 7
bit_size: 1
- name: TIM14RST
description: TIM14 block reset Set and reset by software.
bit_offset: 8
bit_size: 1
- name: LPTIM1RST
description: LPTIM1 block reset Set and reset by software.
bit_offset: 9
bit_size: 1
- name: SPI2RST
description: SPI2S2 block reset Set and reset by software.
bit_offset: 14
bit_size: 1
- name: SPI3RST
description: SPI2S3 block reset Set and reset by software.
bit_offset: 15
bit_size: 1
- name: SPDIFRXRST
description: SPDIFRX block reset Set and reset by software.
bit_offset: 16
bit_size: 1
- name: USART2RST
description: USART2 block reset Set and reset by software.
bit_offset: 17
bit_size: 1
- name: USART3RST
description: USART3 block reset Set and reset by software.
bit_offset: 18
bit_size: 1
- name: UART4RST
description: UART4 block reset Set and reset by software.
bit_offset: 19
bit_size: 1
- name: UART5RST
description: UART5 block reset Set and reset by software.
bit_offset: 20
bit_size: 1
- name: I2C1_I3C1RST
description: I2C1/I3C1 block reset Set and reset by software.
bit_offset: 21
bit_size: 1
- name: I2C2RST
description: I2C2 block reset Set and reset by software.
bit_offset: 22
bit_size: 1
- name: I2C3RST
description: I2C3 block reset Set and reset by software.
bit_offset: 23
bit_size: 1
- name: CECRST
description: HDMI-CEC block reset Set and reset by software.
bit_offset: 27
bit_size: 1
- name: UART7RST
description: UART7 block reset Set and reset by software.
bit_offset: 30
bit_size: 1
- name: UART8RST
description: UART8 block reset Set and reset by software.
bit_offset: 31
bit_size: 1
fieldset/APB1RSTR2:
description: RCC APB1 peripheral reset register 2.
fields:
- name: CRSRST
description: clock recovery system reset Set and reset by software.
bit_offset: 1
bit_size: 1
- name: MDIOSRST
description: MDIOS block reset Set and reset by software.
bit_offset: 5
bit_size: 1
- name: FDCANRST
description: FDCAN block reset Set and reset by software.
bit_offset: 8
bit_size: 1
- name: UCPDRST
description: UCPD block reset Set and reset by software.
bit_offset: 27
bit_size: 1
fieldset/APB2ENR:
description: RCC APB2 clock enable register.
fields:
- name: TIM1EN
description: TIM1 peripheral clock enable Set and reset by software.
bit_offset: 0
bit_size: 1
- name: USART1EN
description: USART1 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART1 are the kernel clock selected by USART1SEL, and the pclk2 bus interface clock.
bit_offset: 4
bit_size: 1
- name: SPI1EN
description: 'SPI2S1 Peripheral Clocks Enable Set and reset by software. The peripheral clocks of the SPI2S1 are: the kernel clock selected by SPI1SEL, and the pclk2 bus interface clock.'
bit_offset: 12
bit_size: 1
- name: SPI4EN
description: 'SPI4 Peripheral Clocks Enable Set and reset by software. The peripheral clocks of the SPI4 are: the kernel clock selected by SPI45SEL, and the pclk2 bus interface clock.'
bit_offset: 13
bit_size: 1
- name: TIM15EN
description: TIM15 peripheral clock enable Set and reset by software.
bit_offset: 16
bit_size: 1
- name: TIM16EN
description: TIM16 peripheral clock enable Set and reset by software.
bit_offset: 17
bit_size: 1
- name: TIM17EN
description: TIM17 peripheral clock enable Set and reset by software.
bit_offset: 18
bit_size: 1
- name: TIM9EN
description: TIM9 peripheral clock enable Set and reset by software.
bit_offset: 19
bit_size: 1
- name: SPI5EN
description: SPI5 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI5 are the kernel clock selected by SPI45SEL, and the pclk2 bus interface clock.
bit_offset: 20
bit_size: 1
- name: SAI1EN
description: SAI1 peripheral clocks enable Set and reset by software. The peripheral clocks of the SAI1 are the kernel clock selected by SAI1SEL, and the pclk2 bus interface clock.
bit_offset: 22
bit_size: 1
- name: SAI2EN
description: SAI2 peripheral clocks enable Set and reset by software. The peripheral clocks of the SAI2 are the kernel clock selected by SAI2SEL, and the pclk2 bus interface clock.
bit_offset: 23
bit_size: 1
fieldset/APB2LPENR:
description: RCC APB2 low-power clock enable register.
fields:
- name: TIM1LPEN
description: TIM1 peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 0
bit_size: 1
- name: USART1LPEN
description: USART1 peripheral clock enable in low-power mode Set and reset by software. The peripheral clocks of the USART1 are the kernel clock selected by USART169SEL and provided to UCLK inputs, and the pclk2 bus interface clock.
bit_offset: 4
bit_size: 1
- name: SPI1LPEN
description: 'SPI2S1 peripheral clock enable in low-power mode Set and reset by software. The peripheral clocks of the SPI2S1 are: the kernel clock selected by I2S1SEL and provided to spi_ker_ck input, and the pclk2 bus interface clock.'
bit_offset: 12
bit_size: 1
- name: SPI4LPEN
description: 'SPI4 peripheral clock enable in low-power mode Set and reset by software. The peripheral clocks of the SPI4 are: the kernel clock selected by SPI45SEL and provided to com_clk input, and the pclk2 bus interface clock.'
bit_offset: 13
bit_size: 1
- name: TIM15LPEN
description: TIM15 peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 16
bit_size: 1
- name: TIM16LPEN
description: TIM16 peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 17
bit_size: 1
- name: TIM17LPEN
description: TIM17 peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 18
bit_size: 1
- name: TIM9LPEN
description: TIM9 peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 19
bit_size: 1
- name: SPI5LPEN
description: SPI5 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the SPI5 are the kernel clock selected by SPI45SEL and provided to com_clk input, and the pclk2 bus interface clock.
bit_offset: 20
bit_size: 1
- name: SAI1LPEN
description: 'SAI1 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the SAI1 are: the kernel clock selected by SAI1SEL and provided to SAI_CK_A and SAI_CK_B inputs, and the pclk2 bus interface clock.'
bit_offset: 22
bit_size: 1
- name: SAI2LPEN
description: 'SAI2 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the SAI2 are: the kernel clock selected by SAI2SEL and provided to SAI_CK_A and SAI_CK_B inputs, and the pclk2 bus interface clock.'
bit_offset: 23
bit_size: 1
fieldset/APB2PERCKSELR:
description: RCC APB2 peripherals kernel clock selection register.
fields:
- name: USART1SEL
description: 'USART1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.'
bit_offset: 0
bit_size: 3
enum: USART1SEL
- name: SPI45SEL
description: 'SPI4 and 5 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.'
bit_offset: 4
bit_size: 3
enum: SPI45SEL
- name: SPI1SEL
description: 'SPI/I2S1 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin.'
bit_offset: 8
bit_size: 3
enum: SPI123SEL
- name: SAI1SEL
description: 'SAI1 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin.'
bit_offset: 16
bit_size: 3
enum: SAI1SEL
- name: SAI2SEL
description: 'SAI2 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. spdifrx_symb_ck is the symbol clock generated by the spdifrx (see Figure 51).'
bit_offset: 20
bit_size: 3
enum: SAI2SEL
fieldset/APB2RSTR:
description: RCC APB2 peripheral reset register.
fields:
- name: TIM1RST
description: TIM1 block reset Set and reset by software.
bit_offset: 0
bit_size: 1
- name: USART1RST
description: USART1 block reset Set and reset by software.
bit_offset: 4
bit_size: 1
- name: SPI1RST
description: SPI2S1 block reset Set and reset by software.
bit_offset: 12
bit_size: 1
- name: SPI4RST
description: SPI4 block reset Set and reset by software.
bit_offset: 13
bit_size: 1
- name: TIM15RST
description: TIM15 block reset Set and reset by software.
bit_offset: 16
bit_size: 1
- name: TIM16RST
description: TIM16 block reset Set and reset by software.
bit_offset: 17
bit_size: 1
- name: TIM17RST
description: TIM17 block reset Set and reset by software.
bit_offset: 18
bit_size: 1
- name: TIM9RST
description: TIM9 block reset Set and reset by software.
bit_offset: 19
bit_size: 1
- name: SPI5RST
description: SPI5 block reset Set and reset by software.
bit_offset: 20
bit_size: 1
- name: SAI1RST
description: SAI1 block reset Set and reset by software.
bit_offset: 22
bit_size: 1
- name: SAI2RST
description: SAI2 block reset Set and reset by software.
bit_offset: 23
bit_size: 1
fieldset/APB45PERCKSELR:
description: RCC APB4,5 peripherals kernel clock selection register.
fields:
- name: LPUART1SEL
description: 'LPUART1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.'
bit_offset: 0
bit_size: 3
enum: LPUARTSEL
- name: SPI6SEL
description: 'SPI/I2S6 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.'
bit_offset: 4
bit_size: 3
enum: SPI6SEL
- name: LPTIM23SEL
description: 'LPTIM2 and LPTIM3 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.'
bit_offset: 8
bit_size: 3
enum: LPTIMSEL
- name: LPTIM45SEL
description: 'LPTIM4, and LPTIM5 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.'
bit_offset: 12
bit_size: 3
enum: LPTIMSEL
fieldset/APB4ENR:
description: RCC APB4 clock enable register.
fields:
- name: SYSCFGEN
description: SBS peripheral clock enable Set and reset by software.
bit_offset: 1
bit_size: 1
- name: LPUART1EN
description: LPUART1 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPUART1 are the kernel clock selected by LPUART1SEL and provided to UCLK input, and the pclk4 bus interface clock.
bit_offset: 3
bit_size: 1
- name: SPI6EN
description: SPI/I2S6 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI/I2S6 are the kernel clock selected by SPI6SEL and provided to com_clk input, and the pclk4 bus interface clock.
bit_offset: 5
bit_size: 1
- name: LPTIM2EN
description: LPTIM2 peripheral clocks enable Set and reset by software. The LPTIM2 kernel clock can be selected by LPTIM23SEL.
bit_offset: 9
bit_size: 1
- name: LPTIM3EN
description: LPTIM3 peripheral clocks enable Set and reset by software. The LPTIM3 kernel clock can be selected by LPTIM23SEL.
bit_offset: 10
bit_size: 1
- name: LPTIM4EN
description: LPTIM4 peripheral clocks enable Set and reset by software. The LPTIM4 kernel clock can be selected by LPTIM45SEL.
bit_offset: 11
bit_size: 1
- name: LPTIM5EN
description: LPTIM5 peripheral clocks enable Set and reset by software. The LPTIM5 kernel clock can be selected by LPTIM45SEL.
bit_offset: 12
bit_size: 1
- name: VREFEN
description: VREF peripheral clock enable Set and reset by software.
bit_offset: 15
bit_size: 1
- name: RTCAPBEN
description: RTC APB clock enable Set and reset by software.
bit_offset: 16
bit_size: 1
- name: TMPSENSEN
description: Temperature Sensor peripheral clock enable Set and reset by software.
bit_offset: 26
bit_size: 1
fieldset/APB4LPENR:
description: RCC APB4 low-power clock enable register.
fields:
- name: SYSCFGLPEN
description: SBS peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 1
bit_size: 1
- name: LPUART1LPEN
description: LPUART1 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPUART1 are the kernel clock selected by LPUART1SEL and provided to UCLK input, and the rcc_pclk4 bus interface clock.
bit_offset: 3
bit_size: 1
- name: SPI6LPEN
description: SPI/I2S6 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the SPI/I2S6 are the kernel clock selected by SPI6SEL and provided to com_ck input, and the rcc_pclk4 bus interface clock.
bit_offset: 5
bit_size: 1
- name: LPTIM2LPEN
description: LPTIM2 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPTIM2 are the kernel clock selected by LPTIM23SEL and provided to clk_lpt input, and the pclk4 bus interface clock.
bit_offset: 9
bit_size: 1
- name: LPTIM3LPEN
description: LPTIM3 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPTIM3 are the kernel clock selected by LPTIM23SEL and provided to clk_lpt input, and the pclk4 bus interface clock.
bit_offset: 10
bit_size: 1
- name: LPTIM4LPEN
description: LPTIM4 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPTIM4 are the kernel clock selected by LPTIM45SEL and provided to clk_lpt input, and the pclk4 bus interface clock.
bit_offset: 11
bit_size: 1
- name: LPTIM5LPEN
description: LPTIM5 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPTIM5 are the kernel clock selected by LPTIM45SEL and provided to clk_lpt input, and the pclk4 bus interface clock.
bit_offset: 12
bit_size: 1
- name: VREFLPEN
description: VREF peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 15
bit_size: 1
- name: RTCAPBLPEN
description: RTC APB clock enable in low-power mode Set and reset by software.
bit_offset: 16
bit_size: 1
- name: TMPSENSLPEN
description: temperature sensor peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 26
bit_size: 1
fieldset/APB4RSTR:
description: RCC APB4 peripheral reset register.
fields:
- name: SYSCFGRST
description: SBS block reset Set and reset by software.
bit_offset: 1
bit_size: 1
- name: LPUART1RST
description: LPUART1 block reset Set and reset by software.
bit_offset: 3
bit_size: 1
- name: SPI6RST
description: SPI/I2S6 block reset Set and reset by software.
bit_offset: 5
bit_size: 1
- name: LPTIM2RST
description: LPTIM2 block reset Set and reset by software.
bit_offset: 9
bit_size: 1
- name: LPTIM3RST
description: LPTIM3 block reset Set and reset by software.
bit_offset: 10
bit_size: 1
- name: LPTIM4RST
description: LPTIM4 block reset Set and reset by software.
bit_offset: 11
bit_size: 1
- name: LPTIM5RST
description: LPTIM5 block reset Set and reset by software.
bit_offset: 12
bit_size: 1
- name: VREFRST
description: VREF block reset Set and reset by software.
bit_offset: 15
bit_size: 1
- name: TMPSENSRST
description: TMPSENS block reset Set and reset by software.
bit_offset: 26
bit_size: 1
fieldset/APB5ENR:
description: RCC APB5 clock enable register.
fields:
- name: LTDCEN
description: LTDC peripheral clock enable Provides the pixel clock (ltdc_clk) to the LTDC block. Set and reset by software.
bit_offset: 1
bit_size: 1
- name: DCMIPPEN
description: DCMIPP peripheral clock enable Set and reset by software.
bit_offset: 2
bit_size: 1
- name: GFXTIMEN
description: GFXTIM peripheral clock enable Set and reset by software.
bit_offset: 4
bit_size: 1
fieldset/APB5LPENR:
description: RCC APB5 sleep clock register.
fields:
- name: LTDCLPEN
description: LTDC peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 1
bit_size: 1
- name: DCMIPPLPEN
description: DCMIPP peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 2
bit_size: 1
- name: GFXTIMLPEN
description: GFXTIM peripheral clock enable in low-power mode Set and reset by software.
bit_offset: 4
bit_size: 1
fieldset/APB5RSTR:
description: RCC APB5 peripheral reset register.
fields:
- name: LTDCRST
description: LTDC block reset Set and reset by software.
bit_offset: 1
bit_size: 1
- name: DCMIPPRST
description: DCMIPP block reset Set and reset by software.
bit_offset: 2
bit_size: 1
- name: GFXTIMRST
description: GFXTIM block reset Set and reset by software.
bit_offset: 4
bit_size: 1
fieldset/APBCFGR:
description: RCC APB clocks configuration register.
fields:
- name: PPRE1
description: 'CPU domain APB1 prescaler Set and reset by software to control the division factor of rcc_pclk1. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE1 write. 0xx: rcc_pclk1 = sys_bus_ck (default after reset).'
bit_offset: 0
bit_size: 3
enum: PPRE
- name: PPRE2
description: 'CPU domain APB2 prescaler Set and reset by software to control the division factor of rcc_pclk2. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE2 write. 0xx: rcc_pclk2 = sys_bus_ck (default after reset).'
bit_offset: 4
bit_size: 3
enum: PPRE
- name: PPRE4
description: 'CPU domain APB4 prescaler Set and reset by software to control the division factor of rcc_pclk4. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE4 write. 0xx: rcc_pclk4 = sys_bus_ck (default after reset).'
bit_offset: 8
bit_size: 3
enum: PPRE
- name: PPRE5
description: 'CPU domain APB5 prescaler Set and reset by software to control the division factor of rcc_pclk5. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE5 write. 0xx: rcc_pclk5 = sys_bus_ck (default after reset).'
bit_offset: 12
bit_size: 3
enum: PPRE
fieldset/BDCR:
description: RCC Backup domain control register.
fields:
- name: LSEON
description: LSE oscillator enabled Set and reset by software.
bit_offset: 0
bit_size: 1
- name: LSERDY
description: LSE oscillator ready Set and reset by hardware to indicate when the LSE is stable. This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0.
bit_offset: 1
bit_size: 1
- name: LSEBYP
description: LSE oscillator bypass Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1).
bit_offset: 2
bit_size: 1
- name: LSEDRV
description: LSE oscillator driving capability Set by software to select the driving capability of the LSE oscillator.
bit_offset: 3
bit_size: 2
enum: LSEDRV
- name: LSECSSON
description: LSE clock security system enable Set by software to enable the clock security system on 32 kHz oscillator. LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected. Once enabled, this bit can only be disabled, After a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON. After a back-up domain reset.
bit_offset: 5
bit_size: 1
- name: LSECSSD
description: LSE clock security system failure detection Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator.
bit_offset: 6
bit_size: 1
- name: LSEEXT
description: low-speed external clock type in Bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the LSEON bit, to be used by the device. The LSEEXT bit can be written only if the LSE oscillator is disabled.
bit_offset: 7
bit_size: 1
- name: RTCSEL
description: RTC clock source selection Set by software to select the clock source for the RTC. These bits can be written only one time (except in case of failure detection on LSE). These bits must be written before LSECSSON is enabled. The VSWRST bit can be used to reset them, then it can be written one time again. If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST).
bit_offset: 8
bit_size: 2
enum: RTCSEL
- name: LSECSSRA
description: 'Re-Arm the LSECSS function Set by software. After a LSE failure detection, the software application can re-enable the LSECSS by writing this bit to 1. Reading this bit returns the written value. Prior to set this bit to 1, LSECSSON must be set to 0. Please refer to Section : CSS on LSE for details.'
bit_offset: 12
bit_size: 1
- name: RTCEN
description: RTC clock enable Set and reset by software.
bit_offset: 15
bit_size: 1
- name: VSWRST
description: VSwitch domain software reset Set and reset by software. To generate a VSW reset, it is recommended to write this bit to 1, then back to 0.
bit_offset: 16
bit_size: 1
fieldset/BMCFGR:
description: RCC AHB clock configuration register.
fields:
- name: BMPRE
description: 'Bus matrix clock prescaler Set and reset by software to control the division factor of rcc_hclk[5:1] and rcc_aclk. This group of clocks is also named sys_bus_ck. Changing this division ratio has an impact on the frequency of all bus matrix clocks. 0xxx: sys_bus_ck= sys_cpu_ck (default after reset) Note: The clocks are divided by the new prescaler factor from 1 to 16 periods of the slowest APB clock among rcc_pclk1,2,4,5 after BMPRE update. Note: Note also that frequency of rcc_hclk[5:1] = rcc_aclk = sys_bus_ck.'
bit_offset: 0
bit_size: 4
enum: HPRE
fieldset/CDCFGR:
description: RCC CPU domain clock configuration register.
fields:
- name: CPRE
description: 'CPU domain core prescaler Set and reset by software to control the CPU clock division factor. Changing this division ratio has an impact on the frequency of the CPU clock and all bus matrix clocks. After changing this prescaler value, it takes up to 16 periods of the slowest APB clock before the new division ratio is taken into account. The application can check if the new division factor is taken into account by reading back this register. 0xxx: sys_ck not divided (default after reset).'
bit_offset: 0
bit_size: 4
enum: HPRE
fieldset/CFGR:
description: RCC clock configuration register.
fields:
- name: SW
description: 'system clock switch Set and reset by software to select system clock source (sys_ck). Set by hardware in order to force the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode or in case of failure of the HSE when used directly or indirectly as system clock. others: reserved.'
bit_offset: 0
bit_size: 3
enum: SW
- name: SWS
description: 'system clock switch status Set and reset by hardware to indicate which clock source is used as system clock. others: reserved.'
bit_offset: 3
bit_size: 3
enum: SW
- name: STOPWUCK
description: 'system clock selection after a wake up from system Stop Set and reset by software to select the system wakeup clock from system Stop. The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. See Section 1.: Dividers values can be changed on-the-fly. All dividers provide have 50% duty-cycles. for details. STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10).'
bit_offset: 6
bit_size: 1
enum: STOPWUCK
- name: STOPKERWUCK
description: 'kernel clock selection after a wake up from system Stop Set and reset by software to select the kernel wakeup clock from system Stop. See Section 1.: Dividers values can be changed on-the-fly. All dividers provide have 50% duty-cycles. for details.'
bit_offset: 7
bit_size: 1
enum: STOPKERWUCK
- name: RTCPRE
description: 'HSE division factor for RTC clock Set and cleared by software to divide the HSE to generate a clock for RTC. Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source. ...'
bit_offset: 8
bit_size: 6
- name: TIMPRE
description: 'timers clocks prescaler selection This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains. or 4, else it is equal to 4 x F<sub>rcc_pclkx_d2</sub> Refer to Table 64: Ratio between clock timer and pclk for more details.'
bit_offset: 15
bit_size: 1
enum: TIMPRE
- name: MCO1PRE
description: MCO1 prescaler Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ...
bit_offset: 18
bit_size: 4
enum: MCOPRE
- name: MCO1SEL
description: 'Microcontroller clock output 1 Set and cleared by software. Clock source selection may generate glitches on MCO1. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved.'
bit_offset: 22
bit_size: 3
enum: MCO1SEL
- name: MCO2PRE
description: MCO2 prescaler Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ...
bit_offset: 25
bit_size: 4
enum: MCOPRE
- name: MCO2SEL
description: 'microcontroller clock output 2 Set and cleared by software. Clock source selection may generate glitches on MCO2. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved.'
bit_offset: 29
bit_size: 3
enum: MCO2SEL
fieldset/CICR:
description: RCC clock source interrupt clear register.
fields:
- name: LSIRDYC
description: LSI ready interrupt clear Set by software to clear LSIRDYF. Reset by hardware when clear done.
bit_offset: 0
bit_size: 1
- name: LSERDYC
description: LSE ready interrupt clear Set by software to clear LSERDYF. Reset by hardware when clear done.
bit_offset: 1
bit_size: 1
- name: HSIRDYC
description: HSI ready interrupt clear Set by software to clear HSIRDYF. Reset by hardware when clear done.
bit_offset: 2
bit_size: 1
- name: HSERDYC
description: HSE ready interrupt clear Set by software to clear HSERDYF. Reset by hardware when clear done.
bit_offset: 3
bit_size: 1
- name: CSIRDYC
description: CSI ready interrupt clear Set by software to clear CSIRDYF. Reset by hardware when clear done.
bit_offset: 4
bit_size: 1
- name: HSI48RDYC
description: HSI48 ready interrupt clear Set by software to clear HSI48RDYF. Reset by hardware when clear done.
bit_offset: 5
bit_size: 1
- name: PLLRDYC
description: PLL1 ready interrupt clear Set by software to clear PLL1RDYF. Reset by hardware when clear done.
bit_offset: 6
bit_size: 1
array:
len: 3
stride: 1
- name: LSECSSC
description: LSE clock security system interrupt clear Set by software to clear LSECSSF. Reset by hardware when clear done.
bit_offset: 9
bit_size: 1
- name: HSECSSC
description: HSE clock security system interrupt clear Set by software to clear HSECSSF. Reset by hardware when clear done.
bit_offset: 10
bit_size: 1
fieldset/CIER:
description: RCC clock source interrupt enable register.
fields:
- name: LSIRDYIE
description: LSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization.
bit_offset: 0
bit_size: 1
- name: LSERDYIE
description: LSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization.
bit_offset: 1
bit_size: 1
- name: HSIRDYIE
description: HSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization.
bit_offset: 2
bit_size: 1
- name: HSERDYIE
description: HSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization.
bit_offset: 3
bit_size: 1
- name: CSIRDYIE
description: CSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization.
bit_offset: 4
bit_size: 1
- name: HSI48RDYIE
description: HSI48 ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization.
bit_offset: 5
bit_size: 1
- name: PLLRDYIE
description: PLL1 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL1 lock.
bit_offset: 6
bit_size: 1
array:
len: 3
stride: 1
- name: LSECSSIE
description: LSE clock security system interrupt enable Set and reset by software to enable/disable interrupt caused by the clock security system (CSS) on external 32 kHz oscillator.
bit_offset: 9
bit_size: 1
fieldset/CIFR:
description: RCC clock source interrupt flag register.
fields:
- name: LSIRDYF
description: LSI ready interrupt flag Reset by software by writing LSIRDYC bit. Set by hardware when the LSI clock becomes stable and LSIRDYIE is set.
bit_offset: 0
bit_size: 1
- name: LSERDYF
description: LSE ready interrupt flag Reset by software by writing LSERDYC bit. Set by hardware when the LSE clock becomes stable and LSERDYIE is set.
bit_offset: 1
bit_size: 1
- name: HSIRDYF
description: HSI ready interrupt flag Reset by software by writing HSIRDYC bit. Set by hardware when the HSI clock becomes stable and HSIRDYIE is set.
bit_offset: 2
bit_size: 1
- name: HSERDYF
description: HSE ready interrupt flag Reset by software by writing HSERDYC bit. Set by hardware when the HSE clock becomes stable and HSERDYIE is set.
bit_offset: 3
bit_size: 1
- name: CSIRDYF
description: CSI ready interrupt flag Reset by software by writing CSIRDYC bit. Set by hardware when the CSI clock becomes stable and CSIRDYIE is set.
bit_offset: 4
bit_size: 1
- name: HSI48RDYF
description: HSI48 ready interrupt flag Reset by software by writing HSI48RDYC bit. Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set.
bit_offset: 5
bit_size: 1
- name: PLLRDYF
description: PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set.
bit_offset: 6
bit_size: 1
array:
len: 3
stride: 1
- name: LSECSSF
description: LSE clock security system interrupt flag Reset by software by writing LSECSSC bit. Set by hardware when a failure is detected on the external 32 kHz oscillator and LSECSSIE is set.
bit_offset: 9
bit_size: 1
- name: HSECSSF
description: HSE clock security system interrupt flag Reset by software by writing HSECSSC bit. Set by hardware in case of HSE clock failure.
bit_offset: 10
bit_size: 1
fieldset/CKGDISR:
description: RCC AXI clocks gating disable register.
fields:
- name: AXICKG
description: AXI interconnect matrix clock gating disable This bit is set and reset by software.
bit_offset: 0
bit_size: 1
- name: AHBMCKG
description: AXI master AHB clock gating disable This bit is set and reset by software.
bit_offset: 1
bit_size: 1
- name: SDMMC1CKG
description: AXI master SDMMC1 clock gating disable This bit is set and reset by software.
bit_offset: 2
bit_size: 1
- name: HPDMA1CKG
description: AXI master HPDMA1 clock gating disable This bit is set and reset by software.
bit_offset: 3
bit_size: 1
- name: CPUCKG
description: AXI master CPU clock gating disable This bit is set and reset by software.
bit_offset: 4
bit_size: 1
- name: GPUS0CKG
description: AXI master 0 GPU clock gating disable This bit is set and reset by software.
bit_offset: 5
bit_size: 1
- name: GPUS1CKG
description: AXI master 1 GPU clock gating disable This bit is set and reset by software.
bit_offset: 6
bit_size: 1
- name: GPUCLCKG
description: AXI master cache GPU clock gating disable This bit is set and reset by software.
bit_offset: 7
bit_size: 1
- name: DCMIPPCKG
description: AXI master DCMIPP clock gating disable This bit is set and reset by software.
bit_offset: 8
bit_size: 1
- name: DMA2DCKG
description: AXI master DMA2D clock gating disable This bit is set and reset by software.
bit_offset: 9
bit_size: 1
- name: GFXMMUSCKG
description: AXI matrix slave GFXMMU clock gating disable This bit is set and reset by software.
bit_offset: 10
bit_size: 1
- name: LTDCCKG
description: AXI master LTDC clock gating disable This bit is set and reset by software.
bit_offset: 11
bit_size: 1
- name: GFXMMUMCKG
description: AXI master GFXMMU clock gating disable This bit is set and reset by software.
bit_offset: 12
bit_size: 1
- name: AHBSCKG
description: AXI slave AHB clock gating disable This bit is set and reset by software.
bit_offset: 13
bit_size: 1
- name: FMCCKG
description: AXI slave FMC and MCE3 clock gating disable This bit is set and reset by software.
bit_offset: 14
bit_size: 1
- name: XSPI1CKG
description: AXI slave XSPI1 and MCE1 clock gating disable This bit is set and reset by software.
bit_offset: 15
bit_size: 1
- name: XSPI2CKG
description: AXI slave XSPI2 and MCE2 clock gating disable This bit is set and reset by software.
bit_offset: 16
bit_size: 1
- name: AXIRAM4CKG
description: AXI matrix slave SRAM4 clock gating disable This bit is set and reset by software.
bit_offset: 17
bit_size: 1
- name: AXIRAM3CKG
description: AXI matrix slave SRAM3 clock gating disable This bit is set and reset by software.
bit_offset: 18
bit_size: 1
- name: AXIRAM2CKG
description: AXI slave SRAM2 clock gating disable This bit is set and reset by software.
bit_offset: 19
bit_size: 1
- name: AXIRAM1CKG
description: AXI slave SRAM1 / error code correction (ECC) clock gating disable This bit is set and reset by software.
bit_offset: 20
bit_size: 1
- name: FLITFCKG
description: AXI slave Flash interface (FLIFT) clock gating disable This bit is set and reset by software.
bit_offset: 21
bit_size: 1
- name: EXTICKG
description: EXTI clock gating disable This bit is set and reset by software.
bit_offset: 30
bit_size: 1
- name: JTAGCKG
description: JTAG automatic clock gating disabling This bit is set and reset by software.
bit_offset: 31
bit_size: 1
fieldset/CKPROTR:
description: RCC clock protection register.
fields:
- name: XSPICKP
description: 'XSPI clock protection Set and cleared by software. When set to 1, this bit prevents disabling accidentally the XSPIs. The following fields cannot be modified when this bit is set to 1: PLL2ON, PLL2DIVSEN, PLL2DIVTEN, HSEON, HSION, CSION, XSPIxEN, OCTOSPIxLPEN, OCTOSPIxRST.'
bit_offset: 0
bit_size: 1
- name: FMCCKP
description: 'FMC clock protection Set and cleared by software. When set to 1, this bit prevents disabling accidentally the FMC. The following fields cannot be modified when this bit is set to 1: PLL1ON, PLL2ON, PLL1DIVQEN, PLL2DIVREN, HSEON, HSION, CSION, FMCEN, FMCLPEN, FMCRST.'
bit_offset: 1
bit_size: 1
- name: XSPI1SWP
description: XSPI1 kernel clock switch position Set by hardware. This field can be used to verify the real position of XSPI2 kernel switch selector.
bit_offset: 4
bit_size: 3
enum: XSPISWP
- name: XSPI2SWP
description: XSPI2 kernel clock switch position Set by hardware. This field can be used to verify the real position of XSPI2 kernel switch selector.
bit_offset: 8
bit_size: 3
enum: XSPISWP
- name: FMCSWP
description: FMC kernel clock switch position Set by hardware. This field can be used to verify the real position of FMC kernel switch selector.
bit_offset: 12
bit_size: 3
enum: FMCSWP
fieldset/CR:
description: RCC source control register.
fields:
- name: HSION
description: HSI clock enable Set and cleared by software. Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 0 or STOPKERWUCK = 0. Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source. This bit cannot be cleared if the HSI is used directly (via SW switch) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1) or if FMCCKP = 1, or if XSPICKP = 1.
bit_offset: 0
bit_size: 1
- name: HSIKERON
description: HSI clock enable in Stop mode Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION.
bit_offset: 1
bit_size: 1
- name: HSIRDY
description: HSI clock ready flag Set by hardware to indicate that the HSI oscillator is stable.
bit_offset: 2
bit_size: 1
- name: HSIDIV
description: HSI clock divider Set and reset by software. These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored.
bit_offset: 3
bit_size: 2
enum: HSIDIV
- name: HSIDIVF
description: HSI divider flag Set and reset by hardware. As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV. clock setting is completed).
bit_offset: 5
bit_size: 1
- name: CSION
description: CSI clock enable Set and reset by software to enable/disable CSI clock for system and/or peripheral. Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1. This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1) or if FMCCKP = 1, or if XSPICKP = 1.
bit_offset: 7
bit_size: 1
- name: CSIRDY
description: CSI clock ready flag Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request).
bit_offset: 8
bit_size: 1
- name: CSIKERON
description: CSI clock enable in Stop mode Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION.
bit_offset: 9
bit_size: 1
- name: HSI48ON
description: HSI48 clock enable Set by software and cleared by software or by the hardware when the system enters to Stop or Standby mode.
bit_offset: 12
bit_size: 1
- name: HSI48RDY
description: HSI48 clock ready flag Set by hardware to indicate that the HSI48 oscillator is stable.
bit_offset: 13
bit_size: 1
- name: HSEON
description: HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE when entering Stop or Standby mode. This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1) or if FMCCKP = 1, or if XSPICKP = 1.
bit_offset: 16
bit_size: 1
- name: HSERDY
description: HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable.
bit_offset: 17
bit_size: 1
- name: HSEBYP
description: HSE clock bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled.
bit_offset: 18
bit_size: 1
- name: HSEEXT
description: external high speed clock type in Bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled.
bit_offset: 19
bit_size: 1
enum: HSEEXT
- name: HSECSSON
description: HSE clock security system enable Set by software to enable clock security system on HSE. This bit is set only (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected.
bit_offset: 20
bit_size: 1
- name: PLLON
description: PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock (SW=3) or if FMCCKP = 1, or if XSPICKP = 1.
bit_offset: 24
bit_size: 1
array:
len: 3
stride: 2
- name: PLLRDY
description: PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked.
bit_offset: 25
bit_size: 1
array:
len: 3
stride: 2
fieldset/CRRCR:
description: RCC clock recovery RC register.
fields:
- name: HSI48CAL
description: Internal RC 48 MHz clock calibration Set by hardware by option byte loading. Read-only.
bit_offset: 0
bit_size: 10
fieldset/CSICFGR:
description: RCC CSI calibration register.
fields:
- name: CSICAL
description: CSI clock calibration Set by hardware by option byte loading. Adjusted by software through trimming bits CSITRIM. This field represents the sum of engineering option byte calibration value and CSITRIM bits value.
bit_offset: 0
bit_size: 8
- name: CSITRIM
description: 'CSI clock trimming Set by software to adjust calibration. CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_opt) in order to form the calibration trimming value. CSICAL = CSITRIM + FLASH_CSI_opt. Note: The reset value of the field is 0x20.'
bit_offset: 24
bit_size: 6
fieldset/CSR:
description: RCC clock control and status register.
fields:
- name: LSION
description: LSI oscillator enable Set and reset by software.
bit_offset: 0
bit_size: 1
- name: LSIRDY
description: LSI oscillator ready Set and reset by hardware to indicate when the low-speed internal RC oscillator is stable. This bit needs 3 cycles of lsi_ck clock to fall down after LSION has been set to 0. This bit can be set even when LSION is not enabled if there is a request for LSI clock by the clock security system on LSE or by the low-speed watchdog or by the RTC.
bit_offset: 1
bit_size: 1
fieldset/HSICFGR:
description: RCC HSI calibration register.
fields:
- name: HSICAL
description: HSI clock calibration Set by hardware by option byte loading. Adjusted by software through trimming bits HSITRIM. This field represents the sum of engineering option byte calibration value and HSITRIM bits value.
bit_offset: 0
bit_size: 12
- name: HSITRIM
description: 'HSI clock trimming Set by software to adjust calibration. HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_opt) in order to form the calibration trimming value. HSICAL = HSITRIM + FLASH_HSI_opt. Note: The reset value of the field is 0x40.'
bit_offset: 24
bit_size: 7
fieldset/PLLCFGR:
description: RCC PLLs configuration register.
fields:
- name: PLLFRACEN
description: PLL1 fractional latch enable Set and reset by software to latch the content of FRACN into the sigma-delta modulator. In order to latch the FRACN value into the sigma-delta modulator, PLL1FRACLE must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN into the modulator. Refer to PLL initialization procedure on page 444 for additional information.
bit_offset: 0
bit_size: 1
array:
len: 3
stride: 11
- name: PLLVCOSEL
description: 'PLL1 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1. It allows the application to select the VCO range: VCOH: working from 400 to 1600 MHz (F<sub>ref1_ck</sub> must be between 2 and 16 MHz) VCOL: working from 150 to 420 MHz (F<sub>ref1_ck</sub> must be between 1 and 2 MHz).'
bit_offset: 1
bit_size: 1
array:
len: 3
stride: 11
enum: PLLVCOSEL
- name: PLLSSCGEN
description: PLL1 SSCG enable Set and reset by software to enable the Spread Spectrum Clock Generator of PLL1, in order to reduce the amount of EMI peaks.
bit_offset: 2
bit_size: 1
array:
len: 3
stride: 11
- name: PLLRGE
description: PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1.
bit_offset: 3
bit_size: 2
array:
len: 3
stride: 11
enum: PLLRGE
- name: DIVPEN
description: PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. The hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock (SW=3). In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled.
bit_offset: 5
bit_size: 1
array:
len: 3
stride: 11
- name: DIVQEN
description: PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. The hardware prevents writing this bit if FMCCKP = 1. In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled.
bit_offset: 6
bit_size: 1
array:
len: 3
stride: 11
- name: DIVREN
description: PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, PLL1DIVREN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used.
bit_offset: 7
bit_size: 1
array:
len: 3
stride: 11
- name: DIVSEN
description: PLL1 DIVS divider output enable Set and reset by software to enable the pll1_s_ck output of the PLL1. To save power, PLL1DIVSEN must be set to 0 when the pll1_s_ck is not used.
bit_offset: 8
bit_size: 1
array:
len: 3
stride: 11
- name: DIVTEN
description: PLL1 DIVT divider output enable Set and reset by software to enable the pll1_t_ck output of the PLL1. To save power, PLL1DIVTEN must be set to 0 when the pll1_t_ck is not used.
bit_offset: 9
bit_size: 1
array:
len: 3
stride: 11
fieldset/PLLCKSELR:
description: RCC PLLs clock source selection register.
fields:
- name: PLLSRC
description: DIVMx and PLLs clock source selection Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled. In order to save power, when no PLL is used, PLLSRC must be set to 11.
bit_offset: 0
bit_size: 2
enum: PLLSRC
- name: DIVM
description: prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1). In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0. ... ...
bit_offset: 4
bit_size: 6
array:
len: 3
stride: 8
enum: PLLM
fieldset/PLLDIVR:
description: RCC PLL1 dividers configuration register 1.
fields:
- name: PLLN
description: 'multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = PLL1RDY = 0). ..........: not used ... ... Others: wrong configurations The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 544MHz if PLL1VCOSEL = 0 150 to 420 MHz if PLL1VCOSEL = 1 VCO output frequency = F<sub>ref1_ck</sub> x DIVN1, when fractional value 0 has been loaded into FRACN, with: DIVN1 between 8 and 420 The input frequency F<sub>ref1_ck</sub> must be between 1 and 16 MHz.'
bit_offset: 0
bit_size: 9
enum: PLLN
- name: PLLP
description: PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1DIVPEN = 0. ...
bit_offset: 9
bit_size: 7
enum: PLLDIV
- name: PLLQ
description: PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1DIVQEN = 0. ...
bit_offset: 16
bit_size: 7
enum: PLLDIV
- name: PLLR
description: PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1DIVREN = 0. ...
bit_offset: 24
bit_size: 7
enum: PLLDIV
fieldset/PLLDIVR2:
description: RCC PLL1 dividers configuration register 2.
fields:
- name: PLLS
description: 'PLL1 DIVS division factor Set and reset by software to control the frequency of the pll1_s_ck clock. This post-divider performs divisions with 50% duty-cycle. The duty-cycle of 50% is guaranteed only in the following conditions: With VCOL, if (DIVS+1) is even, With VCOH, for all DIVS values These bits can be written only when the PLL1DIVSEN = 0.'
bit_offset: 0
bit_size: 3
enum: PLLDIVST
- name: PLLT
description: 'PLL1 DIVT division factor Set and reset by software to control the frequency of the pll1_t_ck clock. This post-divider performs divisions with 50% duty-cycle. The duty-cycle of 50% is guaranteed only in the following conditions: With VCOL, if (DIVT+1) is even, With VCOH, for all DIVT values These bits can be written only when the PLL1DIVTEN = 0.'
bit_offset: 8
bit_size: 3
enum: PLLDIVST
fieldset/PLLFRACR:
description: RCC PLL1 fractional divider register.
fields:
- name: FRACN
description: 'fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 544 MHz if PLL1VCOSEL = 0 150 to 420 MHz if PLL1VCOSEL = 1 VCO output frequency = F<sub>ref1_ck</sub> x (DIVN1 + (FRACN / 2<sup>13</sup>)), with DIVN1 between 8 and 420 FRACN can be between 0 and 2<sup>13</sup>- 1 The input frequency F<sub>ref1_ck</sub> must be between 1 and 16 MHz. To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL1FRACLE to 0. Write the new fractional value into FRACN. Set the bit PLL1FRACLE to 1.'
bit_offset: 3
bit_size: 13
fieldset/PLLSSCGR:
description: RCC PLL1 Spread Spectrum Clock Generator register.
fields:
- name: MOD_PER
description: Modulation Period Adjustment for PLL1 Set and reset by software to adjust the modulation period of the clock spreading generator.
bit_offset: 0
bit_size: 13
- name: TPDFN_DIS1
description: Dithering TPDF noise control for PLL1 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a triangular probability density function.
bit_offset: 13
bit_size: 1
- name: RPDFN_DIS1
description: Dithering RPDF noise control for PLL1 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a rectangular probability density function.
bit_offset: 14
bit_size: 1
- name: DWNSPREAD1
description: Spread spectrum clock generator mode for PLL1 Set and reset by software to select the clock spreading mode.
bit_offset: 15
bit_size: 1
enum: DWNSPREAD
- name: INC_STEP
description: Modulation Depth Adjustment for PLL1 Set and reset by software to adjust the modulation depth of the clock spreading generator.
bit_offset: 16
bit_size: 15
fieldset/RSR:
description: RCC Reset status register.
fields:
- name: RMVF
description: remove reset flag Set and reset by software to reset the value of the reset flags.
bit_offset: 16
bit_size: 1
- name: OBLRSTF
description: Option byte loading reset flag <sup>(1)</sup> Reset by software by the RMVF bit. Set by hardware when a reset from the option byte loading occurs.
bit_offset: 17
bit_size: 1
- name: BORRSTF
description: BOR reset flag <sup>(1)</sup> Reset by software by writing the RMVF bit. Set by hardware when a BOR reset occurs (pwr_bor_rst).
bit_offset: 21
bit_size: 1
- name: PINRSTF
description: pin reset flag (NRST) <sup>(1)</sup> Reset by software by writing the RMVF bit. Set by hardware when a reset from pin occurs.
bit_offset: 22
bit_size: 1
- name: PORRSTF
description: POR/PDR reset flag <sup>(1)</sup> Reset by software by writing the RMVF bit. Set by hardware when a POR/PDR reset occurs.
bit_offset: 23
bit_size: 1
- name: SFTRSTF
description: system reset from CPU reset flag <sup>(1)</sup> Reset by software by writing the RMVF bit. Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M7.
bit_offset: 24
bit_size: 1
- name: IWDGRSTF
description: independent watchdog reset flag <sup>(1)</sup> Reset by software by writing the RMVF bit. Set by hardware when an independent watchdog reset occurs.
bit_offset: 26
bit_size: 1
- name: WWDGRSTF
description: window watchdog reset flag <sup>(1)</sup> Reset by software by writing the RMVF bit. Set by hardware when a window watchdog reset occurs.
bit_offset: 28
bit_size: 1
- name: LPWRRSTF
description: reset due to illegal Stop or Standby flag Reset by software by writing the RMVF bit. Set by hardware when the CPU goes erroneously in Stop or Standby mode,.
bit_offset: 30
bit_size: 1
enum/ADCSEL:
bit_size: 2
variants:
- name: PLL2_P
description: pll2_p selected as peripheral clock
value: 0
- name: PLL3_R
description: pll3_r selected as peripheral clock
value: 1
- name: PER
description: PER selected as peripheral clock
value: 2
enum/ADFSEL:
bit_size: 3
variants:
- name: HCLK1
description: hclk1 selected as ADF kernel clock (default after reset).
value: 0
- name: PLL2_P
description: pll2_p_ck selected as ADF kernel clock.
value: 1
enum/CECSEL:
bit_size: 2
variants:
- name: LSE
description: LSE selected as peripheral clock
value: 0
- name: LSI
description: LSI selected as peripheral clock
value: 1
- name: CSI
description: csi_ker selected as peripheral clock
value: 2
enum/DWNSPREAD:
bit_size: 1
variants:
- name: CenterSpread
description: Center-spread modulation selected (default after reset).
value: 0
- name: DownSpread
description: Down-spread modulation selected.
value: 1
enum/ETHPHY_CLK_SEL:
bit_size: 1
variants:
- name: HSE
description: hse_ker_ck selected as clock source (default after reset).
value: 0
- name: PLL3_S
description: pll3_s_ck selected clock source.
value: 1
enum/ETH_REF_CLK_SEL:
bit_size: 2
variants:
- name: ETH_RMII_REF
description: PAD ETH_RMII_REF_CLK selected as kernel peripheral clock (default after reset).
value: 0
- name: HSE
description: hse_ker_ck selected as kernel peripheral clock.
value: 1
- name: ETH
description: eth_clk_fb selected as kernel peripheral clock.
value: 2
enum/FDCANSEL:
bit_size: 2
variants:
- name: HSE
description: HSE selected as peripheral clock
value: 0
- name: PLL1_Q
description: pll1_q selected as peripheral clock
value: 1
- name: PLL2_P
description: pll2_p selected as peripheral clock
value: 2
enum/FMCSEL:
bit_size: 2
variants:
- name: HCLK5
description: hclk5 selected as kernel peripheral clock (default after reset).
value: 0
- name: PLL1_Q
description: pll1_q_ck selected as kernel peripheral clock.
value: 1
- name: PLL2_R
description: pll2_r_ck selected as kernel peripheral clock.
value: 2
- name: HSI
description: hsi_ker_ck selected as kernel peripheral clock.
value: 3
enum/FMCSWP:
bit_size: 3
variants:
- name: B_0x0
description: The switch is in neutral mode and output clock is gated (default after reset).
value: 0
- name: B_0x1
description: The switch is selecting hclk5.
value: 1
- name: B_0x2
description: The switch is selecting pll1_q_ck.
value: 2
- name: B_0x3
description: The switch is selecting pll2_r_ck.
value: 3
- name: B_0x4
description: The switch is selecting hsi_ker_ck.
value: 4
- name: B_0x5
description: The switch is in recovery position (hclk5/4).
value: 5
enum/HPRE:
bit_size: 4
variants:
- name: Div1
value: 0
- name: Div2
value: 8
- name: Div4
value: 9
- name: Div8
value: 10
- name: Div16
value: 11
- name: Div64
value: 12
- name: Div128
value: 13
- name: Div256
value: 14
- name: Div512
value: 15
enum/HSEEXT:
bit_size: 1
variants:
- name: Analog
description: HSE in analog mode (default after reset)
value: 0
- name: Digital
description: HSE in digital mode
value: 1
enum/HSIDIV:
bit_size: 2
variants:
- name: Div1
description: division by 1, hsi(_ker)_ck = 64 MHz (default after reset).
value: 0
- name: Div2
description: division by 2, hsi(_ker)_ck = 32 MHz.
value: 1
- name: Div4
description: division by 4, hsi(_ker)_ck = 16 MHz.
value: 2
- name: Div8
description: division by 8, hsi(_ker)_ck = 8 MHz.
value: 3
enum/I2C1_I3C1SEL:
bit_size: 2
variants:
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL3_R
description: pll3_r selected as peripheral clock
value: 1
- name: HSI
description: hsi_ker selected as peripheral clock
value: 2
- name: CSI
description: csi_ker selected as peripheral clock
value: 3
enum/I2CSEL:
bit_size: 2
variants:
- name: PCLK1
description: pclk1 selected as kernel clock (default after reset).
value: 0
- name: PLL3_R
description: pll3_r selected as peripheral clock
value: 1
- name: HSI
description: hsi_ker selected as peripheral clock
value: 2
- name: CSI
description: csi_ker selected as peripheral clock
value: 3
enum/LPTIM1SEL:
bit_size: 3
variants:
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL2_P
description: pll2_p selected as peripheral clock
value: 1
- name: PLL3_R
description: pll3_r selected as peripheral clock
value: 2
- name: LSE
description: LSE selected as peripheral clock
value: 3
- name: LSI
description: LSI selected as peripheral clock
value: 4
- name: PER
description: PER selected as peripheral clock
value: 5
enum/LPTIMSEL:
bit_size: 3
variants:
- name: PCLK4
description: rcc_pclk4 selected as peripheral clock
value: 0
- name: PLL2_P
description: pll2_p selected as peripheral clock
value: 1
- name: PLL3_R
description: pll3_r selected as peripheral clock
value: 2
- name: LSE
description: LSE selected as peripheral clock
value: 3
- name: LSI
description: LSI selected as peripheral clock
value: 4
- name: PER
description: PER selected as peripheral clock
value: 5
enum/LPUARTSEL:
bit_size: 3
variants:
- name: PCLK4
description: rcc_pclk_d4 selected as peripheral clock
value: 0
- name: PLL2_Q
description: pll2_q selected as peripheral clock
value: 1
- name: PLL3_Q
description: pll3_q selected as peripheral clock
value: 2
- name: HSI
description: hsi_ker selected as peripheral clock
value: 3
- name: CSI
description: csi_ker selected as peripheral clock
value: 4
- name: LSE
description: LSE selected as peripheral clock
value: 5
enum/LSEDRV:
bit_size: 2
variants:
- name: Low
description: Low driving capability
value: 0
- name: MediumLow
description: Medium low driving capability
value: 1
- name: MediumHigh
description: Medium high driving capability
value: 2
- name: High
description: High driving capability
value: 3
enum/MCO1SEL:
bit_size: 3
variants:
- name: HSI
description: HSI selected for micro-controller clock output
value: 0
- name: LSE
description: LSE selected for micro-controller clock output
value: 1
- name: HSE
description: HSE selected for micro-controller clock output
value: 2
- name: PLL1_Q
description: pll1_q selected for micro-controller clock output
value: 3
- name: HSI48
description: HSI48 selected for micro-controller clock output
value: 4
enum/MCO2SEL:
bit_size: 3
variants:
- name: SYS
description: System clock selected for micro-controller clock output
value: 0
- name: PLL2_P
description: pll2_p selected for micro-controller clock output
value: 1
- name: HSE
description: HSE selected for micro-controller clock output
value: 2
- name: PLL1_P
description: pll1_p selected for micro-controller clock output
value: 3
- name: CSI
description: CSI selected for micro-controller clock output
value: 4
- name: LSI
description: LSI selected for micro-controller clock output
value: 5
enum/MCOPRE:
bit_size: 4
variants:
- name: Div1
description: Divide by 1
value: 1
- name: Div2
description: Divide by 2
value: 2
- name: Div3
description: Divide by 3
value: 3
- name: Div4
description: Divide by 4
value: 4
- name: Div5
description: Divide by 5
value: 5
- name: Div6
description: Divide by 6
value: 6
- name: Div7
description: Divide by 7
value: 7
- name: Div8
description: Divide by 8
value: 8
- name: Div9
description: Divide by 9
value: 9
- name: Div10
description: Divide by 10
value: 10
- name: Div11
description: Divide by 11
value: 11
- name: Div12
description: Divide by 12
value: 12
- name: Div13
description: Divide by 13
value: 13
- name: Div14
description: Divide by 14
value: 14
- name: Div15
description: Divide by 15
value: 15
enum/OCTOSPISEL:
bit_size: 2
variants:
- name: HCLK5
description: hclk5 selected as kernel peripheral clock (default after reset).
value: 0
- name: PLL2_S
description: pll2_s_ck selected as kernel peripheral clock.
value: 1
enum/PERSEL:
bit_size: 2
variants:
- name: HSI
description: HSI selected as peripheral clock
value: 0
- name: CSI
description: CSI selected as peripheral clock
value: 1
- name: HSE
description: HSE selected as peripheral clock
value: 2
enum/PLLDIV:
bit_size: 7
variants:
- name: Div1
value: 0
- name: Div2
value: 1
- name: Div3
value: 2
- name: Div4
value: 3
- name: Div5
value: 4
- name: Div6
value: 5
- name: Div7
value: 6
- name: Div8
value: 7
- name: Div9
value: 8
- name: Div10
value: 9
- name: Div11
value: 10
- name: Div12
value: 11
- name: Div13
value: 12
- name: Div14
value: 13
- name: Div15
value: 14
- name: Div16
value: 15
- name: Div17
value: 16
- name: Div18
value: 17
- name: Div19
value: 18
- name: Div20
value: 19
- name: Div21
value: 20
- name: Div22
value: 21
- name: Div23
value: 22
- name: Div24
value: 23
- name: Div25
value: 24
- name: Div26
value: 25
- name: Div27
value: 26
- name: Div28
value: 27
- name: Div29
value: 28
- name: Div30
value: 29
- name: Div31
value: 30
- name: Div32
value: 31
- name: Div33
value: 32
- name: Div34
value: 33
- name: Div35
value: 34
- name: Div36
value: 35
- name: Div37
value: 36
- name: Div38
value: 37
- name: Div39
value: 38
- name: Div40
value: 39
- name: Div41
value: 40
- name: Div42
value: 41
- name: Div43
value: 42
- name: Div44
value: 43
- name: Div45
value: 44
- name: Div46
value: 45
- name: Div47
value: 46
- name: Div48
value: 47
- name: Div49
value: 48
- name: Div50
value: 49
- name: Div51
value: 50
- name: Div52
value: 51
- name: Div53
value: 52
- name: Div54
value: 53
- name: Div55
value: 54
- name: Div56
value: 55
- name: Div57
value: 56
- name: Div58
value: 57
- name: Div59
value: 58
- name: Div60
value: 59
- name: Div61
value: 60
- name: Div62
value: 61
- name: Div63
value: 62
- name: Div64
value: 63
- name: Div65
value: 64
- name: Div66
value: 65
- name: Div67
value: 66
- name: Div68
value: 67
- name: Div69
value: 68
- name: Div70
value: 69
- name: Div71
value: 70
- name: Div72
value: 71
- name: Div73
value: 72
- name: Div74
value: 73
- name: Div75
value: 74
- name: Div76
value: 75
- name: Div77
value: 76
- name: Div78
value: 77
- name: Div79
value: 78
- name: Div80
value: 79
- name: Div81
value: 80
- name: Div82
value: 81
- name: Div83
value: 82
- name: Div84
value: 83
- name: Div85
value: 84
- name: Div86
value: 85
- name: Div87
value: 86
- name: Div88
value: 87
- name: Div89
value: 88
- name: Div90
value: 89
- name: Div91
value: 90
- name: Div92
value: 91
- name: Div93
value: 92
- name: Div94
value: 93
- name: Div95
value: 94
- name: Div96
value: 95
- name: Div97
value: 96
- name: Div98
value: 97
- name: Div99
value: 98
- name: Div100
value: 99
- name: Div101
value: 100
- name: Div102
value: 101
- name: Div103
value: 102
- name: Div104
value: 103
- name: Div105
value: 104
- name: Div106
value: 105
- name: Div107
value: 106
- name: Div108
value: 107
- name: Div109
value: 108
- name: Div110
value: 109
- name: Div111
value: 110
- name: Div112
value: 111
- name: Div113
value: 112
- name: Div114
value: 113
- name: Div115
value: 114
- name: Div116
value: 115
- name: Div117
value: 116
- name: Div118
value: 117
- name: Div119
value: 118
- name: Div120
value: 119
- name: Div121
value: 120
- name: Div122
value: 121
- name: Div123
value: 122
- name: Div124
value: 123
- name: Div125
value: 124
- name: Div126
value: 125
- name: Div127
value: 126
- name: Div128
value: 127
enum/PLLDIVST:
bit_size: 3
variants:
- name: Div1
value: 0
- name: Div2
value: 1
- name: Div3
value: 2
- name: Div4
value: 3
- name: Div5
value: 4
- name: Div6
value: 5
- name: Div7
value: 6
- name: Div8
value: 7
enum/PLLM:
bit_size: 6
variants:
- name: Div1
value: 1
- name: Div2
value: 2
- name: Div3
value: 3
- name: Div4
value: 4
- name: Div5
value: 5
- name: Div6
value: 6
- name: Div7
value: 7
- name: Div8
value: 8
- name: Div9
value: 9
- name: Div10
value: 10
- name: Div11
value: 11
- name: Div12
value: 12
- name: Div13
value: 13
- name: Div14
value: 14
- name: Div15
value: 15
- name: Div16
value: 16
- name: Div17
value: 17
- name: Div18
value: 18
- name: Div19
value: 19
- name: Div20
value: 20
- name: Div21
value: 21
- name: Div22
value: 22
- name: Div23
value: 23
- name: Div24
value: 24
- name: Div25
value: 25
- name: Div26
value: 26
- name: Div27
value: 27
- name: Div28
value: 28
- name: Div29
value: 29
- name: Div30
value: 30
- name: Div31
value: 31
- name: Div32
value: 32
- name: Div33
value: 33
- name: Div34
value: 34
- name: Div35
value: 35
- name: Div36
value: 36
- name: Div37
value: 37
- name: Div38
value: 38
- name: Div39
value: 39
- name: Div40
value: 40
- name: Div41
value: 41
- name: Div42
value: 42
- name: Div43
value: 43
- name: Div44
value: 44
- name: Div45
value: 45
- name: Div46
value: 46
- name: Div47
value: 47
- name: Div48
value: 48
- name: Div49
value: 49
- name: Div50
value: 50
- name: Div51
value: 51
- name: Div52
value: 52
- name: Div53
value: 53
- name: Div54
value: 54
- name: Div55
value: 55
- name: Div56
value: 56
- name: Div57
value: 57
- name: Div58
value: 58
- name: Div59
value: 59
- name: Div60
value: 60
- name: Div61
value: 61
- name: Div62
value: 62
- name: Div63
value: 63
enum/PLLN:
bit_size: 9
variants:
- name: Mul8
value: 7
- name: Mul9
value: 8
- name: Mul10
value: 9
- name: Mul11
value: 10
- name: Mul12
value: 11
- name: Mul13
value: 12
- name: Mul14
value: 13
- name: Mul15
value: 14
- name: Mul16
value: 15
- name: Mul17
value: 16
- name: Mul18
value: 17
- name: Mul19
value: 18
- name: Mul20
value: 19
- name: Mul21
value: 20
- name: Mul22
value: 21
- name: Mul23
value: 22
- name: Mul24
value: 23
- name: Mul25
value: 24
- name: Mul26
value: 25
- name: Mul27
value: 26
- name: Mul28
value: 27
- name: Mul29
value: 28
- name: Mul30
value: 29
- name: Mul31
value: 30
- name: Mul32
value: 31
- name: Mul33
value: 32
- name: Mul34
value: 33
- name: Mul35
value: 34
- name: Mul36
value: 35
- name: Mul37
value: 36
- name: Mul38
value: 37
- name: Mul39
value: 38
- name: Mul40
value: 39
- name: Mul41
value: 40
- name: Mul42
value: 41
- name: Mul43
value: 42
- name: Mul44
value: 43
- name: Mul45
value: 44
- name: Mul46
value: 45
- name: Mul47
value: 46
- name: Mul48
value: 47
- name: Mul49
value: 48
- name: Mul50
value: 49
- name: Mul51
value: 50
- name: Mul52
value: 51
- name: Mul53
value: 52
- name: Mul54
value: 53
- name: Mul55
value: 54
- name: Mul56
value: 55
- name: Mul57
value: 56
- name: Mul58
value: 57
- name: Mul59
value: 58
- name: Mul60
value: 59
- name: Mul61
value: 60
- name: Mul62
value: 61
- name: Mul63
value: 62
- name: Mul64
value: 63
- name: Mul65
value: 64
- name: Mul66
value: 65
- name: Mul67
value: 66
- name: Mul68
value: 67
- name: Mul69
value: 68
- name: Mul70
value: 69
- name: Mul71
value: 70
- name: Mul72
value: 71
- name: Mul73
value: 72
- name: Mul74
value: 73
- name: Mul75
value: 74
- name: Mul76
value: 75
- name: Mul77
value: 76
- name: Mul78
value: 77
- name: Mul79
value: 78
- name: Mul80
value: 79
- name: Mul81
value: 80
- name: Mul82
value: 81
- name: Mul83
value: 82
- name: Mul84
value: 83
- name: Mul85
value: 84
- name: Mul86
value: 85
- name: Mul87
value: 86
- name: Mul88
value: 87
- name: Mul89
value: 88
- name: Mul90
value: 89
- name: Mul91
value: 90
- name: Mul92
value: 91
- name: Mul93
value: 92
- name: Mul94
value: 93
- name: Mul95
value: 94
- name: Mul96
value: 95
- name: Mul97
value: 96
- name: Mul98
value: 97
- name: Mul99
value: 98
- name: Mul100
value: 99
- name: Mul101
value: 100
- name: Mul102
value: 101
- name: Mul103
value: 102
- name: Mul104
value: 103
- name: Mul105
value: 104
- name: Mul106
value: 105
- name: Mul107
value: 106
- name: Mul108
value: 107
- name: Mul109
value: 108
- name: Mul110
value: 109
- name: Mul111
value: 110
- name: Mul112
value: 111
- name: Mul113
value: 112
- name: Mul114
value: 113
- name: Mul115
value: 114
- name: Mul116
value: 115
- name: Mul117
value: 116
- name: Mul118
value: 117
- name: Mul119
value: 118
- name: Mul120
value: 119
- name: Mul121
value: 120
- name: Mul122
value: 121
- name: Mul123
value: 122
- name: Mul124
value: 123
- name: Mul125
value: 124
- name: Mul126
value: 125
- name: Mul127
value: 126
- name: Mul128
value: 127
- name: Mul129
value: 128
- name: Mul130
value: 129
- name: Mul131
value: 130
- name: Mul132
value: 131
- name: Mul133
value: 132
- name: Mul134
value: 133
- name: Mul135
value: 134
- name: Mul136
value: 135
- name: Mul137
value: 136
- name: Mul138
value: 137
- name: Mul139
value: 138
- name: Mul140
value: 139
- name: Mul141
value: 140
- name: Mul142
value: 141
- name: Mul143
value: 142
- name: Mul144
value: 143
- name: Mul145
value: 144
- name: Mul146
value: 145
- name: Mul147
value: 146
- name: Mul148
value: 147
- name: Mul149
value: 148
- name: Mul150
value: 149
- name: Mul151
value: 150
- name: Mul152
value: 151
- name: Mul153
value: 152
- name: Mul154
value: 153
- name: Mul155
value: 154
- name: Mul156
value: 155
- name: Mul157
value: 156
- name: Mul158
value: 157
- name: Mul159
value: 158
- name: Mul160
value: 159
- name: Mul161
value: 160
- name: Mul162
value: 161
- name: Mul163
value: 162
- name: Mul164
value: 163
- name: Mul165
value: 164
- name: Mul166
value: 165
- name: Mul167
value: 166
- name: Mul168
value: 167
- name: Mul169
value: 168
- name: Mul170
value: 169
- name: Mul171
value: 170
- name: Mul172
value: 171
- name: Mul173
value: 172
- name: Mul174
value: 173
- name: Mul175
value: 174
- name: Mul176
value: 175
- name: Mul177
value: 176
- name: Mul178
value: 177
- name: Mul179
value: 178
- name: Mul180
value: 179
- name: Mul181
value: 180
- name: Mul182
value: 181
- name: Mul183
value: 182
- name: Mul184
value: 183
- name: Mul185
value: 184
- name: Mul186
value: 185
- name: Mul187
value: 186
- name: Mul188
value: 187
- name: Mul189
value: 188
- name: Mul190
value: 189
- name: Mul191
value: 190
- name: Mul192
value: 191
- name: Mul193
value: 192
- name: Mul194
value: 193
- name: Mul195
value: 194
- name: Mul196
value: 195
- name: Mul197
value: 196
- name: Mul198
value: 197
- name: Mul199
value: 198
- name: Mul200
value: 199
- name: Mul201
value: 200
- name: Mul202
value: 201
- name: Mul203
value: 202
- name: Mul204
value: 203
- name: Mul205
value: 204
- name: Mul206
value: 205
- name: Mul207
value: 206
- name: Mul208
value: 207
- name: Mul209
value: 208
- name: Mul210
value: 209
- name: Mul211
value: 210
- name: Mul212
value: 211
- name: Mul213
value: 212
- name: Mul214
value: 213
- name: Mul215
value: 214
- name: Mul216
value: 215
- name: Mul217
value: 216
- name: Mul218
value: 217
- name: Mul219
value: 218
- name: Mul220
value: 219
- name: Mul221
value: 220
- name: Mul222
value: 221
- name: Mul223
value: 222
- name: Mul224
value: 223
- name: Mul225
value: 224
- name: Mul226
value: 225
- name: Mul227
value: 226
- name: Mul228
value: 227
- name: Mul229
value: 228
- name: Mul230
value: 229
- name: Mul231
value: 230
- name: Mul232
value: 231
- name: Mul233
value: 232
- name: Mul234
value: 233
- name: Mul235
value: 234
- name: Mul236
value: 235
- name: Mul237
value: 236
- name: Mul238
value: 237
- name: Mul239
value: 238
- name: Mul240
value: 239
- name: Mul241
value: 240
- name: Mul242
value: 241
- name: Mul243
value: 242
- name: Mul244
value: 243
- name: Mul245
value: 244
- name: Mul246
value: 245
- name: Mul247
value: 246
- name: Mul248
value: 247
- name: Mul249
value: 248
- name: Mul250
value: 249
- name: Mul251
value: 250
- name: Mul252
value: 251
- name: Mul253
value: 252
- name: Mul254
value: 253
- name: Mul255
value: 254
- name: Mul256
value: 255
- name: Mul257
value: 256
- name: Mul258
value: 257
- name: Mul259
value: 258
- name: Mul260
value: 259
- name: Mul261
value: 260
- name: Mul262
value: 261
- name: Mul263
value: 262
- name: Mul264
value: 263
- name: Mul265
value: 264
- name: Mul266
value: 265
- name: Mul267
value: 266
- name: Mul268
value: 267
- name: Mul269
value: 268
- name: Mul270
value: 269
- name: Mul271
value: 270
- name: Mul272
value: 271
- name: Mul273
value: 272
- name: Mul274
value: 273
- name: Mul275
value: 274
- name: Mul276
value: 275
- name: Mul277
value: 276
- name: Mul278
value: 277
- name: Mul279
value: 278
- name: Mul280
value: 279
- name: Mul281
value: 280
- name: Mul282
value: 281
- name: Mul283
value: 282
- name: Mul284
value: 283
- name: Mul285
value: 284
- name: Mul286
value: 285
- name: Mul287
value: 286
- name: Mul288
value: 287
- name: Mul289
value: 288
- name: Mul290
value: 289
- name: Mul291
value: 290
- name: Mul292
value: 291
- name: Mul293
value: 292
- name: Mul294
value: 293
- name: Mul295
value: 294
- name: Mul296
value: 295
- name: Mul297
value: 296
- name: Mul298
value: 297
- name: Mul299
value: 298
- name: Mul300
value: 299
- name: Mul301
value: 300
- name: Mul302
value: 301
- name: Mul303
value: 302
- name: Mul304
value: 303
- name: Mul305
value: 304
- name: Mul306
value: 305
- name: Mul307
value: 306
- name: Mul308
value: 307
- name: Mul309
value: 308
- name: Mul310
value: 309
- name: Mul311
value: 310
- name: Mul312
value: 311
- name: Mul313
value: 312
- name: Mul314
value: 313
- name: Mul315
value: 314
- name: Mul316
value: 315
- name: Mul317
value: 316
- name: Mul318
value: 317
- name: Mul319
value: 318
- name: Mul320
value: 319
- name: Mul321
value: 320
- name: Mul322
value: 321
- name: Mul323
value: 322
- name: Mul324
value: 323
- name: Mul325
value: 324
- name: Mul326
value: 325
- name: Mul327
value: 326
- name: Mul328
value: 327
- name: Mul329
value: 328
- name: Mul330
value: 329
- name: Mul331
value: 330
- name: Mul332
value: 331
- name: Mul333
value: 332
- name: Mul334
value: 333
- name: Mul335
value: 334
- name: Mul336
value: 335
- name: Mul337
value: 336
- name: Mul338
value: 337
- name: Mul339
value: 338
- name: Mul340
value: 339
- name: Mul341
value: 340
- name: Mul342
value: 341
- name: Mul343
value: 342
- name: Mul344
value: 343
- name: Mul345
value: 344
- name: Mul346
value: 345
- name: Mul347
value: 346
- name: Mul348
value: 347
- name: Mul349
value: 348
- name: Mul350
value: 349
- name: Mul351
value: 350
- name: Mul352
value: 351
- name: Mul353
value: 352
- name: Mul354
value: 353
- name: Mul355
value: 354
- name: Mul356
value: 355
- name: Mul357
value: 356
- name: Mul358
value: 357
- name: Mul359
value: 358
- name: Mul360
value: 359
- name: Mul361
value: 360
- name: Mul362
value: 361
- name: Mul363
value: 362
- name: Mul364
value: 363
- name: Mul365
value: 364
- name: Mul366
value: 365
- name: Mul367
value: 366
- name: Mul368
value: 367
- name: Mul369
value: 368
- name: Mul370
value: 369
- name: Mul371
value: 370
- name: Mul372
value: 371
- name: Mul373
value: 372
- name: Mul374
value: 373
- name: Mul375
value: 374
- name: Mul376
value: 375
- name: Mul377
value: 376
- name: Mul378
value: 377
- name: Mul379
value: 378
- name: Mul380
value: 379
- name: Mul381
value: 380
- name: Mul382
value: 381
- name: Mul383
value: 382
- name: Mul384
value: 383
- name: Mul385
value: 384
- name: Mul386
value: 385
- name: Mul387
value: 386
- name: Mul388
value: 387
- name: Mul389
value: 388
- name: Mul390
value: 389
- name: Mul391
value: 390
- name: Mul392
value: 391
- name: Mul393
value: 392
- name: Mul394
value: 393
- name: Mul395
value: 394
- name: Mul396
value: 395
- name: Mul397
value: 396
- name: Mul398
value: 397
- name: Mul399
value: 398
- name: Mul400
value: 399
- name: Mul401
value: 400
- name: Mul402
value: 401
- name: Mul403
value: 402
- name: Mul404
value: 403
- name: Mul405
value: 404
- name: Mul406
value: 405
- name: Mul407
value: 406
- name: Mul408
value: 407
- name: Mul409
value: 408
- name: Mul410
value: 409
- name: Mul411
value: 410
- name: Mul412
value: 411
- name: Mul413
value: 412
- name: Mul414
value: 413
- name: Mul415
value: 414
- name: Mul416
value: 415
- name: Mul417
value: 416
- name: Mul418
value: 417
- name: Mul419
value: 418
- name: Mul420
value: 419
enum/PLLRGE:
bit_size: 2
variants:
- name: Range1
description: Frequency is between 1 and 2 MHz
value: 0
- name: Range2
description: Frequency is between 2 and 4 MHz
value: 1
- name: Range4
description: Frequency is between 4 and 8 MHz
value: 2
- name: Range8
description: Frequency is between 8 and 16 MHz
value: 3
enum/PLLSRC:
bit_size: 2
variants:
- name: HSI
description: HSI selected as PLL clock
value: 0
- name: CSI
description: CSI selected as PLL clock
value: 1
- name: HSE
description: HSE selected as PLL clock
value: 2
- name: DISABLE
description: No clock sent to DIVMx dividers and PLLs
value: 3
enum/PLLVCOSEL:
bit_size: 1
variants:
- name: WideVCO
description: VCOH selected (default after reset).
value: 0
- name: MediumVCO
description: VCOL selected.
value: 1
enum/PPRE:
bit_size: 3
variants:
- name: Div1
description: rcc_hclk not divided
value: 0
- name: Div2
description: rcc_hclk divided by 2
value: 4
- name: Div4
description: rcc_hclk divided by 4
value: 5
- name: Div8
description: rcc_hclk divided by 8
value: 6
- name: Div16
description: rcc_hclk divided by 16
value: 7
enum/PSSISEL:
bit_size: 1
variants:
- name: PLL3_R
description: pll3_r_ck selected as kernel peripheral clock (default after reset).
value: 0
- name: PER
description: per_ck selected as kernel peripheral clock.
value: 1
enum/RTCSEL:
bit_size: 2
variants:
- name: DISABLE
description: No clock
value: 0
- name: LSE
description: LSE oscillator clock used as RTC clock
value: 1
- name: LSI
description: LSI oscillator clock used as RTC clock
value: 2
- name: HSE
description: HSE oscillator clock divided by a prescaler used as RTC clock
value: 3
enum/SAI1SEL:
bit_size: 3
variants:
- name: PLL1_Q
description: pll1_q selected as peripheral clock
value: 0
- name: PLL2_P
description: pll2_p selected as peripheral clock
value: 1
- name: PLL3_P
description: pll3_p selected as peripheral clock
value: 2
- name: I2S_CKIN
description: I2S_CKIN selected as peripheral clock
value: 3
- name: PER
description: PER selected as peripheral clock
value: 4
enum/SAI2SEL:
bit_size: 3
variants:
- name: PLL1_Q
description: pll1_q selected as peripheral clock
value: 0
- name: PLL2_P
description: pll2_p selected as peripheral clock
value: 1
- name: PLL3_P
description: pll3_p selected as peripheral clock
value: 2
- name: I2S_CKIN
description: I2S_CKIN selected as peripheral clock
value: 3
- name: PER
description: PER selected as peripheral clock
value: 4
- name: SPDIFRX_SYMB
description: spdifrx_symb_ck selected as SAI2 kernel clock.
value: 5
enum/SDMMCSEL:
bit_size: 1
variants:
- name: PLL2_S
description: pll2_s_ck selected as kernel peripheral clock (default after reset).
value: 0
- name: PLL2_T
description: pll2_t_ck selected as kernel peripheral clock.
value: 1
enum/SPDIFRXSEL:
bit_size: 2
variants:
- name: PLL1_Q
description: pll1_q selected as peripheral clock
value: 0
- name: PLL2_R
description: pll2_r selected as peripheral clock
value: 1
- name: PLL3_R
description: pll3_r selected as peripheral clock
value: 2
- name: HSI
description: hsi_ker selected as peripheral clock
value: 3
enum/SPI123SEL:
bit_size: 3
variants:
- name: PLL1_Q
description: pll1_q_ck selected as SPI/I2S1 and 7 kernel clock (default after reset).
value: 0
- name: PLL2_P
description: pll2_p_ck selected as SPI/I2S1 and 7 kernel clock.
value: 1
- name: PLL3_P
description: pll3_p_ck selected as SPI/I2S1 and 7 kernel clock.
value: 2
- name: I2S_CKIN
description: I2S_CKIN selected as SPI/I2S1 and 7 kernel clock.
value: 3
- name: PER
description: per_ck selected as SPI/I2S1,and 7 kernel clock.
value: 4
enum/SPI45SEL:
bit_size: 3
variants:
- name: HCLK2
description: APB2 clock selected as peripheral clock
value: 0
- name: PLL2_Q
description: pll2_q selected as peripheral clock
value: 1
- name: PLL3_Q
description: pll3_q selected as peripheral clock
value: 2
- name: HSI
description: hsi_ker selected as peripheral clock
value: 3
- name: CSI
description: csi_ker selected as peripheral clock
value: 4
- name: HSE
description: HSE selected as peripheral clock
value: 5
enum/SPI6SEL:
bit_size: 3
variants:
- name: PCLK4
description: rcc_pclk4 selected as peripheral clock
value: 0
- name: PLL2_Q
description: pll2_q selected as peripheral clock
value: 1
- name: PLL3_Q
description: pll3_q selected as peripheral clock
value: 2
- name: HSI
description: hsi_ker selected as peripheral clock
value: 3
- name: CSI
description: csi_ker selected as peripheral clock
value: 4
- name: HSE
description: HSE selected as peripheral clock
value: 5
enum/STOPKERWUCK:
bit_size: 1
variants:
- name: HSI
description: HSI selected as wake up clock from system Stop (default after reset).
value: 0
- name: CSI
description: CSI selected as wake up clock from system Stop.
value: 1
enum/STOPWUCK:
bit_size: 1
variants:
- name: HSI
description: HSI selected as wake up clock from system Stop
value: 0
- name: CSI
description: CSI selected as wake up clock from system Stop
value: 1
enum/SW:
bit_size: 3
variants:
- name: HSI
description: HSI selected as system clock
value: 0
- name: CSI
description: CSI selected as system clock
value: 1
- name: HSE
description: HSE selected as system clock
value: 2
- name: PLL1_P
description: PLL1 selected as system clock
value: 3
enum/TIMPRE:
bit_size: 1
variants:
- name: DefaultX2
description: Timer kernel clock equal to 2x pclk by default
value: 0
- name: DefaultX4
description: Timer kernel clock equal to 4x pclk by default
value: 1
enum/USART1SEL:
bit_size: 3
variants:
- name: PCLK2
description: rcc_pclk2 selected as peripheral clock
value: 0
- name: PLL2_Q
description: pll2_q selected as peripheral clock
value: 1
- name: PLL3_Q
description: pll3_q selected as peripheral clock
value: 2
- name: HSI
description: hsi_ker selected as peripheral clock
value: 3
- name: CSI
description: csi_ker selected as peripheral clock
value: 4
- name: LSE
description: LSE selected as peripheral clock
value: 5
enum/USART234578SEL:
bit_size: 3
variants:
- name: PCLK1
description: rcc_pclk1 selected as peripheral clock
value: 0
- name: PLL2_Q
description: pll2_q selected as peripheral clock
value: 1
- name: PLL3_Q
description: pll3_q selected as peripheral clock
value: 2
- name: HSI
description: hsi_ker selected as peripheral clock
value: 3
- name: CSI
description: csi_ker selected as peripheral clock
value: 4
- name: LSE
description: LSE selected as peripheral clock
value: 5
enum/USBPDCTRL:
bit_size: 1
variants:
- name: RemainPowered
description: In SUSPEND, PHY state machine, bias and USBPHYC PLL remain powered (default after reset).
value: 0
- name: PowerDown
description: In SUSPEND, PHY state machine, bias and USBPHYC PLL are powered down.
value: 1
enum/USBPHYCSEL:
bit_size: 2
variants:
- name: HSE
description: hse_ker_ck (default after reset).
value: 0
- name: HSE_DIV_2
description: hse_ker_ck / 2.
value: 1
- name: PLL3_Q
description: pll3_q_ck.
value: 2
enum/USBREFCKSEL:
bit_size: 4
variants:
- name: Mhz16
description: The kernel clock frequency provided to the USBPHYC is 16 MHz.
value: 3
- name: Mhz19_2
description: The kernel clock frequency provided to the USBPHYC is 19.2 MHz.
value: 8
- name: Mhz20
description: The kernel clock frequency provided to the USBPHYC is 20MHz.
value: 9
- name: Mhz24
description: The kernel clock frequency provided to the USBPHYC is 24 MHz (default after reset).
value: 10
- name: Mhz32
description: The kernel clock frequency provided to the USBPHYC is 32 MHz.
value: 11
- name: Mhz26
description: The kernel clock frequency provided to the USBPHYC is 26 MHz.
value: 14
enum/USB_OTG_FSSEL:
bit_size: 2
variants:
- name: HSI48
description: hsi48_ker_ck (default after reset).
value: 0
- name: PLL3_Q
description: pll3_q_ck.
value: 1
- name: HSE
description: hse_ker_ck.
value: 2
- name: CLK48MOHCI
description: clk48mohci.
value: 3
enum/XSPISWP:
bit_size: 3
variants:
- name: B_0x0
description: The switch is in neutral mode and output clock is gated (default after reset).
value: 0
- name: B_0x1
description: The switch is selecting hclk5.
value: 1
- name: B_0x2
description: The switch is selecting pll2_s_ck.
value: 2
- name: B_0x3
description: The switch is selecting pll2_t_ck.
value: 3
- name: B_0x4
description: The switch is in recovery position (hclk5/4).
value: 4
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