1760 lines
41 KiB
YAML
1760 lines
41 KiB
YAML
block/FDCAN:
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description: Controller area network with flexible data rate (FD)
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items:
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- name: CREL
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description: FDCAN Core Release Register
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byte_offset: 0
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fieldset: CREL
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- name: ENDN
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description: FDCAN Core Release Register
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byte_offset: 4
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fieldset: ENDN
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- name: DBTP
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description: FDCAN Data Bit Timing and Prescaler Register
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byte_offset: 12
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fieldset: DBTP
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- name: TEST
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description: FDCAN Test Register
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byte_offset: 16
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fieldset: TEST
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- name: RWD
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description: FDCAN RAM Watchdog Register
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byte_offset: 20
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fieldset: RWD
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- name: CCCR
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description: FDCAN CC Control Register
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byte_offset: 24
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fieldset: CCCR
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- name: NBTP
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description: FDCAN Nominal Bit Timing and Prescaler Register
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byte_offset: 28
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fieldset: NBTP
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- name: TSCC
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description: FDCAN Timestamp Counter Configuration Register
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byte_offset: 32
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fieldset: TSCC
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- name: TSCV
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description: FDCAN Timestamp Counter Value Register
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byte_offset: 36
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fieldset: TSCV
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- name: TOCC
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description: FDCAN Timeout Counter Configuration Register
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byte_offset: 40
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fieldset: TOCC
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- name: TOCV
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description: FDCAN Timeout Counter Value Register
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byte_offset: 44
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fieldset: TOCV
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- name: ECR
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description: FDCAN Error Counter Register
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byte_offset: 64
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fieldset: ECR
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- name: PSR
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description: FDCAN Protocol Status Register
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byte_offset: 68
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fieldset: PSR
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- name: TDCR
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description: FDCAN Transmitter Delay Compensation Register
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byte_offset: 72
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fieldset: TDCR
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- name: IR
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description: FDCAN Interrupt Register
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byte_offset: 80
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fieldset: IR
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- name: IE
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description: FDCAN Interrupt Enable Register
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byte_offset: 84
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fieldset: IE
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- name: ILS
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description: FDCAN Interrupt Line Select Register
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byte_offset: 88
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fieldset: ILS
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- name: ILE
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description: FDCAN Interrupt Line Enable Register
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byte_offset: 92
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fieldset: ILE
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- name: GFC
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description: FDCAN Global Filter Configuration Register
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byte_offset: 128
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fieldset: GFC
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- name: SIDFC
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description: FDCAN Standard ID Filter Configuration Register
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byte_offset: 132
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fieldset: SIDFC
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- name: XIDFC
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description: FDCAN Extended ID Filter Configuration Register
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byte_offset: 136
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fieldset: XIDFC
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- name: XIDAM
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description: FDCAN Extended ID and Mask Register
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byte_offset: 144
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fieldset: XIDAM
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- name: HPMS
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description: FDCAN High Priority Message Status Register
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byte_offset: 148
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fieldset: HPMS
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- name: NDAT1
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description: FDCAN New Data 1 Register
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byte_offset: 152
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fieldset: NDAT1
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- name: NDAT2
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description: FDCAN New Data 2 Register
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byte_offset: 156
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fieldset: NDAT2
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- name: RXFC
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description: FDCAN Rx FIFO X Configuration Register
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array:
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offsets:
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- 0
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- 16
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byte_offset: 160
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fieldset: RXFC
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- name: RXFS
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description: FDCAN Rx FIFO X Status Register
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array:
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offsets:
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- 0
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- 16
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byte_offset: 164
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fieldset: RXFS
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- name: RXFA
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description: CAN Rx FIFO X Acknowledge Register
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array:
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offsets:
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- 0
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- 16
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byte_offset: 168
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fieldset: RXFA
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- name: RXBC
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description: FDCAN Rx Buffer Configuration Register
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byte_offset: 172
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fieldset: RXBC
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- name: RXESC
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description: FDCAN Rx Buffer Element Size Configuration Register
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byte_offset: 188
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fieldset: RXESC
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- name: TXBC
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description: FDCAN Tx Buffer Configuration Register
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byte_offset: 192
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fieldset: TXBC
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- name: TXFQS
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description: FDCAN Tx FIFO/Queue Status Register
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byte_offset: 196
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fieldset: TXFQS
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- name: TXESC
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description: FDCAN Tx Buffer Element Size Configuration Register
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byte_offset: 200
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fieldset: TXESC
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- name: TXBRP
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description: FDCAN Tx Buffer Request Pending Register
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byte_offset: 204
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fieldset: TXBRP
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- name: TXBAR
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description: FDCAN Tx Buffer Add Request Register
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byte_offset: 208
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fieldset: TXBAR
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- name: TXBCR
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description: FDCAN Tx Buffer Cancellation Request Register
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byte_offset: 212
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fieldset: TXBCR
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- name: TXBTO
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description: FDCAN Tx Buffer Transmission Occurred Register
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byte_offset: 216
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fieldset: TXBTO
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- name: TXBCF
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description: FDCAN Tx Buffer Cancellation Finished Register
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byte_offset: 220
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fieldset: TXBCF
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- name: TXBTIE
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description: FDCAN Tx Buffer Transmission Interrupt Enable Register
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byte_offset: 224
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fieldset: TXBTIE
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- name: TXBCIE
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description: FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register
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byte_offset: 228
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fieldset: TXBCIE
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- name: TXEFC
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description: FDCAN Tx Event FIFO Configuration Register
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byte_offset: 240
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fieldset: TXEFC
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- name: TXEFS
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description: FDCAN Tx Event FIFO Status Register
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byte_offset: 244
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fieldset: TXEFS
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- name: TXEFA
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description: FDCAN Tx Event FIFO Acknowledge Register
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byte_offset: 248
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fieldset: TXEFA
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- name: TTTMC
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description: FDCAN TT Trigger Memory Configuration Register
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byte_offset: 256
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fieldset: TTTMC
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- name: TTRMC
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description: FDCAN TT Reference Message Configuration Register
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byte_offset: 260
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fieldset: TTRMC
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- name: TTOCF
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description: FDCAN TT Operation Configuration Register
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byte_offset: 264
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fieldset: TTOCF
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- name: TTMLM
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description: FDCAN TT Matrix Limits Register
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byte_offset: 268
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fieldset: TTMLM
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- name: TURCF
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description: FDCAN TUR Configuration Register
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byte_offset: 272
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fieldset: TURCF
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- name: TTOCN
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description: FDCAN TT Operation Control Register
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byte_offset: 276
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fieldset: TTOCN
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- name: TTGTP
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description: FDCAN TT Global Time Preset Register
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byte_offset: 280
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fieldset: TTGTP
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- name: TTTMK
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description: FDCAN TT Time Mark Register
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byte_offset: 284
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fieldset: TTTMK
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- name: TTIR
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description: FDCAN TT Interrupt Register
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byte_offset: 288
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fieldset: TTIR
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- name: TTIE
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description: FDCAN TT Interrupt Enable Register
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byte_offset: 292
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fieldset: TTIE
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- name: TTILS
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description: FDCAN TT Interrupt Line Select Register
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byte_offset: 296
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fieldset: TTILS
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- name: TTOST
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description: FDCAN TT Operation Status Register
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byte_offset: 300
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fieldset: TTOST
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- name: TURNA
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description: FDCAN TUR Numerator Actual Register
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byte_offset: 304
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fieldset: TURNA
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- name: TTLGT
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description: FDCAN TT Local and Global Time Register
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byte_offset: 308
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fieldset: TTLGT
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- name: TTCTC
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description: FDCAN TT Cycle Time and Count Register
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byte_offset: 312
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fieldset: TTCTC
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- name: TTCPT
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description: FDCAN TT Capture Time Register
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byte_offset: 316
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fieldset: TTCPT
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- name: TTCSM
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description: FDCAN TT Cycle Sync Mark Register
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byte_offset: 320
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fieldset: TTCSM
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- name: TTTS
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description: FDCAN TT Trigger Select Register
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byte_offset: 768
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fieldset: TTTS
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fieldset/CCCR:
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description: FDCAN CC Control Register
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fields:
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- name: INIT
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description: Initialization
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bit_offset: 0
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bit_size: 1
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- name: CCE
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description: Configuration Change Enable
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bit_offset: 1
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bit_size: 1
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- name: ASM
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description: ASM Restricted Operation Mode
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bit_offset: 2
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bit_size: 1
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- name: CSA
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description: Clock Stop Acknowledge
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bit_offset: 3
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bit_size: 1
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- name: CSR
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description: Clock Stop Request
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bit_offset: 4
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bit_size: 1
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- name: MON
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description: Bus Monitoring Mode
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bit_offset: 5
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bit_size: 1
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- name: DAR
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description: Disable Automatic Retransmission
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bit_offset: 6
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bit_size: 1
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- name: TEST
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description: Test Mode Enable
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bit_offset: 7
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bit_size: 1
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- name: FDOE
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description: FD Operation Enable
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bit_offset: 8
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bit_size: 1
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- name: BSE
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description: FDCAN Bit Rate Switching
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bit_offset: 9
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bit_size: 1
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- name: PXHD
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description: Protocol Exception Handling Disable
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bit_offset: 12
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bit_size: 1
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- name: EFBI
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description: Edge Filtering during Bus Integration
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bit_offset: 13
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bit_size: 1
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- name: TXP
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description: TXP
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bit_offset: 14
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bit_size: 1
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- name: NISO
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description: Non ISO Operation
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bit_offset: 15
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bit_size: 1
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fieldset/CREL:
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description: FDCAN Core Release Register
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fields:
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- name: DAY
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description: Timestamp Day
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bit_offset: 0
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bit_size: 8
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- name: MON
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description: Timestamp Month
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bit_offset: 8
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bit_size: 8
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- name: YEAR
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description: Timestamp Year
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bit_offset: 16
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bit_size: 4
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- name: SUBSTEP
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description: Sub-step of Core release
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bit_offset: 20
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bit_size: 4
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- name: STEP
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description: Step of Core release
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bit_offset: 24
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bit_size: 4
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- name: REL
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description: Core release
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bit_offset: 28
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bit_size: 4
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fieldset/DBTP:
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description: FDCAN Data Bit Timing and Prescaler Register
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fields:
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- name: DSJW
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description: Synchronization Jump Width
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bit_offset: 0
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bit_size: 4
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- name: DTSEG2
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description: Data time segment after sample point
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bit_offset: 4
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bit_size: 4
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- name: DTSEG1
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description: Data time segment after sample point
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bit_offset: 8
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bit_size: 5
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- name: DBRP
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description: Data BIt Rate Prescaler
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bit_offset: 16
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bit_size: 5
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- name: TDC
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description: Transceiver Delay Compensation
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bit_offset: 23
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bit_size: 1
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fieldset/ECR:
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description: FDCAN Error Counter Register
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fields:
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- name: TEC
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description: Transmit Error Counter
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bit_offset: 0
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bit_size: 8
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- name: REC
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description: Receive Error Counter
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bit_offset: 8
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bit_size: 7
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- name: RP
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description: Receive Error Passive
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bit_offset: 15
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bit_size: 1
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- name: CEL
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description: AN Error Logging
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bit_offset: 16
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bit_size: 8
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fieldset/ENDN:
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description: FDCAN Core Release Register
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fields:
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- name: ETV
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description: Endiannes Test Value
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bit_offset: 0
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bit_size: 32
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fieldset/GFC:
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description: FDCAN Global Filter Configuration Register
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fields:
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- name: RRFE
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description: Reject Remote Frames Extended
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bit_offset: 0
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bit_size: 1
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- name: RRFS
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description: Reject Remote Frames Standard
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bit_offset: 1
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bit_size: 1
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- name: ANFE
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description: Accept Non-matching Frames Extended
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bit_offset: 2
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bit_size: 2
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- name: ANFS
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description: Accept Non-matching Frames Standard
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bit_offset: 4
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bit_size: 2
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fieldset/HPMS:
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description: FDCAN High Priority Message Status Register
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fields:
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- name: BIDX
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description: Buffer Index
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bit_offset: 0
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bit_size: 6
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- name: MSI
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description: Message Storage Indicator
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bit_offset: 6
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bit_size: 2
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- name: FIDX
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description: Filter Index
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bit_offset: 8
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bit_size: 7
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- name: FLST
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description: Filter List
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bit_offset: 15
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bit_size: 1
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fieldset/IE:
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description: FDCAN Interrupt Enable Register
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fields:
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- name: RFNE
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description: Rx FIFO X New Message Enable
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bit_offset: 0
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bit_size: 1
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array:
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offsets:
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- 0
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- 4
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- name: RFWE
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description: Rx FIFO X Watermark Reached Enable
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bit_offset: 1
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bit_size: 1
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array:
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offsets:
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- 0
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- 4
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- name: RFFE
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description: Rx FIFO X Full Enable
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bit_offset: 2
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bit_size: 1
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array:
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offsets:
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- 0
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- 4
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- name: RFLE
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description: Rx FIFO X Message Lost Enable
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bit_offset: 3
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bit_size: 1
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array:
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offsets:
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- 0
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- 4
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- name: HPME
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description: High Priority Message Enable
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bit_offset: 8
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bit_size: 1
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- name: TCE
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description: Transmission Completed Enable
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bit_offset: 9
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bit_size: 1
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- name: TCFE
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description: Transmission Cancellation Finished Enable
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bit_offset: 10
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bit_size: 1
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- name: TEFE
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description: Tx FIFO Empty Enable
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bit_offset: 11
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bit_size: 1
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- name: TEFNE
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description: Tx Event FIFO New Entry Enable
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bit_offset: 12
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bit_size: 1
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- name: TEFWE
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description: Tx Event FIFO Watermark Reached Enable
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bit_offset: 13
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bit_size: 1
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- name: TEFFE
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description: Tx Event FIFO Full Enable
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bit_offset: 14
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bit_size: 1
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- name: TEFLE
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description: Tx Event FIFO Element Lost Enable
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bit_offset: 15
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bit_size: 1
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- name: TSWE
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description: Timestamp Wraparound Enable
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bit_offset: 16
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bit_size: 1
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- name: MRAFE
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description: Message RAM Access Failure Enable
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bit_offset: 17
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bit_size: 1
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- name: TOOE
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description: Timeout Occurred Enable
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bit_offset: 18
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bit_size: 1
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- name: DRXE
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description: Message stored to Dedicated Rx Buffer Enable
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bit_offset: 19
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bit_size: 1
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- name: BECE
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description: Bit Error Corrected Interrupt Enable
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bit_offset: 20
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bit_size: 1
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- name: BEUE
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description: Bit Error Uncorrected Interrupt Enable
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bit_offset: 21
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bit_size: 1
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- name: ELOE
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description: Error Logging Overflow Enable
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bit_offset: 22
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bit_size: 1
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- name: EPE
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description: Error Passive Enable
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bit_offset: 23
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bit_size: 1
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- name: EWE
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description: Warning Status Enable
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bit_offset: 24
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bit_size: 1
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- name: BOE
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description: Bus_Off Status Enable
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bit_offset: 25
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bit_size: 1
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- name: WDIE
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description: Watchdog Interrupt Enable
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bit_offset: 26
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bit_size: 1
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- name: PEAE
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description: Protocol Error in Arbitration Phase Enable
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bit_offset: 27
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bit_size: 1
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- name: PEDE
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description: Protocol Error in Data Phase Enable
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bit_offset: 28
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bit_size: 1
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- name: ARAE
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description: Access to Reserved Address Enable
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bit_offset: 29
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bit_size: 1
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fieldset/ILE:
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description: FDCAN Interrupt Line Enable Register
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fields:
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- name: EINT0
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description: Enable Interrupt Line 0
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bit_offset: 0
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bit_size: 1
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- name: EINT1
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description: Enable Interrupt Line 1
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bit_offset: 1
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bit_size: 1
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fieldset/ILS:
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description: FDCAN Interrupt Line Select Register
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fields:
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- name: RFNL
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description: Rx FIFO X New Message Interrupt Line
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bit_offset: 0
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bit_size: 1
|
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array:
|
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offsets:
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- 0
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- 4
|
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- name: RFWL
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description: Rx FIFO X Watermark Reached Interrupt Line
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|
bit_offset: 1
|
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bit_size: 1
|
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array:
|
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offsets:
|
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- 0
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- 4
|
|
- name: RFFL
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|
description: Rx FIFO X Full Interrupt Line
|
|
bit_offset: 2
|
|
bit_size: 1
|
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array:
|
|
offsets:
|
|
- 0
|
|
- 4
|
|
- name: RFLL
|
|
description: Rx FIFO X Message Lost Interrupt Line
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
array:
|
|
offsets:
|
|
- 0
|
|
- 4
|
|
- name: HPML
|
|
description: High Priority Message Interrupt Line
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: TCL
|
|
description: Transmission Completed Interrupt Line
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: TCFL
|
|
description: Transmission Cancellation Finished Interrupt Line
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: TEFL
|
|
description: Tx FIFO Empty Interrupt Line
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: TEFNL
|
|
description: Tx Event FIFO New Entry Interrupt Line
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: TEFWL
|
|
description: Tx Event FIFO Watermark Reached Interrupt Line
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: TEFFL
|
|
description: Tx Event FIFO Full Interrupt Line
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TEFLL
|
|
description: Tx Event FIFO Element Lost Interrupt Line
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: TSWL
|
|
description: Timestamp Wraparound Interrupt Line
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: MRAFL
|
|
description: Message RAM Access Failure Interrupt Line
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TOOL
|
|
description: Timeout Occurred Interrupt Line
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: DRXL
|
|
description: Message stored to Dedicated Rx Buffer Interrupt Line
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: BECL
|
|
description: Bit Error Corrected Interrupt Line
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: BEUL
|
|
description: Bit Error Uncorrected Interrupt Line
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: ELOL
|
|
description: Error Logging Overflow Interrupt Line
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: EPL
|
|
description: Error Passive Interrupt Line
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: EWL
|
|
description: Warning Status Interrupt Line
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: BOL
|
|
description: Bus_Off Status
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: WDIL
|
|
description: Watchdog Interrupt Line
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: PEAL
|
|
description: Protocol Error in Arbitration Phase Line
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: PEDL
|
|
description: Protocol Error in Data Phase Line
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: ARAL
|
|
description: Access to Reserved Address Line
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
fieldset/IR:
|
|
description: FDCAN Interrupt Register
|
|
fields:
|
|
- name: RFN
|
|
description: Rx FIFO X New Message
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
array:
|
|
offsets:
|
|
- 0
|
|
- 4
|
|
- name: RFW
|
|
description: Rx FIFO X Watermark Reached
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
array:
|
|
offsets:
|
|
- 0
|
|
- 4
|
|
- name: RFF
|
|
description: Rx FIFO X Full
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
array:
|
|
offsets:
|
|
- 0
|
|
- 4
|
|
- name: RFL
|
|
description: Rx FIFO X Message Lost
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
array:
|
|
offsets:
|
|
- 0
|
|
- 4
|
|
- name: HPM
|
|
description: High Priority Message
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: TC
|
|
description: Transmission Completed
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: TCF
|
|
description: Transmission Cancellation Finished
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: TEF
|
|
description: Tx FIFO Empty
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: TEFN
|
|
description: Tx Event FIFO New Entry
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: TEFW
|
|
description: Tx Event FIFO Watermark Reached
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: TEFF
|
|
description: Tx Event FIFO Full
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TEFL
|
|
description: Tx Event FIFO Element Lost
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: TSW
|
|
description: Timestamp Wraparound
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: MRAF
|
|
description: Message RAM Access Failure
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TOO
|
|
description: Timeout Occurred
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: DRX
|
|
description: Message stored to Dedicated Rx Buffer
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: ELO
|
|
description: Error Logging Overflow
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: EP
|
|
description: Error Passive
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: EW
|
|
description: Warning Status
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: BO
|
|
description: Bus_Off Status
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: WDI
|
|
description: Watchdog Interrupt
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: PEA
|
|
description: Protocol Error in Arbitration Phase (Nominal Bit Time is used)
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: PED
|
|
description: Protocol Error in Data Phase (Data Bit Time is used)
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: ARA
|
|
description: Access to Reserved Address
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
fieldset/NBTP:
|
|
description: FDCAN Nominal Bit Timing and Prescaler Register
|
|
fields:
|
|
- name: NTSEG2
|
|
description: Nominal Time segment after sample point
|
|
bit_offset: 0
|
|
bit_size: 7
|
|
- name: NTSEG1
|
|
description: Nominal Time segment before sample point
|
|
bit_offset: 8
|
|
bit_size: 8
|
|
- name: NBRP
|
|
description: Bit Rate Prescaler
|
|
bit_offset: 16
|
|
bit_size: 9
|
|
- name: NSJW
|
|
description: 'NSJW: Nominal (Re)Synchronization Jump Width.'
|
|
bit_offset: 25
|
|
bit_size: 7
|
|
fieldset/NDAT1:
|
|
description: FDCAN New Data 1 Register
|
|
fields:
|
|
- name: ND
|
|
description: New data (buffers 0 - 31)
|
|
bit_offset: 0
|
|
bit_size: 32
|
|
fieldset/NDAT2:
|
|
description: FDCAN New Data 2 Register
|
|
fields:
|
|
- name: ND
|
|
description: New data (buffers 32 - 63)
|
|
bit_offset: 0
|
|
bit_size: 32
|
|
fieldset/PSR:
|
|
description: FDCAN Protocol Status Register
|
|
fields:
|
|
- name: LEC
|
|
description: Last Error Code
|
|
bit_offset: 0
|
|
bit_size: 3
|
|
- name: ACT
|
|
description: Activity
|
|
bit_offset: 3
|
|
bit_size: 2
|
|
- name: EP
|
|
description: Error Passive
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: EW
|
|
description: Warning Status
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: BO
|
|
description: Bus_Off Status
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: DLEC
|
|
description: Data Last Error Code
|
|
bit_offset: 8
|
|
bit_size: 3
|
|
- name: RESI
|
|
description: ESI flag of last received FDCAN Message
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: RBRS
|
|
description: BRS flag of last received FDCAN Message
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: REDL
|
|
description: Received FDCAN Message
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: PXE
|
|
description: Protocol Exception Event
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TDCV
|
|
description: Transmitter Delay Compensation Value
|
|
bit_offset: 16
|
|
bit_size: 7
|
|
fieldset/RWD:
|
|
description: FDCAN RAM Watchdog Register
|
|
fields:
|
|
- name: WDC
|
|
description: Watchdog configuration
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
- name: WDV
|
|
description: Watchdog value
|
|
bit_offset: 8
|
|
bit_size: 8
|
|
fieldset/RXBC:
|
|
description: FDCAN Rx Buffer Configuration Register
|
|
fields:
|
|
- name: RBSA
|
|
description: Rx Buffer Start Address
|
|
bit_offset: 2
|
|
bit_size: 14
|
|
fieldset/RXESC:
|
|
description: FDCAN Rx Buffer Element Size Configuration Register
|
|
fields:
|
|
- name: FDS
|
|
description: Rx FIFO X Data Field Size
|
|
bit_offset: 0
|
|
bit_size: 3
|
|
array:
|
|
offsets:
|
|
- 0
|
|
- 4
|
|
- name: RBDS
|
|
description: Rx Buffer Data Field Size
|
|
bit_offset: 8
|
|
bit_size: 3
|
|
fieldset/RXFA:
|
|
description: CAN Rx FIFO X Acknowledge Register
|
|
fields:
|
|
- name: FAI
|
|
description: Rx FIFO X Acknowledge Index
|
|
bit_offset: 0
|
|
bit_size: 6
|
|
fieldset/RXFC:
|
|
description: FDCAN Rx FIFO X Configuration Register
|
|
fields:
|
|
- name: FSA
|
|
description: Rx FIFO X Start Address
|
|
bit_offset: 2
|
|
bit_size: 14
|
|
- name: FS
|
|
description: Rx FIFO X Size
|
|
bit_offset: 16
|
|
bit_size: 7
|
|
- name: FWM
|
|
description: FIFO X Watermark
|
|
bit_offset: 24
|
|
bit_size: 7
|
|
- name: FOM
|
|
description: FIFO X operation mode
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/RXFS:
|
|
description: FDCAN Rx FIFO X Status Register
|
|
fields:
|
|
- name: FFL
|
|
description: Rx FIFO X Fill Level
|
|
bit_offset: 0
|
|
bit_size: 7
|
|
- name: FGI
|
|
description: Rx FIFO X Get Index
|
|
bit_offset: 8
|
|
bit_size: 6
|
|
- name: FPI
|
|
description: Rx FIFO X Put Index
|
|
bit_offset: 16
|
|
bit_size: 6
|
|
- name: FF
|
|
description: Rx FIFO X Full
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: RFL
|
|
description: Rx FIFO X Message Lost
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
fieldset/SIDFC:
|
|
description: FDCAN Standard ID Filter Configuration Register
|
|
fields:
|
|
- name: FLSSA
|
|
description: Filter List Standard Start Address
|
|
bit_offset: 2
|
|
bit_size: 14
|
|
- name: LSS
|
|
description: List Size Standard
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
fieldset/TDCR:
|
|
description: FDCAN Transmitter Delay Compensation Register
|
|
fields:
|
|
- name: TDCF
|
|
description: Transmitter Delay Compensation Filter Window Length
|
|
bit_offset: 0
|
|
bit_size: 7
|
|
- name: TDCO
|
|
description: Transmitter Delay Compensation Offset
|
|
bit_offset: 8
|
|
bit_size: 7
|
|
fieldset/TEST:
|
|
description: FDCAN Test Register
|
|
fields:
|
|
- name: LBCK
|
|
description: Loop Back mode
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: TX
|
|
description: Loop Back mode
|
|
bit_offset: 5
|
|
bit_size: 2
|
|
- name: RX
|
|
description: Control of Transmit Pin
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
fieldset/TOCC:
|
|
description: FDCAN Timeout Counter Configuration Register
|
|
fields:
|
|
- name: ETOC
|
|
description: Enable Timeout Counter
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: TOS
|
|
description: Timeout Select
|
|
bit_offset: 1
|
|
bit_size: 2
|
|
- name: TOP
|
|
description: Timeout Period
|
|
bit_offset: 16
|
|
bit_size: 16
|
|
fieldset/TOCV:
|
|
description: FDCAN Timeout Counter Value Register
|
|
fields:
|
|
- name: TOC
|
|
description: Timeout Counter
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/TSCC:
|
|
description: FDCAN Timestamp Counter Configuration Register
|
|
fields:
|
|
- name: TSS
|
|
description: Timestamp Select
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: TCP
|
|
description: Timestamp Counter Prescaler
|
|
bit_offset: 16
|
|
bit_size: 4
|
|
fieldset/TSCV:
|
|
description: FDCAN Timestamp Counter Value Register
|
|
fields:
|
|
- name: TSC
|
|
description: Timestamp Counter
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/TTCPT:
|
|
description: FDCAN TT Capture Time Register
|
|
fields:
|
|
- name: CCV
|
|
description: Cycle Count Value
|
|
bit_offset: 0
|
|
bit_size: 6
|
|
- name: SWV
|
|
description: Stop Watch Value
|
|
bit_offset: 16
|
|
bit_size: 16
|
|
fieldset/TTCSM:
|
|
description: FDCAN TT Cycle Sync Mark Register
|
|
fields:
|
|
- name: CSM
|
|
description: Cycle Sync Mark
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/TTCTC:
|
|
description: FDCAN TT Cycle Time and Count Register
|
|
fields:
|
|
- name: CT
|
|
description: Cycle Time
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
- name: CC
|
|
description: Cycle Count
|
|
bit_offset: 16
|
|
bit_size: 6
|
|
fieldset/TTGTP:
|
|
description: FDCAN TT Global Time Preset Register
|
|
fields:
|
|
- name: NCL
|
|
description: Time Preset
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
- name: CTP
|
|
description: Cycle Time Target Phase
|
|
bit_offset: 16
|
|
bit_size: 16
|
|
fieldset/TTIE:
|
|
description: FDCAN TT Interrupt Enable Register
|
|
fields:
|
|
- name: SBCE
|
|
description: Start of Basic Cycle Interrupt Enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: SMCE
|
|
description: Start of Matrix Cycle Interrupt Enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: CSME
|
|
description: Change of Synchronization Mode Interrupt Enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: SOGE
|
|
description: Start of Gap Interrupt Enable
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: RTMIE
|
|
description: Register Time Mark Interrupt Enable
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: TTMIE
|
|
description: Trigger Time Mark Event Internal Interrupt Enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: SWEE
|
|
description: Stop Watch Event Interrupt Enable
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: GTWE
|
|
description: Global Time Wrap Interrupt Enable
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: GTDE
|
|
description: Global Time Discontinuity Interrupt Enable
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: GTEE
|
|
description: Global Time Error Interrupt Enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: TXUE
|
|
description: Tx Count Underflow Interrupt Enable
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: TXOE
|
|
description: Tx Count Overflow Interrupt Enable
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SE1E
|
|
description: Scheduling Error 1 Interrupt Enable
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: SE2E
|
|
description: Scheduling Error 2 Interrupt Enable
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: ELCE
|
|
description: Change Error Level Interrupt Enable
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: IWTGE
|
|
description: Initialization Watch Trigger Interrupt Enable
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: WTE
|
|
description: Watch Trigger Interrupt Enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: AWE
|
|
description: Application Watchdog Interrupt Enable
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: CERE
|
|
description: Configuration Error Interrupt Enable
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
fieldset/TTILS:
|
|
description: FDCAN TT Interrupt Line Select Register
|
|
fields:
|
|
- name: SBCL
|
|
description: Start of Basic Cycle Interrupt Line
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: SMCL
|
|
description: Start of Matrix Cycle Interrupt Line
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: CSML
|
|
description: Change of Synchronization Mode Interrupt Line
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: SOGL
|
|
description: Start of Gap Interrupt Line
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: RTMIL
|
|
description: Register Time Mark Interrupt Line
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: TTMIL
|
|
description: Trigger Time Mark Event Internal Interrupt Line
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: SWEL
|
|
description: Stop Watch Event Interrupt Line
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: GTWL
|
|
description: Global Time Wrap Interrupt Line
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: GTDL
|
|
description: Global Time Discontinuity Interrupt Line
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: GTEL
|
|
description: Global Time Error Interrupt Line
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: TXUL
|
|
description: Tx Count Underflow Interrupt Line
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: TXOL
|
|
description: Tx Count Overflow Interrupt Line
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SE1L
|
|
description: Scheduling Error 1 Interrupt Line
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: SE2L
|
|
description: Scheduling Error 2 Interrupt Line
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: ELCL
|
|
description: Change Error Level Interrupt Line
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: IWTGL
|
|
description: Initialization Watch Trigger Interrupt Line
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: WTL
|
|
description: Watch Trigger Interrupt Line
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: AWL
|
|
description: Application Watchdog Interrupt Line
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: CERL
|
|
description: Configuration Error Interrupt Line
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
fieldset/TTIR:
|
|
description: FDCAN TT Interrupt Register
|
|
fields:
|
|
- name: SBC
|
|
description: Start of Basic Cycle
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: SMC
|
|
description: Start of Matrix Cycle
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: CSM
|
|
description: Change of Synchronization Mode
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: SOG
|
|
description: Start of Gap
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: RTMI
|
|
description: Register Time Mark Interrupt
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: TTMI
|
|
description: Trigger Time Mark Event Internal
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: SWE
|
|
description: Stop Watch Event
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: GTW
|
|
description: Global Time Wrap
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: GTD
|
|
description: Global Time Discontinuity
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: GTE
|
|
description: Global Time Error
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: TXU
|
|
description: Tx Count Underflow
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: TXO
|
|
description: Tx Count Overflow
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SE1
|
|
description: Scheduling Error 1
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: SE2
|
|
description: Scheduling Error 2
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: ELC
|
|
description: Error Level Changed
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: IWTG
|
|
description: Initialization Watch Trigger
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: WT
|
|
description: Watch Trigger
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: AW
|
|
description: Application Watchdog
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: CER
|
|
description: Configuration Error
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
fieldset/TTLGT:
|
|
description: FDCAN TT Local and Global Time Register
|
|
fields:
|
|
- name: LT
|
|
description: Local Time
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
- name: GT
|
|
description: Global Time
|
|
bit_offset: 16
|
|
bit_size: 16
|
|
fieldset/TTMLM:
|
|
description: FDCAN TT Matrix Limits Register
|
|
fields:
|
|
- name: CCM
|
|
description: Cycle Count Max
|
|
bit_offset: 0
|
|
bit_size: 6
|
|
- name: CSS
|
|
description: Cycle Start Synchronization
|
|
bit_offset: 6
|
|
bit_size: 2
|
|
- name: TXEW
|
|
description: Tx Enable Window
|
|
bit_offset: 8
|
|
bit_size: 4
|
|
- name: ENTT
|
|
description: Expected Number of Tx Triggers
|
|
bit_offset: 16
|
|
bit_size: 12
|
|
fieldset/TTOCF:
|
|
description: FDCAN TT Operation Configuration Register
|
|
fields:
|
|
- name: OM
|
|
description: Operation Mode
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: GEN
|
|
description: Gap Enable
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: TM
|
|
description: Time Master
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: LDSDL
|
|
description: LD of Synchronization Deviation Limit
|
|
bit_offset: 5
|
|
bit_size: 3
|
|
- name: IRTO
|
|
description: Initial Reference Trigger Offset
|
|
bit_offset: 8
|
|
bit_size: 7
|
|
- name: EECS
|
|
description: Enable External Clock Synchronization
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: AWL
|
|
description: Application Watchdog Limit
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
- name: EGTF
|
|
description: Enable Global Time Filtering
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: ECC
|
|
description: Enable Clock Calibration
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: EVTP
|
|
description: Event Trigger Polarity
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
fieldset/TTOCN:
|
|
description: FDCAN TT Operation Control Register
|
|
fields:
|
|
- name: SGT
|
|
description: Set Global time
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: ECS
|
|
description: External Clock Synchronization
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: SWP
|
|
description: Stop Watch Polarity
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: SWS
|
|
description: Stop Watch Source
|
|
bit_offset: 3
|
|
bit_size: 2
|
|
- name: RTIE
|
|
description: Register Time Mark Interrupt Pulse Enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: TMC
|
|
description: Register Time Mark Compare
|
|
bit_offset: 6
|
|
bit_size: 2
|
|
- name: TTIE
|
|
description: Trigger Time Mark Interrupt Pulse Enable
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: GCS
|
|
description: Gap Control Select
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: FGP
|
|
description: Finish Gap
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: TMG
|
|
description: Time Mark Gap
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: NIG
|
|
description: Next is Gap
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: ESCN
|
|
description: External Synchronization Control
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: LCKC
|
|
description: TT Operation Control Register Locked
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
fieldset/TTOST:
|
|
description: FDCAN TT Operation Status Register
|
|
fields:
|
|
- name: EL
|
|
description: Error Level
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: MS
|
|
description: Master State
|
|
bit_offset: 2
|
|
bit_size: 2
|
|
- name: SYS
|
|
description: Synchronization State
|
|
bit_offset: 4
|
|
bit_size: 2
|
|
- name: QGTP
|
|
description: Quality of Global Time Phase
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: QCS
|
|
description: Quality of Clock Speed
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: RTO
|
|
description: Reference Trigger Offset
|
|
bit_offset: 8
|
|
bit_size: 8
|
|
- name: WGTD
|
|
description: Wait for Global Time Discontinuity
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: GFI
|
|
description: Gap Finished Indicator
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: TMP
|
|
description: Time Master Priority
|
|
bit_offset: 24
|
|
bit_size: 3
|
|
- name: GSI
|
|
description: Gap Started Indicator
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: WFE
|
|
description: Wait for Event
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: AWE
|
|
description: Application Watchdog Event
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: WECS
|
|
description: Wait for External Clock Synchronization
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: SPL
|
|
description: Schedule Phase Lock
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/TTRMC:
|
|
description: FDCAN TT Reference Message Configuration Register
|
|
fields:
|
|
- name: RID
|
|
description: Reference Identifier
|
|
bit_offset: 0
|
|
bit_size: 29
|
|
- name: XTD
|
|
description: Extended Identifier
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: RMPS
|
|
description: Reference Message Payload Select
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/TTTMC:
|
|
description: FDCAN TT Trigger Memory Configuration Register
|
|
fields:
|
|
- name: TMSA
|
|
description: Trigger Memory Start Address
|
|
bit_offset: 2
|
|
bit_size: 14
|
|
- name: TME
|
|
description: Trigger Memory Elements
|
|
bit_offset: 16
|
|
bit_size: 7
|
|
fieldset/TTTMK:
|
|
description: FDCAN TT Time Mark Register
|
|
fields:
|
|
- name: TM
|
|
description: Time Mark
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
- name: TICC
|
|
description: Time Mark Cycle Code
|
|
bit_offset: 16
|
|
bit_size: 7
|
|
- name: LCKM
|
|
description: TT Time Mark Register Locked
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/TTTS:
|
|
description: FDCAN TT Trigger Select Register
|
|
fields:
|
|
- name: SWTDEL
|
|
description: Stop watch trigger input selection
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: EVTSEL
|
|
description: Event trigger input selection
|
|
bit_offset: 4
|
|
bit_size: 2
|
|
fieldset/TURCF:
|
|
description: FDCAN TUR Configuration Register
|
|
fields:
|
|
- name: NCL
|
|
description: Numerator Configuration Low
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
- name: DC
|
|
description: Denominator Configuration
|
|
bit_offset: 16
|
|
bit_size: 14
|
|
- name: ELT
|
|
description: Enable Local Time
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/TURNA:
|
|
description: FDCAN TUR Numerator Actual Register
|
|
fields:
|
|
- name: NAV
|
|
description: Numerator Actual Value
|
|
bit_offset: 0
|
|
bit_size: 18
|
|
fieldset/TXBAR:
|
|
description: FDCAN Tx Buffer Add Request Register
|
|
fields:
|
|
- name: AR
|
|
description: Add Request
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
array:
|
|
len: 32
|
|
stride: 1
|
|
fieldset/TXBC:
|
|
description: FDCAN Tx Buffer Configuration Register
|
|
fields:
|
|
- name: TBSA
|
|
description: Tx Buffers Start Address
|
|
bit_offset: 2
|
|
bit_size: 14
|
|
- name: NDTB
|
|
description: Number of Dedicated Transmit Buffers
|
|
bit_offset: 16
|
|
bit_size: 6
|
|
- name: TFQS
|
|
description: Transmit FIFO/Queue Size
|
|
bit_offset: 24
|
|
bit_size: 6
|
|
- name: TFQM
|
|
description: Tx FIFO/Queue Mode
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
fieldset/TXBCF:
|
|
description: FDCAN Tx Buffer Cancellation Finished Register
|
|
fields:
|
|
- name: CF
|
|
description: Cancellation Finished
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
array:
|
|
len: 32
|
|
stride: 1
|
|
fieldset/TXBCIE:
|
|
description: FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register
|
|
fields:
|
|
- name: CF
|
|
description: Cancellation Finished Interrupt Enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
array:
|
|
len: 32
|
|
stride: 1
|
|
fieldset/TXBCR:
|
|
description: FDCAN Tx Buffer Cancellation Request Register
|
|
fields:
|
|
- name: CR
|
|
description: Cancellation Request
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
array:
|
|
len: 32
|
|
stride: 1
|
|
fieldset/TXBRP:
|
|
description: FDCAN Tx Buffer Request Pending Register
|
|
fields:
|
|
- name: TRP
|
|
description: Transmission Request Pending
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
array:
|
|
len: 32
|
|
stride: 1
|
|
fieldset/TXBTIE:
|
|
description: FDCAN Tx Buffer Transmission Interrupt Enable Register
|
|
fields:
|
|
- name: TIE
|
|
description: Transmission Interrupt Enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
array:
|
|
len: 32
|
|
stride: 1
|
|
fieldset/TXBTO:
|
|
description: FDCAN Tx Buffer Transmission Occurred Register
|
|
fields:
|
|
- name: TO
|
|
description: Transmission Occurred
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
array:
|
|
len: 32
|
|
stride: 1
|
|
fieldset/TXEFA:
|
|
description: FDCAN Tx Event FIFO Acknowledge Register
|
|
fields:
|
|
- name: EFAI
|
|
description: Event FIFO Acknowledge Index
|
|
bit_offset: 0
|
|
bit_size: 5
|
|
fieldset/TXEFC:
|
|
description: FDCAN Tx Event FIFO Configuration Register
|
|
fields:
|
|
- name: EFSA
|
|
description: Event FIFO Start Address
|
|
bit_offset: 2
|
|
bit_size: 14
|
|
- name: EFS
|
|
description: Event FIFO Size
|
|
bit_offset: 16
|
|
bit_size: 6
|
|
- name: EFWM
|
|
description: Event FIFO Watermark
|
|
bit_offset: 24
|
|
bit_size: 6
|
|
fieldset/TXEFS:
|
|
description: FDCAN Tx Event FIFO Status Register
|
|
fields:
|
|
- name: EFFL
|
|
description: Event FIFO Fill Level
|
|
bit_offset: 0
|
|
bit_size: 6
|
|
- name: EFGI
|
|
description: Event FIFO Get Index
|
|
bit_offset: 8
|
|
bit_size: 5
|
|
- name: EFPI
|
|
description: Event FIFO put index
|
|
bit_offset: 16
|
|
bit_size: 5
|
|
- name: EFF
|
|
description: Event FIFO Full
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: TEFL
|
|
description: Tx Event FIFO Element Lost
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
fieldset/TXESC:
|
|
description: FDCAN Tx Buffer Element Size Configuration Register
|
|
fields:
|
|
- name: TBDS
|
|
description: Tx Buffer Data Field Size
|
|
bit_offset: 0
|
|
bit_size: 3
|
|
fieldset/TXFQS:
|
|
description: FDCAN Tx FIFO/Queue Status Register
|
|
fields:
|
|
- name: TFFL
|
|
description: Tx FIFO Free Level
|
|
bit_offset: 0
|
|
bit_size: 6
|
|
- name: TFGI
|
|
description: TFGI
|
|
bit_offset: 8
|
|
bit_size: 5
|
|
- name: TFQPI
|
|
description: Tx FIFO/Queue Put Index
|
|
bit_offset: 16
|
|
bit_size: 5
|
|
- name: TFQF
|
|
description: Tx FIFO/Queue Full
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
fieldset/XIDAM:
|
|
description: FDCAN Extended ID and Mask Register
|
|
fields:
|
|
- name: EIDM
|
|
description: Extended ID Mask
|
|
bit_offset: 0
|
|
bit_size: 29
|
|
fieldset/XIDFC:
|
|
description: FDCAN Extended ID Filter Configuration Register
|
|
fields:
|
|
- name: FLESA
|
|
description: Filter List Standard Start Address
|
|
bit_offset: 2
|
|
bit_size: 14
|
|
- name: LSE
|
|
description: List Size Extended
|
|
bit_offset: 16
|
|
bit_size: 8
|