1773 lines
44 KiB
YAML
1773 lines
44 KiB
YAML
---
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block/HRTIM:
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description: "High Resolution Timer: Master Timer"
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items:
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- name: MCR
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description: Master Timer Control Register
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byte_offset: 0
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fieldset: MCR
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- name: MISR
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description: "Master Timer Interrupt Status Register"
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byte_offset: 4
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access: Read
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fieldset: MISR
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- name: MICR
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description: "Master Timer Interrupt Clear Register"
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byte_offset: 8
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access: Write
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fieldset: MICR
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- name: MDIER
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description: MDIER4
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byte_offset: 12
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fieldset: MDIER
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- name: MCNTR
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description: Master Timer Counter Register
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byte_offset: 16
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fieldset: MCNTR
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- name: MPER
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description: Master Timer Period Register
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byte_offset: 20
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fieldset: MPER
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- name: MREP
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description: "Master Timer Repetition Register"
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byte_offset: 24
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fieldset: MREP
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- name: MCMP1R
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description: "Master Timer Compare 1 Register"
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byte_offset: 28
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fieldset: MCMP1R
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- name: MCMP2R
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description: "Master Timer Compare 2 Register"
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byte_offset: 36
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fieldset: MCMP2R
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- name: MCMP3R
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description: "Master Timer Compare 3 Register"
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byte_offset: 40
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fieldset: MCMP3R
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- name: MCMP4R
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description: "Master Timer Compare 4 Register"
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byte_offset: 44
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fieldset: MCMP4R
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- name: TIMX
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description: "High Resolution Timer: TIMX"
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array:
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len: 5
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stride: 128
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byte_offset: 128
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block: HRTIM_TIMX
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block/HRTIM_TIMX:
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description: "High Resolution Timer: TIMA"
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items:
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- name: TIMXCR
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description: Timerx Control Register
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byte_offset: 0
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fieldset: TIMXCR
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- name: TIMXISR
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description: "Timerx Interrupt Status Register"
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byte_offset: 4
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access: Read
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fieldset: TIMXISR
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- name: TIMXICR
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description: "Timerx Interrupt Clear Register"
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byte_offset: 8
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access: Write
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fieldset: TIMXICR
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- name: TIMXDIER
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description: Timerx DMA / Interrupt Enable Register
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byte_offset: 12
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fieldset: TIMXDIER
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- name: CNTXR
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description: Timerx Counter Register
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byte_offset: 16
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fieldset: CNTXR
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- name: PERXR
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description: Timerx Period Register
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byte_offset: 20
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fieldset: PERXR
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- name: REPXR
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description: Timerx Repetition Register
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byte_offset: 24
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fieldset: REPXR
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- name: CMPXXR
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description: Timerx Compare X Register
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byte_offset: 28
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fieldset: CMPXXR
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array:
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offsets:
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- 0
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- 8
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- 12
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- 16
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- name: CMPXCXR
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description: "Timerx Compare X Compound Register"
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byte_offset: 32
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fieldset: CMPXCXR
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array:
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offsets:
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- 0
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- name: CPTXXR
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description: Timerx Capture X Register
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byte_offset: 48
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access: Read
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fieldset: CPTXXR
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array:
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len: 2
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stride: 4
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- name: DTXR
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description: Timerx Deadtime Register
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byte_offset: 56
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fieldset: DTXR
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- name: SETXXR
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description: Timerx OutputX Set Register
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byte_offset: 60
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fieldset: SETXXR
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array:
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offsets:
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- 0
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- 8
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- name: RSTXXR
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description: Timerx OutputX Reset Register
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byte_offset: 64
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fieldset: RSTXXR
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array:
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offsets:
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- 0
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- 8
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- name: EEFXRX
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description: "Timerx External Event Filtering Register 1"
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byte_offset: 76
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fieldset: EEFXRX
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array:
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offsets:
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- 0
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- 4
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- name: RSTXR
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description: Timerx Reset Register
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byte_offset: 84
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fieldset: RSTXR
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- name: CHPXR
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description: Timerx Chopper Register
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byte_offset: 88
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fieldset: CHPXR
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- name: CPTXCR
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description: Timerx Capture X Control Register
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byte_offset: 92
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fieldset: CPTXXCR
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array:
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offsets:
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- 0
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- 4
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- name: OUTXR
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description: Timerx Output Register
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byte_offset: 100
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fieldset: OUTXR
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- name: FLTXR
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description: Timerx Fault Register
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byte_offset: 104
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fieldset: FLTXR
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fieldset/CHPXR:
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description: Timerx Chopper Register
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fields:
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- name: CARFRQ
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description: "Timerx carrier frequency value"
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bit_offset: 0
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bit_size: 4
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- name: CARDTY
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description: "Timerx chopper duty cycle value"
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bit_offset: 4
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bit_size: 3
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- name: STRTPW
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description: STRTPW
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bit_offset: 7
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bit_size: 4
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fieldset/CMPXXR:
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description: Timerx Compare X Register
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fields:
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- name: CMPXx
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description: Timerx Compare X value
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bit_offset: 0
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bit_size: 16
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fieldset/CMPXCXR:
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description: "Timerx Compare X Compound Register"
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fields:
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- name: CMPXx
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description: Timerx Compare X value
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bit_offset: 0
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bit_size: 16
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- name: REPx
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description: "Timerx Repetition value (aliased from HRTIM_REPx register)"
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bit_offset: 16
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bit_size: 8
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fieldset/CNTXR:
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description: Timerx Counter Register
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fields:
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- name: CNTx
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description: Timerx Counter value
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bit_offset: 0
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bit_size: 16
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fieldset/CPTXXCR:
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description: "Timerx Capture 2 Control Register"
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fields:
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- name: SWCPT
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description: Software Capture
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bit_offset: 0
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: UPDCPT
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description: Update Capture
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bit_offset: 1
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: EXEV1CPT
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description: External Event 1 Capture
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bit_offset: 2
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: EXEV2CPT
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description: External Event 2 Capture
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bit_offset: 3
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: EXEV3CPT
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description: External Event 3 Capture
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bit_offset: 4
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: EXEV4CPT
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description: External Event 4 Capture
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bit_offset: 5
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: EXEV5CPT
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description: External Event 5 Capture
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bit_offset: 6
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: EXEV6CPT
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description: External Event 6 Capture
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bit_offset: 7
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: EXEV7CPT
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description: External Event 7 Capture
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bit_offset: 8
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: EXEV8CPT
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description: External Event 8 Capture
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bit_offset: 9
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: EXEV9CPT
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description: External Event 9 Capture
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bit_offset: 10
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: EXEV10CPT
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description: External Event 10 Capture
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bit_offset: 11
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: TB1SET
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description: Timer B output 1 Set
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bit_offset: 16
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: TB1RST
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description: Timer B output 1 Reset
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bit_offset: 17
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: TBCMP1
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description: Timer B Compare 1
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bit_offset: 18
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: TBCMP2
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description: Timer B Compare 2
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bit_offset: 19
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: TC1SET
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description: Timer C output 1 Set
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bit_offset: 20
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: TC1RST
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description: Timer C output 1 Reset
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bit_offset: 21
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: TCCMP1
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description: Timer C Compare 1
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bit_offset: 22
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: TCCMP2
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description: Timer C Compare 2
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bit_offset: 23
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: TD1SET
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description: Timer D output 1 Set
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bit_offset: 24
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: TD1RST
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description: Timer D output 1 Reset
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bit_offset: 25
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: TDCMP1
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description: Timer D Compare 1
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bit_offset: 26
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: TDCMP2
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description: Timer D Compare 2
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bit_offset: 27
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: TE1SET
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description: Timer E output 1 Set
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bit_offset: 28
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: TE1RST
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description: Timer E output 1 Reset
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bit_offset: 29
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: TECMP1
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description: Timer E Compare 1
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bit_offset: 30
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bit_size: 1
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enum: CAPTUREEFFECT
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- name: TECMP2
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description: Timer E Compare 2
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bit_offset: 31
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bit_size: 1
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enum: CAPTUREEFFECT
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fieldset/CPTXXR:
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description: Timerx Capture X Register
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fields:
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- name: CPTXx
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description: Timerx Capture X value
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bit_offset: 0
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bit_size: 16
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fieldset/DTXR:
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description: Timerx Deadtime Register
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fields:
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- name: DTRx
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description: Deadtime Rising value
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bit_offset: 0
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bit_size: 9
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- name: SDTRx
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description: Sign Deadtime Rising value
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bit_offset: 9
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bit_size: 1
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enum: SDTRx
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- name: DTPRSC
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description: Deadtime Prescaler
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bit_offset: 10
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bit_size: 3
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- name: DTRSLKx
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description: Deadtime Rising Sign Lock
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bit_offset: 14
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bit_size: 1
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enum: LOCKED
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- name: DTRLKx
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description: Deadtime Rising Lock
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bit_offset: 15
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bit_size: 1
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enum: LOCKED
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- name: DTFx
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description: Deadtime Falling value
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bit_offset: 16
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bit_size: 9
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- name: SDTFx
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description: "Sign Deadtime Falling value"
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bit_offset: 25
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bit_size: 1
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enum: SDTFx
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- name: DTFSLKx
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description: Deadtime Falling Sign Lock
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bit_offset: 30
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bit_size: 1
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enum: LOCKED
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- name: DTFLKx
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description: Deadtime Falling Lock
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bit_offset: 31
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bit_size: 1
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enum: LOCKED
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fieldset/EEFXRX:
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description: "Timerx External Event Filtering Register 1"
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fields:
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- name: EEXLTCH
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description: External Event X latch
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bit_offset: 0
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bit_size: 1
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array:
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len: 5
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stride: 6
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- name: EEXFLTR
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description: External Event 1 filter
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bit_offset: 1
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bit_size: 4
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enum: EEXFLTR
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array:
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len: 5
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stride: 6
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fieldset/FLTXR:
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description: Timerx Fault Register
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fields:
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- name: FLT1EN
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description: Fault 1 enable
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bit_offset: 0
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bit_size: 1
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enum: FLT1EN
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- name: FLT2EN
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description: Fault 2 enable
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bit_offset: 1
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bit_size: 1
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enum: FLT1EN
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- name: FLT3EN
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description: Fault 3 enable
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bit_offset: 2
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bit_size: 1
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enum: FLT1EN
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- name: FLT4EN
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description: Fault 4 enable
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bit_offset: 3
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bit_size: 1
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enum: FLT1EN
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- name: FLT5EN
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description: Fault 5 enable
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bit_offset: 4
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bit_size: 1
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enum: FLT1EN
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- name: FLTLCK
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description: Fault sources Lock
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bit_offset: 31
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bit_size: 1
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enum: LOCKED
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fieldset/MCMP1R:
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description: "Master Timer Compare 1 Register"
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fields:
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- name: MCMP1
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description: "Master Timer Compare 1 value"
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bit_offset: 0
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bit_size: 16
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fieldset/MCMP2R:
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description: "Master Timer Compare 2 Register"
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fields:
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- name: MCMP2
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description: "Master Timer Compare 2 value"
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bit_offset: 0
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bit_size: 16
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fieldset/MCMP3R:
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description: "Master Timer Compare 3 Register"
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fields:
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- name: MCMP3
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description: "Master Timer Compare 3 value"
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bit_offset: 0
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bit_size: 16
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fieldset/MCMP4R:
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description: "Master Timer Compare 4 Register"
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fields:
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- name: MCMP4
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description: "Master Timer Compare 4 value"
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bit_offset: 0
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bit_size: 16
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fieldset/MCNTR:
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description: Master Timer Counter Register
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fields:
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- name: MCNT
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description: Counter value
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bit_offset: 0
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bit_size: 16
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fieldset/MCR:
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description: Master Timer Control Register
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fields:
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- name: CKPSC
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description: "HRTIM Master Clock prescaler"
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bit_offset: 0
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bit_size: 3
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- name: CONT
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description: Master Continuous mode
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bit_offset: 3
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bit_size: 1
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enum: CONT
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- name: RETRIG
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description: Master Re-triggerable mode
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bit_offset: 4
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bit_size: 1
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- name: HALF
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description: Half mode enable
|
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bit_offset: 5
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bit_size: 1
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- name: SYNCIN
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description: ynchronization input
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bit_offset: 8
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bit_size: 2
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enum: SYNCIN
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- name: SYNCRSTM
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description: "Synchronization Resets Master"
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bit_offset: 10
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bit_size: 1
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- name: SYNCSTRTM
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description: "Synchronization Starts Master"
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bit_offset: 11
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bit_size: 1
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- name: SYNCOUT
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description: Synchronization output
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bit_offset: 12
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bit_size: 2
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enum: SYNCOUT
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- name: SYNCSRC
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description: Synchronization source
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bit_offset: 14
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bit_size: 2
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enum: SYNCSRC
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|
- name: MCEN
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description: Master Counter enable
|
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bit_offset: 16
|
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bit_size: 1
|
|
- name: TACEN
|
|
description: Timer A counter enable
|
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bit_offset: 17
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|
bit_size: 1
|
|
- name: TBCEN
|
|
description: Timer B counter enable
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: TCCEN
|
|
description: Timer C counter enable
|
|
bit_offset: 19
|
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bit_size: 1
|
|
- name: TDCEN
|
|
description: Timer D counter enable
|
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bit_offset: 20
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bit_size: 1
|
|
- name: TECEN
|
|
description: Timer E counter enable
|
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bit_offset: 21
|
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bit_size: 1
|
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- name: DACSYNC
|
|
description: AC Synchronization
|
|
bit_offset: 25
|
|
bit_size: 2
|
|
enum: DACSYNC
|
|
- name: PREEN
|
|
description: Preload enable
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: MREPU
|
|
description: "Master Timer Repetition update"
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: BRSTDMA
|
|
description: Burst DMA Update
|
|
bit_offset: 30
|
|
bit_size: 2
|
|
enum: BRSTDMA
|
|
fieldset/MDIER:
|
|
description: MDIER4
|
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fields:
|
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- name: MCMP1IE
|
|
description: MCMP1IE
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: MCMP2IE
|
|
description: MCMP2IE
|
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bit_offset: 1
|
|
bit_size: 1
|
|
- name: MCMP3IE
|
|
description: MCMP3IE
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: MCMP4IE
|
|
description: MCMP4IE
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: MREPIE
|
|
description: MREPIE
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: SYNCIE
|
|
description: SYNCIE
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: MUPDIE
|
|
description: MUPDIE
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: MCMP1DE
|
|
description: MCMP1DE
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: MCMP2DE
|
|
description: MCMP2DE
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: MCMP3DE
|
|
description: MCMP3DE
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: MCMP4DE
|
|
description: MCMP4DE
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: MREPDE
|
|
description: MREPDE
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: SYNCDE
|
|
description: SYNCDE
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: MUPDDE
|
|
description: MUPDDE
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
fieldset/MICR:
|
|
description: "Master Timer Interrupt Clear Register"
|
|
fields:
|
|
- name: MCMP1C
|
|
description: "Master Compare 1 Interrupt flag clear"
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum_write: MCMP1C
|
|
- name: MCMP2C
|
|
description: "Master Compare 2 Interrupt flag clear"
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum_write: MCMP1C
|
|
- name: MCMP3C
|
|
description: "Master Compare 3 Interrupt flag clear"
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum_write: MCMP1C
|
|
- name: MCMP4C
|
|
description: "Master Compare 4 Interrupt flag clear"
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum_write: MCMP1C
|
|
- name: MREPC
|
|
description: "Repetition Interrupt flag clear"
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum_write: MCMP1C
|
|
- name: SYNCC
|
|
description: "Sync Input Interrupt flag clear"
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum_write: MCMP1C
|
|
- name: MUPDC
|
|
description: "Master update Interrupt flag clear"
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum_write: MCMP1C
|
|
fieldset/MISR:
|
|
description: "Master Timer Interrupt Status Register"
|
|
fields:
|
|
- name: MCMP1
|
|
description: "Master Compare 1 Interrupt Flag"
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: MCMP2
|
|
description: "Master Compare 2 Interrupt Flag"
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: MCMP3
|
|
description: "Master Compare 3 Interrupt Flag"
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: MCMP4
|
|
description: "Master Compare 4 Interrupt Flag"
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: MREP
|
|
description: "Master Repetition Interrupt Flag"
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: SYNC
|
|
description: Sync Input Interrupt Flag
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: MUPD
|
|
description: "Master Update Interrupt Flag"
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
fieldset/MPER:
|
|
description: Master Timer Period Register
|
|
fields:
|
|
- name: MPER
|
|
description: Master Timer Period value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/MREP:
|
|
description: "Master Timer Repetition Register"
|
|
fields:
|
|
- name: MREP
|
|
description: "Master Timer Repetition counter value"
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
fieldset/OUTXR:
|
|
description: Timerx Output Register
|
|
fields:
|
|
- name: POLX
|
|
description: Output 1 polarity
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: POL
|
|
array:
|
|
offsets:
|
|
- 0
|
|
- 16
|
|
- name: IDLEMX
|
|
description: Output X Idle mode
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: IDLEM
|
|
array:
|
|
offsets:
|
|
- 0
|
|
- 16
|
|
- name: IDLESX
|
|
description: Output 1 Idle State
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: IDLES
|
|
array:
|
|
offsets:
|
|
- 0
|
|
- 16
|
|
- name: FAULTX
|
|
description: Output X Fault state
|
|
bit_offset: 4
|
|
bit_size: 2
|
|
enum: FAULT
|
|
array:
|
|
offsets:
|
|
- 0
|
|
- 16
|
|
- name: CHPX
|
|
description: Output X Chopper enable
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
array:
|
|
offsets:
|
|
- 0
|
|
- 16
|
|
- name: DIDLX
|
|
description: "Output X Deadtime upon burst mode Idle entry"
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
array:
|
|
offsets:
|
|
- 0
|
|
- 16
|
|
- name: DTEN
|
|
description: Deadtime enable
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: DLYPRTEN
|
|
description: Delayed Protection Enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: DLYPRT
|
|
description: Delayed Protection
|
|
bit_offset: 10
|
|
bit_size: 3
|
|
enum: DLYPRT
|
|
fieldset/PERXR:
|
|
description: Timerx Period Register
|
|
fields:
|
|
- name: PERx
|
|
description: Timerx Period value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/REPXR:
|
|
description: Timerx Repetition Register
|
|
fields:
|
|
- name: REPx
|
|
description: "Timerx Repetition counter value"
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
fieldset/RSTXXR:
|
|
description: Timerx OutputX Reset Register
|
|
fields:
|
|
- name: SRT
|
|
description: SRT
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: INACTIVEEFFECT
|
|
- name: RESYNC
|
|
description: RESYNC
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: INACTIVEEFFECT
|
|
- name: PER
|
|
description: PER
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: INACTIVEEFFECT
|
|
- name: CMPX
|
|
description: CMPX
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: INACTIVEEFFECT
|
|
array:
|
|
len: 4
|
|
stride: 1
|
|
- name: MSTPER
|
|
description: MSTPER
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: INACTIVEEFFECT
|
|
- name: MSTCMPX
|
|
description: MSTCMPX
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: INACTIVEEFFECT
|
|
array:
|
|
len: 4
|
|
stride: 1
|
|
- name: TIMEVNTX
|
|
description: TIMEVNTX
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: INACTIVEEFFECT
|
|
array:
|
|
len: 9
|
|
stride: 1
|
|
- name: EXTEVNTX
|
|
description: EXTEVNTX
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: INACTIVEEFFECT
|
|
array:
|
|
len: 10
|
|
stride: 1
|
|
- name: UPDATE
|
|
description: UPDATE
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: INACTIVEEFFECT
|
|
fieldset/RSTXR:
|
|
description: Timerx Reset Register
|
|
fields:
|
|
- name: UPDT
|
|
description: Timer X Update reset
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: RESETEFFECT
|
|
- name: CMPX
|
|
description: Timer X compare X reset
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: RESETEFFECT
|
|
array:
|
|
len: 2
|
|
stride: 1
|
|
- name: MSTPER
|
|
description: Master timer Period
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: RESETEFFECT
|
|
- name: MSTCMPX
|
|
description: Master compare X
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: RESETEFFECT
|
|
array:
|
|
len: 4
|
|
stride: 1
|
|
- name: EXTEVNTX
|
|
description: External Event X
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: RESETEFFECT
|
|
array:
|
|
len: 10
|
|
stride: 1
|
|
- name: TIMXCMPX
|
|
description: Timer X Compare [1, 2, 4]
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: RESETEFFECT
|
|
array:
|
|
len: 3
|
|
stride: 1
|
|
- name: TIMYCMPX
|
|
description: Timer Y Compare [1, 2, 4]
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: RESETEFFECT
|
|
array:
|
|
len: 3
|
|
stride: 1
|
|
- name: TIMZCMPX
|
|
description: Timer Compare [1, 2, 4]
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: RESETEFFECT
|
|
array:
|
|
len: 3
|
|
stride: 1
|
|
- name: TIMTCMPX
|
|
description: Timer Compare [1, 2, 4]
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: RESETEFFECT
|
|
array:
|
|
len: 3
|
|
stride: 1
|
|
fieldset/SETXXR:
|
|
description: Timerx OutputX Set Register
|
|
fields:
|
|
- name: SST
|
|
description: Software Set trigger
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: ACTIVEEFFECT
|
|
- name: RESYNC
|
|
description: Timer X resynchronizaton
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: ACTIVEEFFECT
|
|
- name: PER
|
|
description: Timer X Period
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: ACTIVEEFFECT
|
|
- name: CMPX
|
|
description: Timer X compare X
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: ACTIVEEFFECT
|
|
array:
|
|
len: 4
|
|
stride: 1
|
|
- name: MSTPER
|
|
description: Master Period
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: ACTIVEEFFECT
|
|
- name: MSTCMPX
|
|
description: Master Compare X
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: ACTIVEEFFECT
|
|
array:
|
|
len: 4
|
|
stride: 1
|
|
- name: TIMEVNTX
|
|
description: Timer Event X
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: ACTIVEEFFECT
|
|
array:
|
|
len: 9
|
|
stride: 1
|
|
- name: EXTEVNTX
|
|
description: External Event X
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: ACTIVEEFFECT
|
|
array:
|
|
len: 10
|
|
stride: 1
|
|
- name: UPDATE
|
|
description: "Registers update (transfer preload to active)"
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: ACTIVEEFFECT
|
|
fieldset/TIMXCR:
|
|
description: Timerx Control Register
|
|
fields:
|
|
- name: CKPSCx
|
|
description: "HRTIM Timer x Clock prescaler"
|
|
bit_offset: 0
|
|
bit_size: 3
|
|
- name: CONT
|
|
description: Continuous mode
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: CONT
|
|
- name: RETRIG
|
|
description: Re-triggerable mode
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: HALF
|
|
description: Half mode enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: PSHPLL
|
|
description: Push-Pull mode enable
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: SYNCRSTx
|
|
description: "Synchronization Resets Timer x"
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: SYNCRSTx
|
|
- name: SYNCSTRTx
|
|
description: "Synchronization Starts Timer x"
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: SYNCSTRTx
|
|
- name: DELCMP2
|
|
description: Delayed CMP2 mode
|
|
bit_offset: 12
|
|
bit_size: 2
|
|
enum: DELCMP2
|
|
- name: DELCMP4
|
|
description: Delayed CMP4 mode
|
|
bit_offset: 14
|
|
bit_size: 2
|
|
enum: DELCMP4
|
|
- name: TxREPU
|
|
description: Timer x Repetition update
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TxRSTU
|
|
description: Timerx reset update
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: TBU
|
|
description: TBU
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: TCU
|
|
description: TCU
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: TDU
|
|
description: TDU
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: TEU
|
|
description: TEU
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: MSTU
|
|
description: Master Timer update
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: DACSYNC
|
|
description: AC Synchronization
|
|
bit_offset: 25
|
|
bit_size: 2
|
|
enum: DACSYNC
|
|
- name: PREEN
|
|
description: Preload enable
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: UPDGAT
|
|
description: Update Gating
|
|
bit_offset: 28
|
|
bit_size: 4
|
|
enum: UPDGAT
|
|
fieldset/TIMXDIER:
|
|
description: Timerx DMA / Interrupt Enable Register
|
|
fields:
|
|
- name: CMP1IE
|
|
description: CMP1IE
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: CMP2IE
|
|
description: CMP2IE
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: CMP3IE
|
|
description: CMP3IE
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: CMP4IE
|
|
description: CMP4IE
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: REPIE
|
|
description: REPIE
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: UPDIE
|
|
description: UPDIE
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: CPT1IE
|
|
description: CPT1IE
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: CPT2IE
|
|
description: CPT2IE
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: SETx1IE
|
|
description: SET1xIE
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: RSTx1IE
|
|
description: RSTx1IE
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: SETx2IE
|
|
description: SETx2IE
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: RSTx2IE
|
|
description: RSTx2IE
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: RSTIE
|
|
description: RSTIE
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: DLYPRTIE
|
|
description: DLYPRTIE
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: CMP1DE
|
|
description: CMP1DE
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: CMP2DE
|
|
description: CMP2DE
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: CMP3DE
|
|
description: CMP3DE
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: CMP4DE
|
|
description: CMP4DE
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: REPDE
|
|
description: REPDE
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: UPDDE
|
|
description: UPDDE
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: CPT1DE
|
|
description: CPT1DE
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: CPT2DE
|
|
description: CPT2DE
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: SETx1DE
|
|
description: SET1xDE
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: RSTx1DE
|
|
description: RSTx1DE
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: SETx2DE
|
|
description: SETx2DE
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: RSTx2DE
|
|
description: RSTx2DE
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: RSTDE
|
|
description: RSTDE
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: DLYPRTDE
|
|
description: DLYPRTDE
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
fieldset/TIMXICR:
|
|
description: "Timerx Interrupt Clear Register"
|
|
fields:
|
|
- name: CMP1C
|
|
description: "Compare 1 Interrupt flag Clear"
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CMP2C
|
|
description: "Compare 2 Interrupt flag Clear"
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CMP3C
|
|
description: "Compare 3 Interrupt flag Clear"
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CMP4C
|
|
description: "Compare 4 Interrupt flag Clear"
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: REPC
|
|
description: "Repetition Interrupt flag Clear"
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: UPDC
|
|
description: "Update Interrupt flag Clear"
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CPT1C
|
|
description: "Capture1 Interrupt flag Clear"
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CPT2C
|
|
description: "Capture2 Interrupt flag Clear"
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: SET1xC
|
|
description: Output 1 Set flag Clear
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: RSTx1C
|
|
description: Output 1 Reset flag Clear
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: SET2xC
|
|
description: Output 2 Set flag Clear
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: RSTx2C
|
|
description: Output 2 Reset flag Clear
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: RSTC
|
|
description: Reset Interrupt flag Clear
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: DLYPRTC
|
|
description: "Delayed Protection Flag Clear"
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
fieldset/TIMXISR:
|
|
description: "Timerx Interrupt Status Register"
|
|
fields:
|
|
- name: CMP1
|
|
description: Compare 1 Interrupt Flag
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CMP2
|
|
description: Compare 2 Interrupt Flag
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CMP3
|
|
description: Compare 3 Interrupt Flag
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CMP4
|
|
description: Compare 4 Interrupt Flag
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: REP
|
|
description: Repetition Interrupt Flag
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: UPD
|
|
description: Update Interrupt Flag
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CPT1
|
|
description: Capture1 Interrupt Flag
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CPT2
|
|
description: Capture2 Interrupt Flag
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: SETx1
|
|
description: "Output 1 Set Interrupt Flag"
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: RSTx1
|
|
description: "Output 1 Reset Interrupt Flag"
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: SETx2
|
|
description: "Output 2 Set Interrupt Flag"
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: RSTx2
|
|
description: "Output 2 Reset Interrupt Flag"
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: RST
|
|
description: Reset Interrupt Flag
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: DLYPRT
|
|
description: Delayed Protection Flag
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum_read: TIMAISR_DLYPRT
|
|
- name: CPPSTAT
|
|
description: Current Push Pull Status
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum_read: CPPSTAT
|
|
- name: IPPSTAT
|
|
description: Idle Push Pull Status
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum_read: IPPSTAT
|
|
- name: O1STAT
|
|
description: Output 1 State
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum_read: OUTPUTSTATE
|
|
- name: O2STAT
|
|
description: Output 2 State
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum_read: OUTPUTSTATE
|
|
- name: O1CPY
|
|
description: Output 1 Copy
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum_read: OUTPUTSTATE
|
|
- name: O2CPY
|
|
description: Output 2 Copy
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum_read: OUTPUTSTATE
|
|
enum/ACTIVEEFFECT:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer event forces the output to its active state
|
|
value: 1
|
|
enum/BRSTDMA:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Independent
|
|
description: Update done independently from the DMA burst transfer completion
|
|
value: 0
|
|
- name: Completion
|
|
description: Update done when the DMA burst transfer is completed
|
|
value: 1
|
|
- name: Rollover
|
|
description: Update done on master timer roll-over following a DMA burst transfer completion
|
|
value: 2
|
|
enum/CAPTUREEFFECT:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer event has no effect
|
|
value: 0
|
|
- name: TriggerCapture
|
|
description: Timer event triggers capture
|
|
value: 1
|
|
enum/CMP1C:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Clear
|
|
description: Clears associated flag in ISR register
|
|
value: 1
|
|
enum/CONT:
|
|
bit_size: 1
|
|
variants:
|
|
- name: SingleShot
|
|
description: The timer operates in single-shot mode and stops when it reaches the MPER value
|
|
value: 0
|
|
- name: Continuous
|
|
description: The timer operates in continuous (free-running) mode and rolls over to zero when it reaches the MPER value
|
|
value: 1
|
|
enum/CPPSTAT:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Output1Active
|
|
description: Signal applied on output 1 and output 2 forced inactive
|
|
value: 0
|
|
- name: Output2Active
|
|
description: Signal applied on output 2 and output 1 forced inactive
|
|
value: 1
|
|
enum/DACSYNC:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Disabled
|
|
description: No DAC trigger generated
|
|
value: 0
|
|
- name: DACSync1
|
|
description: Trigger generated on DACSync1
|
|
value: 1
|
|
- name: DACSync2
|
|
description: Trigger generated on DACSync2
|
|
value: 2
|
|
- name: DACSync3
|
|
description: Trigger generated on DACSync3
|
|
value: 3
|
|
enum/DELCMP2:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Standard
|
|
description: CMP2 register is always active (standard compare mode)
|
|
value: 0
|
|
- name: Capture1
|
|
description: CMP2 is recomputed and is active following a capture 1 event
|
|
value: 1
|
|
- name: Capture1_Compare1
|
|
description: CMP2 is recomputed and is active following a capture 1 event or a Compare 1 match
|
|
value: 2
|
|
- name: Capture1_Compare3
|
|
description: CMP2 is recomputed and is active following a capture 1 event or a Compare 3 match
|
|
value: 3
|
|
enum/DELCMP4:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Standard
|
|
description: CMP4 register is always active (standard compare mode)
|
|
value: 0
|
|
- name: Capture2
|
|
description: CMP4 is recomputed and is active following a capture 2 event
|
|
value: 1
|
|
- name: Capture2_Compare1
|
|
description: CMP4 is recomputed and is active following a capture 2 event or a Compare 1 match
|
|
value: 2
|
|
- name: Capture_Compare3
|
|
description: CMP4 is recomputed and is active following a capture event or a Compare 3 match
|
|
value: 3
|
|
enum/EEXFLTR:
|
|
bit_size: 4
|
|
variants:
|
|
- name: Disabled
|
|
description: No filtering
|
|
value: 0
|
|
- name: BlankResetToCompare1
|
|
description: Blanking from counter reset/roll-over to Compare 1
|
|
value: 1
|
|
- name: BlankResetToCompare2
|
|
description: Blanking from counter reset/roll-over to Compare 2
|
|
value: 2
|
|
- name: BlankResetToCompare3
|
|
description: Blanking from counter reset/roll-over to Compare 3
|
|
value: 3
|
|
- name: BlankResetToCompare4
|
|
description: Blanking from counter reset/roll-over to Compare 4
|
|
value: 4
|
|
- name: BlankTIMFLTR1
|
|
description: "Blanking from another timing unit: TIMFLTR1 source"
|
|
value: 5
|
|
- name: BlankTIMFLTR2
|
|
description: "Blanking from another timing unit: TIMFLTR2 source"
|
|
value: 6
|
|
- name: BlankTIMFLTR3
|
|
description: "Blanking from another timing unit: TIMFLTR3 source"
|
|
value: 7
|
|
- name: BlankTIMFLTR4
|
|
description: "Blanking from another timing unit: TIMFLTR4 source"
|
|
value: 8
|
|
- name: BlankTIMFLTR5
|
|
description: "Blanking from another timing unit: TIMFLTR5 source"
|
|
value: 9
|
|
- name: BlankTIMFLTR6
|
|
description: "Blanking from another timing unit: TIMFLTR6 source"
|
|
value: 10
|
|
- name: BlankTIMFLTR7
|
|
description: "Blanking from another timing unit: TIMFLTR7 source"
|
|
value: 11
|
|
- name: BlankTIMFLTR8
|
|
description: "Blanking from another timing unit: TIMFLTR8 source"
|
|
value: 12
|
|
- name: WindowResetToCompare2
|
|
description: Windowing from counter reset/roll-over to compare 2
|
|
value: 13
|
|
- name: WindowResetToCompare3
|
|
description: Windowing from counter reset/roll-over to compare 3
|
|
value: 14
|
|
- name: WindowTIMWIN
|
|
description: "Windowing from another timing unit: TIMWIN source"
|
|
value: 15
|
|
enum/EVENT:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEvent
|
|
description: No compare interrupt occurred
|
|
value: 0
|
|
- name: Event
|
|
description: Compare interrupt occurred
|
|
value: 1
|
|
enum/FAULT:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Disabled
|
|
description: "No action: the output is not affected by the fault input and stays in run mode"
|
|
value: 0
|
|
- name: SetActive
|
|
description: Output goes to active state after a fault event
|
|
value: 1
|
|
- name: SetInactive
|
|
description: Output goes to inactive state after a fault event
|
|
value: 2
|
|
- name: SetHighZ
|
|
description: Output goes to high-z state after a fault event
|
|
value: 3
|
|
enum/FLT1EN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Ignored
|
|
description: Fault input ignored
|
|
value: 0
|
|
- name: Active
|
|
description: Fault input is active and can disable HRTIM outputs
|
|
value: 1
|
|
enum/IDLEM:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: "No action: the output is not affected by the burst mode operation"
|
|
value: 0
|
|
- name: SetIdle
|
|
description: The output is in idle state when requested by the burst mode controller
|
|
value: 1
|
|
enum/IDLES:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Inactive
|
|
description: Output idle state is inactive
|
|
value: 0
|
|
- name: Active
|
|
description: Output idle state is active
|
|
value: 1
|
|
enum/INACTIVEEFFECT:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer event has no effect
|
|
value: 0
|
|
- name: SetInactive
|
|
description: Timer event forces the output to its inactive state
|
|
value: 1
|
|
enum/IPPSTAT:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Output1Active
|
|
description: Protection occurred when the output 1 was active and output 2 forced inactive
|
|
value: 0
|
|
- name: Output2Active
|
|
description: Protection occurred when the output 2 was active and output 1 forced inactive
|
|
value: 1
|
|
enum/LOCKED:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Unlocked
|
|
description: Bits are writeable
|
|
value: 0
|
|
- name: Locked
|
|
description: Bits are read-only
|
|
value: 1
|
|
enum/MCMP1C:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Clear
|
|
description: Clears flag in MISR register
|
|
value: 1
|
|
enum/DLYPRT:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Output1_EE6
|
|
description: Output 1 delayed idle on external event 6
|
|
value: 0
|
|
- name: Output2_EE6
|
|
description: Output 2 delayed idle on external event 6
|
|
value: 1
|
|
- name: Output1_2_EE6
|
|
description: Output 1 and 2 delayed idle on external event 6
|
|
value: 2
|
|
- name: Balanced_EE6
|
|
description: Balanced idle on external event 6
|
|
value: 3
|
|
- name: Output1_EE7
|
|
description: Output 1 delayed idle on external event 7
|
|
value: 4
|
|
- name: Output2_EE7
|
|
description: Output 2 delayed idle on external event 7
|
|
value: 5
|
|
- name: Output1_2_EE7
|
|
description: Output 1 and 2 delayed idle on external event 7
|
|
value: 6
|
|
- name: Balanced_EE7
|
|
description: Balanced idle on external event 7
|
|
value: 7
|
|
enum/OUTPUTSTATE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Inactive
|
|
description: Output is or was inactive
|
|
value: 0
|
|
- name: Active
|
|
description: Output is or was active
|
|
value: 1
|
|
enum/POL:
|
|
bit_size: 1
|
|
variants:
|
|
- name: ActiveHigh
|
|
description: Positive polarity (output active high)
|
|
value: 0
|
|
- name: ActiveLow
|
|
description: Negative polarity (output active low)
|
|
value: 1
|
|
enum/RESETEFFECT:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer Y compare Z event has no effect
|
|
value: 0
|
|
- name: ResetCounter
|
|
description: Timer X counter is reset upon timer Y compare Z event
|
|
value: 1
|
|
enum/SDTFx:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Positive
|
|
description: Positive deadtime on falling edge
|
|
value: 0
|
|
- name: Negative
|
|
description: Negative deadtime on falling edge
|
|
value: 1
|
|
enum/SDTRx:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Positive
|
|
description: Positive deadtime on rising edge
|
|
value: 0
|
|
- name: Negative
|
|
description: Negative deadtime on rising edge
|
|
value: 1
|
|
enum/SYNCIN:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Disabled
|
|
description: Disabled. HRTIM is not synchronized and runs in standalone mode
|
|
value: 0
|
|
- name: Internal
|
|
description: "Internal event: the HRTIM is synchronized with the on-chip timer"
|
|
value: 2
|
|
- name: External
|
|
description: "External event: a positive pulse on HRTIM_SCIN input triggers the HRTIM"
|
|
value: 3
|
|
enum/SYNCOUT:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Disabled
|
|
description: Disabled
|
|
value: 0
|
|
- name: PositivePulse
|
|
description: Positive pulse on SCOUT output (16x f_HRTIM clock cycles)
|
|
value: 2
|
|
- name: NegativePulse
|
|
description: Negative pulse on SCOUT output (16x f_HRTIM clock cycles)
|
|
value: 3
|
|
enum/SYNCRSTx:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Synchronization event has no effect on Timer x
|
|
value: 0
|
|
- name: Reset
|
|
description: Synchronization event resets Timer x
|
|
value: 1
|
|
enum/SYNCSRC:
|
|
bit_size: 2
|
|
variants:
|
|
- name: MasterStart
|
|
description: Master timer Start
|
|
value: 0
|
|
- name: MasterCompare1
|
|
description: Master timer Compare 1 event
|
|
value: 1
|
|
- name: TimerAStart
|
|
description: Timer A start/reset
|
|
value: 2
|
|
- name: TimerACompare1
|
|
description: Timer A Compare 1 event
|
|
value: 3
|
|
enum/SYNCSTRTx:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Synchronization event has no effect on Timer x
|
|
value: 0
|
|
- name: Start
|
|
description: Synchronization event starts Timer x
|
|
value: 1
|
|
enum/TIMAISR_DLYPRT:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Inactive
|
|
description: Not in delayed idle or balanced idle mode
|
|
value: 0
|
|
- name: Active
|
|
description: Delayed idle or balanced idle mode entry
|
|
value: 1
|
|
enum/UPDGAT:
|
|
bit_size: 4
|
|
variants:
|
|
- name: Independent
|
|
description: Update occurs independently from the DMA burst transfer
|
|
value: 0
|
|
- name: DMABurst
|
|
description: Update occurs when the DMA burst transfer is completed
|
|
value: 1
|
|
- name: DMABurst_Update
|
|
description: Update occurs on the update event following DMA burst transfer completion
|
|
value: 2
|
|
- name: Input1
|
|
description: Update occurs on a rising edge of HRTIM update enable input 1
|
|
value: 3
|
|
- name: Input2
|
|
description: Update occurs on a rising edge of HRTIM update enable input 2
|
|
value: 4
|
|
- name: Input3
|
|
description: Update occurs on a rising edge of HRTIM update enable input 3
|
|
value: 5
|
|
- name: Input1_Update
|
|
description: Update occurs on the update event following a rising edge of HRTIM update enable input 1
|
|
value: 6
|
|
- name: Input2_Update
|
|
description: Update occurs on the update event following a rising edge of HRTIM update enable input 2
|
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value: 7
|
|
- name: Input3_Update
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description: Update occurs on the update event following a rising edge of HRTIM update enable input 3
|
|
value: 8
|