1638 lines
41 KiB
YAML
1638 lines
41 KiB
YAML
block/RCC:
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description: Reset and clock control
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items:
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- name: CR
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description: Clock control register
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byte_offset: 0
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fieldset: CR
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- name: ICSCR
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description: Internal clock sources calibration register
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byte_offset: 4
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fieldset: ICSCR
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- name: CFGR
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description: Clock configuration register
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byte_offset: 8
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fieldset: CFGR
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- name: PLLCFGR
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description: PLLSYS configuration register
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byte_offset: 12
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fieldset: PLLCFGR
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- name: PLLSAI1CFGR
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description: PLLSAI1 configuration register
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byte_offset: 16
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fieldset: PLLSAI1CFGR
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- name: CIER
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description: Clock interrupt enable register
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byte_offset: 24
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fieldset: CIER
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- name: CIFR
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description: Clock interrupt flag register
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byte_offset: 28
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access: Read
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fieldset: CIFR
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- name: CICR
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description: Clock interrupt clear register
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byte_offset: 32
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access: Write
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fieldset: CICR
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- name: SMPSCR
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description: Step Down converter control register
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byte_offset: 36
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fieldset: SMPSCR
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- name: AHB1RSTR
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description: AHB1 peripheral reset register
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byte_offset: 40
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fieldset: AHB1RSTR
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- name: AHB2RSTR
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description: AHB2 peripheral reset register
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byte_offset: 44
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fieldset: AHB2RSTR
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- name: AHB3RSTR
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description: AHB3 peripheral reset register
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byte_offset: 48
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fieldset: AHB3RSTR
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- name: APB1RSTR1
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description: APB1 peripheral reset register 1
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byte_offset: 56
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fieldset: APB1RSTR1
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- name: APB1RSTR2
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description: APB1 peripheral reset register 2
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byte_offset: 60
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fieldset: APB1RSTR2
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- name: APB2RSTR
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description: APB2 peripheral reset register
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byte_offset: 64
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fieldset: APB2RSTR
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- name: APB3RSTR
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description: APB3 peripheral reset register
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byte_offset: 68
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fieldset: APB3RSTR
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- name: AHB1ENR
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description: AHB1 peripheral clock enable register
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byte_offset: 72
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fieldset: AHB1ENR
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- name: AHB2ENR
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description: AHB2 peripheral clock enable register
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byte_offset: 76
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fieldset: AHB2ENR
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- name: AHB3ENR
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description: AHB3 peripheral clock enable register
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byte_offset: 80
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fieldset: AHB3ENR
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- name: APB1ENR1
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description: APB1ENR1
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byte_offset: 88
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fieldset: APB1ENR1
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- name: APB1ENR2
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description: APB1 peripheral clock enable register 2
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byte_offset: 92
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fieldset: APB1ENR2
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- name: APB2ENR
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description: APB2ENR
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byte_offset: 96
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fieldset: APB2ENR
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- name: AHB1SMENR
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description: AHB1 peripheral clocks enable in Sleep and Stop modes register
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byte_offset: 104
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fieldset: AHB1SMENR
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- name: AHB2SMENR
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description: AHB2 peripheral clocks enable in Sleep and Stop modes register
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byte_offset: 108
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fieldset: AHB2SMENR
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- name: AHB3SMENR
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description: AHB3 peripheral clocks enable in Sleep and Stop modes register
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byte_offset: 112
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fieldset: AHB3SMENR
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- name: APB1SMENR1
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description: APB1SMENR1
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byte_offset: 120
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fieldset: APB1SMENR1
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- name: APB1SMENR2
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description: APB1 peripheral clocks enable in Sleep and Stop modes register 2
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byte_offset: 124
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fieldset: APB1SMENR2
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- name: APB2SMENR
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description: APB2SMENR
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byte_offset: 128
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fieldset: APB2SMENR
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- name: CCIPR
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description: CCIPR
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byte_offset: 136
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fieldset: CCIPR
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- name: BDCR
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description: BDCR
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byte_offset: 144
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fieldset: BDCR
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- name: CSR
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description: CSR
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byte_offset: 148
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fieldset: CSR
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- name: CRRCR
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description: Clock recovery RC register
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byte_offset: 152
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fieldset: CRRCR
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- name: HSECR
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description: Clock HSE register
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byte_offset: 156
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fieldset: HSECR
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- name: EXTCFGR
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description: Extended clock recovery register
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byte_offset: 264
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fieldset: EXTCFGR
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- name: C2AHB1ENR
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description: CPU2 AHB1 peripheral clock enable register
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byte_offset: 328
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fieldset: C2AHB1ENR
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- name: C2AHB2ENR
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description: CPU2 AHB2 peripheral clock enable register
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byte_offset: 332
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fieldset: C2AHB2ENR
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- name: C2AHB3ENR
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description: CPU2 AHB3 peripheral clock enable register
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byte_offset: 336
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fieldset: C2AHB3ENR
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- name: C2APB1ENR1
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description: CPU2 APB1ENR1
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byte_offset: 344
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fieldset: C2APB1ENR1
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- name: C2APB1ENR2
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description: CPU2 APB1 peripheral clock enable register 2
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byte_offset: 348
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fieldset: C2APB1ENR2
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- name: C2APB2ENR
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description: CPU2 APB2ENR
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byte_offset: 352
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fieldset: C2APB2ENR
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- name: C2APB3ENR
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description: CPU2 APB3ENR
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byte_offset: 356
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fieldset: C2APB3ENR
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- name: C2AHB1SMENR
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description: CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register
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byte_offset: 360
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fieldset: C2AHB1SMENR
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- name: C2AHB2SMENR
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description: CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register
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byte_offset: 364
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fieldset: C2AHB2SMENR
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- name: C2AHB3SMENR
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description: CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register
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byte_offset: 368
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fieldset: C2AHB3SMENR
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- name: C2APB1SMENR1
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description: CPU2 APB1SMENR1
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byte_offset: 376
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fieldset: C2APB1SMENR1
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- name: C2APB1SMENR2
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description: CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2
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byte_offset: 380
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fieldset: C2APB1SMENR2
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- name: C2APB2SMENR
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description: CPU2 APB2SMENR
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byte_offset: 384
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fieldset: C2APB2SMENR
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- name: C2APB3SMENR
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description: CPU2 APB3SMENR
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byte_offset: 388
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fieldset: C2APB3SMENR
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fieldset/AHB1ENR:
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description: AHB1 peripheral clock enable register
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fields:
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- name: DMA1EN
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description: DMA1 clock enable
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bit_offset: 0
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bit_size: 1
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- name: DMA2EN
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description: DMA2 clock enable
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bit_offset: 1
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bit_size: 1
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- name: DMAMUX1EN
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description: DMAMUX clock enable
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bit_offset: 2
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bit_size: 1
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- name: CRCEN
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description: CPU1 CRC clock enable
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bit_offset: 12
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bit_size: 1
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- name: TSCEN
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description: Touch Sensing Controller clock enable
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bit_offset: 16
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bit_size: 1
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fieldset/AHB1RSTR:
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description: AHB1 peripheral reset register
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fields:
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- name: DMA1RST
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description: DMA1 reset
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bit_offset: 0
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bit_size: 1
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- name: DMA2RST
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description: DMA2 reset
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bit_offset: 1
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bit_size: 1
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- name: DMAMUX1RST
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description: DMAMUX reset
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bit_offset: 2
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bit_size: 1
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- name: CRCRST
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description: CRC reset
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bit_offset: 12
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bit_size: 1
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- name: TSCRST
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description: Touch Sensing Controller reset
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bit_offset: 16
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bit_size: 1
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fieldset/AHB1SMENR:
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description: AHB1 peripheral clocks enable in Sleep and Stop modes register
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fields:
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- name: DMA1SMEN
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description: CPU1 DMA1 clocks enable during Sleep and Stop modes
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bit_offset: 0
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bit_size: 1
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- name: DMA2SMEN
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description: CPU1 DMA2 clocks enable during Sleep and Stop modes
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bit_offset: 1
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bit_size: 1
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- name: DMAMUX1SMEN
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description: CPU1 DMAMUX clocks enable during Sleep and Stop modes
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bit_offset: 2
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bit_size: 1
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- name: SRAM1SMEN
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description: CPU1 SRAM1 interface clocks enable during Sleep and Stop modes
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bit_offset: 9
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bit_size: 1
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- name: CRCSMEN
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description: CPU1 CRCSMEN
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bit_offset: 12
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bit_size: 1
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- name: TSCSMEN
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description: CPU1 Touch Sensing Controller clocks enable during Sleep and Stop modes
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bit_offset: 16
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bit_size: 1
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fieldset/AHB2ENR:
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description: AHB2 peripheral clock enable register
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fields:
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- name: GPIOAEN
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description: IO port A clock enable
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bit_offset: 0
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bit_size: 1
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- name: GPIOBEN
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description: IO port B clock enable
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bit_offset: 1
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bit_size: 1
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- name: GPIOCEN
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description: IO port C clock enable
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bit_offset: 2
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bit_size: 1
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- name: GPIODEN
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description: IO port D clock enable
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bit_offset: 3
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bit_size: 1
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- name: GPIOEEN
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description: IO port E clock enable
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bit_offset: 4
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bit_size: 1
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- name: GPIOHEN
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description: IO port H clock enable
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bit_offset: 7
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bit_size: 1
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- name: ADCEN
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description: ADC clock enable
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bit_offset: 13
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bit_size: 1
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- name: AES1EN
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description: AES1 accelerator clock enable
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bit_offset: 16
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bit_size: 1
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fieldset/AHB2RSTR:
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description: AHB2 peripheral reset register
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fields:
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- name: GPIOARST
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description: IO port A reset
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bit_offset: 0
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bit_size: 1
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- name: GPIOBRST
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description: IO port B reset
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bit_offset: 1
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bit_size: 1
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- name: GPIOCRST
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description: IO port C reset
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bit_offset: 2
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bit_size: 1
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- name: GPIODRST
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description: IO port D reset
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bit_offset: 3
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bit_size: 1
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- name: GPIOERST
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description: IO port E reset
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bit_offset: 4
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bit_size: 1
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- name: GPIOHRST
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description: IO port H reset
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bit_offset: 7
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bit_size: 1
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- name: ADCRST
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description: ADC reset
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bit_offset: 13
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bit_size: 1
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- name: AES1RST
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description: AES1 hardware accelerator reset
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bit_offset: 16
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bit_size: 1
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fieldset/AHB2SMENR:
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description: AHB2 peripheral clocks enable in Sleep and Stop modes register
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fields:
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- name: GPIOASMEN
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description: CPU1 IO port A clocks enable during Sleep and Stop modes
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bit_offset: 0
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bit_size: 1
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- name: GPIOBSMEN
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description: CPU1 IO port B clocks enable during Sleep and Stop modes
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bit_offset: 1
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bit_size: 1
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- name: GPIOCSMEN
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description: CPU1 IO port C clocks enable during Sleep and Stop modes
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bit_offset: 2
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bit_size: 1
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- name: GPIODSMEN
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description: CPU1 IO port D clocks enable during Sleep and Stop modes
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bit_offset: 3
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bit_size: 1
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- name: GPIOESMEN
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description: CPU1 IO port E clocks enable during Sleep and Stop modes
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bit_offset: 4
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bit_size: 1
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- name: GPIOHSMEN
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description: CPU1 IO port H clocks enable during Sleep and Stop modes
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bit_offset: 7
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bit_size: 1
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- name: ADCFSSMEN
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description: CPU1 ADC clocks enable during Sleep and Stop modes
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bit_offset: 13
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bit_size: 1
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- name: AES1SMEN
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description: CPU1 AES1 accelerator clocks enable during Sleep and Stop modes
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bit_offset: 16
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bit_size: 1
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fieldset/AHB3ENR:
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description: AHB3 peripheral clock enable register
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fields:
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- name: QUADSPIEN
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description: QUADSPIEN
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bit_offset: 8
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bit_size: 1
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- name: PKAEN
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description: PKAEN
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bit_offset: 16
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bit_size: 1
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- name: AES2EN
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description: AES2EN
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bit_offset: 17
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bit_size: 1
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- name: RNGEN
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description: RNGEN
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bit_offset: 18
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bit_size: 1
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- name: HSEMEN
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description: HSEMEN
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bit_offset: 19
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bit_size: 1
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- name: IPCCEN
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description: IPCCEN
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bit_offset: 20
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bit_size: 1
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- name: FLASHEN
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description: FLASHEN
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bit_offset: 25
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bit_size: 1
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fieldset/AHB3RSTR:
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description: AHB3 peripheral reset register
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fields:
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- name: QSPIRST
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description: Quad SPI memory interface reset
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bit_offset: 8
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bit_size: 1
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- name: PKARST
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description: PKA interface reset
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bit_offset: 16
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bit_size: 1
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- name: AES2RST
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description: AES2 interface reset
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bit_offset: 17
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bit_size: 1
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- name: RNGRST
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description: RNG interface reset
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bit_offset: 18
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bit_size: 1
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- name: HSEMRST
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description: HSEM interface reset
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bit_offset: 19
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bit_size: 1
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- name: IPCCRST
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description: IPCC interface reset
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bit_offset: 20
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bit_size: 1
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- name: FLASHRST
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description: Flash interface reset
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bit_offset: 25
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bit_size: 1
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fieldset/AHB3SMENR:
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description: AHB3 peripheral clocks enable in Sleep and Stop modes register
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fields:
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- name: QSPISMEN
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description: QSPISMEN
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bit_offset: 8
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bit_size: 1
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- name: PKASMEN
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description: PKA accelerator clocks enable during CPU1 sleep mode
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bit_offset: 16
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bit_size: 1
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- name: AES2SMEN
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description: AES2 accelerator clocks enable during CPU1 sleep mode
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bit_offset: 17
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bit_size: 1
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- name: RNGSMEN
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description: True RNG clocks enable during CPU1 sleep mode
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bit_offset: 18
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bit_size: 1
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- name: SRAM2SMEN
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description: SRAM2a and SRAM2b memory interface clocks enable during CPU1 sleep mode
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bit_offset: 24
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bit_size: 1
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- name: FLASHSMEN
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description: Flash interface clocks enable during CPU1 sleep mode
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bit_offset: 25
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bit_size: 1
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fieldset/APB1ENR1:
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description: APB1ENR1
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fields:
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- name: TIM2EN
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description: CPU1 TIM2 timer clock enable
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bit_offset: 0
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bit_size: 1
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- name: LCDEN
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description: CPU1 LCD clock enable
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bit_offset: 9
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bit_size: 1
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- name: RTCAPBEN
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description: CPU1 RTC APB clock enable
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bit_offset: 10
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bit_size: 1
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- name: WWDGEN
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description: CPU1 Window watchdog clock enable
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bit_offset: 11
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bit_size: 1
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- name: SPI2EN
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description: CPU1 SPI2 clock enable
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bit_offset: 14
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bit_size: 1
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- name: I2C1EN
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description: CPU1 I2C1 clock enable
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bit_offset: 21
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bit_size: 1
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- name: I2C3EN
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description: CPU1 I2C3 clock enable
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bit_offset: 23
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bit_size: 1
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- name: CRSEN
|
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description: CPU1 CRS clock enable
|
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bit_offset: 24
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bit_size: 1
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- name: USBEN
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description: CPU1 USB clock enable
|
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bit_offset: 26
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bit_size: 1
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- name: LPTIM1EN
|
|
description: CPU1 Low power timer 1 clock enable
|
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bit_offset: 31
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bit_size: 1
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fieldset/APB1ENR2:
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description: APB1 peripheral clock enable register 2
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fields:
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- name: LPUART1EN
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description: CPU1 Low power UART 1 clock enable
|
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bit_offset: 0
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bit_size: 1
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- name: LPTIM2EN
|
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description: CPU1 LPTIM2EN
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bit_offset: 5
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bit_size: 1
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fieldset/APB1RSTR1:
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description: APB1 peripheral reset register 1
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fields:
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- name: TIM2RST
|
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description: TIM2 timer reset
|
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bit_offset: 0
|
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bit_size: 1
|
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- name: LCDRST
|
|
description: LCD interface reset
|
|
bit_offset: 9
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bit_size: 1
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- name: SPI2RST
|
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description: SPI2 reset
|
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bit_offset: 14
|
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bit_size: 1
|
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- name: I2C1RST
|
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description: I2C1 reset
|
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bit_offset: 21
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bit_size: 1
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- name: I2C3RST
|
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description: I2C3 reset
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bit_offset: 23
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bit_size: 1
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- name: CRSRST
|
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description: CRS reset
|
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bit_offset: 24
|
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bit_size: 1
|
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- name: USBRST
|
|
description: USB FS reset
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: LPTIM1RST
|
|
description: Low Power Timer 1 reset
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/APB1RSTR2:
|
|
description: APB1 peripheral reset register 2
|
|
fields:
|
|
- name: LPUART1RST
|
|
description: Low-power UART 1 reset
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LPTIM2RST
|
|
description: Low-power timer 2 reset
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
fieldset/APB1SMENR1:
|
|
description: APB1SMENR1
|
|
fields:
|
|
- name: TIM2SMEN
|
|
description: TIM2 timer clocks enable during CPU1 Sleep mode
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LCDSMEN
|
|
description: LCD clocks enable during CPU1 Sleep mode
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: RTCAPBSMEN
|
|
description: RTC APB clocks enable during CPU1 Sleep mode
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: WWDGSMEN
|
|
description: Window watchdog clocks enable during CPU1 Sleep mode
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI2SMEN
|
|
description: SPI2 clocks enable during CPU1 Sleep mode
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: I2C1SMEN
|
|
description: I2C1 clocks enable during CPU1 Sleep mode
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: I2C3SMEN
|
|
description: I2C3 clocks enable during CPU1 Sleep mode
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: CRSMEN
|
|
description: CRS clocks enable during CPU1 Sleep mode
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: USBSMEN
|
|
description: USB FS clocks enable during CPU1 Sleep mode
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: LPTIM1SMEN
|
|
description: Low power timer 1 clocks enable during CPU1 Sleep mode
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/APB1SMENR2:
|
|
description: APB1 peripheral clocks enable in Sleep and Stop modes register 2
|
|
fields:
|
|
- name: LPUART1SMEN
|
|
description: Low power UART 1 clocks enable during CPU1 Sleep mode
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LPTIM2SMEN
|
|
description: Low power timer 2 clocks enable during CPU1 Sleep mode
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
fieldset/APB2ENR:
|
|
description: APB2ENR
|
|
fields:
|
|
- name: TIM1EN
|
|
description: CPU1 TIM1 timer clock enable
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI1EN
|
|
description: CPU1 SPI1 clock enable
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: USART1EN
|
|
description: CPU1 USART1clock enable
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TIM16EN
|
|
description: CPU1 TIM16 timer clock enable
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM17EN
|
|
description: CPU1 TIM17 timer clock enable
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: SAI1EN
|
|
description: CPU1 SAI1 clock enable
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
fieldset/APB2RSTR:
|
|
description: APB2 peripheral reset register
|
|
fields:
|
|
- name: TIM1RST
|
|
description: TIM1 timer reset
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI1RST
|
|
description: SPI1 reset
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: USART1RST
|
|
description: USART1 reset
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TIM16RST
|
|
description: TIM16 timer reset
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM17RST
|
|
description: TIM17 timer reset
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: SAI1RST
|
|
description: Serial audio interface 1 (SAI1) reset
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
fieldset/APB2SMENR:
|
|
description: APB2SMENR
|
|
fields:
|
|
- name: TIM1SMEN
|
|
description: TIM1 timer clocks enable during CPU1 Sleep mode
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI1SMEN
|
|
description: SPI1 clocks enable during CPU1 Sleep mode
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: USART1SMEN
|
|
description: USART1clocks enable during CPU1 Sleep mode
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TIM16SMEN
|
|
description: TIM16 timer clocks enable during CPU1 Sleep mode
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM17SMEN
|
|
description: TIM17 timer clocks enable during CPU1 Sleep mode
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: SAI1SMEN
|
|
description: SAI1 clocks enable during CPU1 Sleep mode
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
fieldset/APB3RSTR:
|
|
description: APB3 peripheral reset register
|
|
fields:
|
|
- name: RFRST
|
|
description: Radio system BLE reset
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
fieldset/BDCR:
|
|
description: BDCR
|
|
fields:
|
|
- name: LSEON
|
|
description: LSE oscillator enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDY
|
|
description: LSE oscillator ready
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: LSEBYP
|
|
description: LSE oscillator bypass
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: LSEDRV
|
|
description: SE oscillator drive capability
|
|
bit_offset: 3
|
|
bit_size: 2
|
|
- name: LSECSSON
|
|
description: LSECSSON
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: LSECSSD_
|
|
description: CSS on LSE failure detection
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: RTCSEL
|
|
description: RTC clock source selection
|
|
bit_offset: 8
|
|
bit_size: 2
|
|
- name: RTCEN
|
|
description: RTC clock enable
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: BDRST
|
|
description: Backup domain software reset
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: LSCOEN
|
|
description: Low speed clock output enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: LSCOSEL
|
|
description: Low speed clock output selection
|
|
bit_offset: 25
|
|
bit_size: 2
|
|
fieldset/C2AHB1ENR:
|
|
description: CPU2 AHB1 peripheral clock enable register
|
|
fields:
|
|
- name: DMA1EN
|
|
description: CPU2 DMA1 clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: DMA2EN
|
|
description: CPU2 DMA2 clock enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: DMAMUX1EN
|
|
description: CPU2 DMAMUX clock enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: SRAM1EN
|
|
description: CPU2 SRAM1 clock enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: CRCEN
|
|
description: CPU2 CRC clock enable
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: TSCEN
|
|
description: CPU2 Touch Sensing Controller clock enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
fieldset/C2AHB1SMENR:
|
|
description: CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register
|
|
fields:
|
|
- name: DMA1SMEN
|
|
description: CPU2 DMA1 clocks enable during Sleep and Stop modes
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: DMA2SMEN
|
|
description: CPU2 DMA2 clocks enable during Sleep and Stop modes
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: DMAMUX1SMEN
|
|
description: CPU2 DMAMUX clocks enable during Sleep and Stop modes
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: SRAM1SMEN
|
|
description: SRAM1 interface clock enable during CPU1 CSleep mode
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: CRCSMEN
|
|
description: CPU2 CRCSMEN
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: TSCSMEN
|
|
description: CPU2 Touch Sensing Controller clocks enable during Sleep and Stop modes
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
fieldset/C2AHB2ENR:
|
|
description: CPU2 AHB2 peripheral clock enable register
|
|
fields:
|
|
- name: GPIOAEN
|
|
description: CPU2 IO port A clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: GPIOBEN
|
|
description: CPU2 IO port B clock enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: GPIOCEN
|
|
description: CPU2 IO port C clock enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: GPIODEN
|
|
description: CPU2 IO port D clock enable
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: GPIOEEN
|
|
description: CPU2 IO port E clock enable
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: GPIOHEN
|
|
description: CPU2 IO port H clock enable
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: ADCEN
|
|
description: CPU2 ADC clock enable
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: AES1EN
|
|
description: CPU2 AES1 accelerator clock enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
fieldset/C2AHB2SMENR:
|
|
description: CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register
|
|
fields:
|
|
- name: GPIOASMEN
|
|
description: CPU2 IO port A clocks enable during Sleep and Stop modes
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: GPIOBSMEN
|
|
description: CPU2 IO port B clocks enable during Sleep and Stop modes
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: GPIOCSMEN
|
|
description: CPU2 IO port C clocks enable during Sleep and Stop modes
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: GPIODSMEN
|
|
description: CPU2 IO port D clocks enable during Sleep and Stop modes
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: GPIOESMEN
|
|
description: CPU2 IO port E clocks enable during Sleep and Stop modes
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: GPIOHSMEN
|
|
description: CPU2 IO port H clocks enable during Sleep and Stop modes
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: ADCFSSMEN
|
|
description: CPU2 ADC clocks enable during Sleep and Stop modes
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: AES1SMEN
|
|
description: CPU2 AES1 accelerator clocks enable during Sleep and Stop modes
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
fieldset/C2AHB3ENR:
|
|
description: CPU2 AHB3 peripheral clock enable register
|
|
fields:
|
|
- name: PKAEN
|
|
description: CPU2 PKAEN
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: AES2EN
|
|
description: CPU2 AES2EN
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: RNGEN
|
|
description: CPU2 RNGEN
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: HSEMEN
|
|
description: CPU2 HSEMEN
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: IPCCEN
|
|
description: CPU2 IPCCEN
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: FLASHEN
|
|
description: CPU2 FLASHEN
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
fieldset/C2AHB3SMENR:
|
|
description: CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register
|
|
fields:
|
|
- name: PKASMEN
|
|
description: PKA accelerator clocks enable during CPU2 sleep modes
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: AES2SMEN
|
|
description: AES2 accelerator clocks enable during CPU2 sleep modes
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: RNGSMEN
|
|
description: True RNG clocks enable during CPU2 sleep modes
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: SRAM2SMEN
|
|
description: SRAM2a and SRAM2b memory interface clocks enable during CPU2 sleep modes
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: FLASHSMEN
|
|
description: Flash interface clocks enable during CPU2 sleep modes
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
fieldset/C2APB1ENR1:
|
|
description: CPU2 APB1ENR1
|
|
fields:
|
|
- name: TIM2EN
|
|
description: CPU2 TIM2 timer clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LCDEN
|
|
description: CPU2 LCD clock enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: RTCAPBEN
|
|
description: CPU2 RTC APB clock enable
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: SPI2EN
|
|
description: CPU2 SPI2 clock enable
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: I2C1EN
|
|
description: CPU2 I2C1 clock enable
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: I2C3EN
|
|
description: CPU2 I2C3 clock enable
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: CRSEN
|
|
description: CPU2 CRS clock enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: USBEN
|
|
description: CPU2 USB clock enable
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: LPTIM1EN
|
|
description: CPU2 Low power timer 1 clock enable
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/C2APB1ENR2:
|
|
description: CPU2 APB1 peripheral clock enable register 2
|
|
fields:
|
|
- name: LPUART1EN
|
|
description: CPU2 Low power UART 1 clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LPTIM2EN
|
|
description: CPU2 LPTIM2EN
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
fieldset/C2APB1SMENR1:
|
|
description: CPU2 APB1SMENR1
|
|
fields:
|
|
- name: TIM2SMEN
|
|
description: TIM2 timer clocks enable during CPU2 Sleep mode
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LCDSMEN
|
|
description: LCD clocks enable during CPU2 Sleep mode
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: RTCAPBSMEN
|
|
description: RTC APB clocks enable during CPU2 Sleep mode
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: SPI2SMEN
|
|
description: SPI2 clocks enable during CPU2 Sleep mode
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: I2C1SMEN
|
|
description: I2C1 clocks enable during CPU2 Sleep mode
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: I2C3SMEN
|
|
description: I2C3 clocks enable during CPU2 Sleep mode
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: CRSMEN
|
|
description: CRS clocks enable during CPU2 Sleep mode
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: USBSMEN
|
|
description: USB FS clocks enable during CPU2 Sleep mode
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: LPTIM1SMEN
|
|
description: Low power timer 1 clocks enable during CPU2 Sleep mode
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/C2APB1SMENR2:
|
|
description: CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2
|
|
fields:
|
|
- name: LPUART1SMEN
|
|
description: Low power UART 1 clocks enable during CPU2 Sleep mode
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LPTIM2SMEN
|
|
description: Low power timer 2 clocks enable during CPU2 Sleep mode
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
fieldset/C2APB2ENR:
|
|
description: CPU2 APB2ENR
|
|
fields:
|
|
- name: TIM1EN
|
|
description: CPU2 TIM1 timer clock enable
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI1EN
|
|
description: CPU2 SPI1 clock enable
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: USART1EN
|
|
description: CPU2 USART1clock enable
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TIM16EN
|
|
description: CPU2 TIM16 timer clock enable
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM17EN
|
|
description: CPU2 TIM17 timer clock enable
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: SAI1EN
|
|
description: CPU2 SAI1 clock enable
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
fieldset/C2APB2SMENR:
|
|
description: CPU2 APB2SMENR
|
|
fields:
|
|
- name: TIM1SMEN
|
|
description: TIM1 timer clocks enable during CPU2 Sleep mode
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI1SMEN
|
|
description: SPI1 clocks enable during CPU2 Sleep mode
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: USART1SMEN
|
|
description: USART1clocks enable during CPU2 Sleep mode
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TIM16SMEN
|
|
description: TIM16 timer clocks enable during CPU2 Sleep mode
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM17SMEN
|
|
description: TIM17 timer clocks enable during CPU2 Sleep mode
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: SAI1SMEN
|
|
description: SAI1 clocks enable during CPU2 Sleep mode
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
fieldset/C2APB3ENR:
|
|
description: CPU2 APB3ENR
|
|
fields:
|
|
- name: BLEEN
|
|
description: CPU2 BLE interface clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: EN802
|
|
description: CPU2 802.15.4 interface clock enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
fieldset/C2APB3SMENR:
|
|
description: CPU2 APB3SMENR
|
|
fields:
|
|
- name: BLESMEN
|
|
description: BLE interface clocks enable during CPU2 Sleep mode
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: SMEN802
|
|
description: 802.15.4 interface clocks enable during CPU2 Sleep modes
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
fieldset/CCIPR:
|
|
description: CCIPR
|
|
fields:
|
|
- name: USART1SEL
|
|
description: USART1 clock source selection
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: LPUART1SEL
|
|
description: LPUART1 clock source selection
|
|
bit_offset: 10
|
|
bit_size: 2
|
|
- name: I2C1SEL
|
|
description: I2C1 clock source selection
|
|
bit_offset: 12
|
|
bit_size: 2
|
|
- name: I2C3SEL
|
|
description: I2C3 clock source selection
|
|
bit_offset: 16
|
|
bit_size: 2
|
|
- name: LPTIM1SEL
|
|
description: Low power timer 1 clock source selection
|
|
bit_offset: 18
|
|
bit_size: 2
|
|
- name: LPTIM2SEL
|
|
description: Low power timer 2 clock source selection
|
|
bit_offset: 20
|
|
bit_size: 2
|
|
- name: SAI1SEL
|
|
description: SAI1 clock source selection
|
|
bit_offset: 22
|
|
bit_size: 2
|
|
- name: CLK48SEL
|
|
description: 48 MHz clock source selection
|
|
bit_offset: 26
|
|
bit_size: 2
|
|
- name: ADCSEL
|
|
description: ADCs clock source selection
|
|
bit_offset: 28
|
|
bit_size: 2
|
|
- name: RNGSEL
|
|
description: RNG clock source selection
|
|
bit_offset: 30
|
|
bit_size: 2
|
|
fieldset/CFGR:
|
|
description: Clock configuration register
|
|
fields:
|
|
- name: SW
|
|
description: System clock switch
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: SWS
|
|
description: System clock switch status
|
|
bit_offset: 2
|
|
bit_size: 2
|
|
- name: HPRE
|
|
description: AHB prescaler
|
|
bit_offset: 4
|
|
bit_size: 4
|
|
- name: PPRE1
|
|
description: PB low-speed prescaler (APB1)
|
|
bit_offset: 8
|
|
bit_size: 3
|
|
- name: PPRE2
|
|
description: APB high-speed prescaler (APB2)
|
|
bit_offset: 11
|
|
bit_size: 3
|
|
- name: STOPWUCK
|
|
description: Wakeup from Stop and CSS backup clock selection
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: HPREF
|
|
description: AHB prescaler flag
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: PPRE1F
|
|
description: APB1 prescaler flag
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: PPRE2F
|
|
description: APB2 prescaler flag
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: MCOSEL
|
|
description: Microcontroller clock output
|
|
bit_offset: 24
|
|
bit_size: 4
|
|
- name: MCOPRE
|
|
description: Microcontroller clock output prescaler
|
|
bit_offset: 28
|
|
bit_size: 3
|
|
fieldset/CICR:
|
|
description: Clock interrupt clear register
|
|
fields:
|
|
- name: LSI1RDYC
|
|
description: LSI1 ready interrupt clear
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYC
|
|
description: LSE ready interrupt clear
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: MSIRDYC
|
|
description: MSI ready interrupt clear
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSIRDYC
|
|
description: HSI ready interrupt clear
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: HSERDYC
|
|
description: HSE ready interrupt clear
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: PLLRDYC
|
|
description: PLL ready interrupt clear
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: PLLSAI1RDYC
|
|
description: PLLSAI1 ready interrupt clear
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: HSECSSC
|
|
description: HSE Clock security system interrupt clear
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LSECSSC
|
|
description: LSE Clock security system interrupt clear
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HSI48RDYC
|
|
description: HSI48 ready interrupt clear
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: LSI2RDYC
|
|
description: LSI2 ready interrupt clear
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
fieldset/CIER:
|
|
description: Clock interrupt enable register
|
|
fields:
|
|
- name: LSI1RDYIE
|
|
description: LSI1 ready interrupt enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYIE
|
|
description: LSE ready interrupt enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: MSIRDYIE
|
|
description: MSI ready interrupt enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSIRDYIE
|
|
description: HSI ready interrupt enable
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: HSERDYIE
|
|
description: HSE ready interrupt enable
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: PLLRDYIE
|
|
description: PLLSYS ready interrupt enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: PLLSAI1RDYIE
|
|
description: PLLSAI1 ready interrupt enable
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: LSECSSIE
|
|
description: LSE clock security system interrupt enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HSI48RDYIE
|
|
description: HSI48 ready interrupt enable
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: LSI2RDYIE
|
|
description: LSI2 ready interrupt enable
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
fieldset/CIFR:
|
|
description: Clock interrupt flag register
|
|
fields:
|
|
- name: LSI1RDYF
|
|
description: LSI1 ready interrupt flag
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYF
|
|
description: LSE ready interrupt flag
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: MSIRDYF
|
|
description: MSI ready interrupt flag
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSIRDYF
|
|
description: HSI ready interrupt flag
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: HSERDYF
|
|
description: HSE ready interrupt flag
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: PLLRDYF
|
|
description: PLL ready interrupt flag
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: PLLSAI1RDYF
|
|
description: PLLSAI1 ready interrupt flag
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: HSECSSF
|
|
description: HSE Clock security system interrupt flag
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LSECSSF
|
|
description: LSE Clock security system interrupt flag
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HSI48RDYF
|
|
description: HSI48 ready interrupt flag
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: LSI2RDYF
|
|
description: LSI2 ready interrupt flag
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
fieldset/CR:
|
|
description: Clock control register
|
|
fields:
|
|
- name: MSION
|
|
description: MSI clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: MSIRDY
|
|
description: MSI clock ready flag
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: MSIPLLEN
|
|
description: MSI clock PLL enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: MSIRANGE
|
|
description: MSI clock ranges
|
|
bit_offset: 4
|
|
bit_size: 4
|
|
- name: HSION
|
|
description: HSI clock enabled
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: HSIKERON
|
|
description: HSI always enable for peripheral kernels
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HSIRDY
|
|
description: HSI clock ready flag
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: HSIASFS
|
|
description: HSI automatic start from Stop
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: HSIKERDY
|
|
description: HSI kernel clock ready flag for peripherals requests
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: HSEON
|
|
description: HSE clock enabled
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: HSERDY
|
|
description: HSE clock ready flag
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: HSEBYP
|
|
description: HSE crystal oscillator bypass
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: CSSON
|
|
description: HSE Clock security system enable
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: HSEPRE
|
|
description: HSE sysclk and PLL M divider prescaler
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: PLLON
|
|
description: Main PLL enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: PLLRDY
|
|
description: Main PLL clock ready flag
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: PLLSAI1ON
|
|
description: SAI1 PLL enable
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: PLLSAI1RDY
|
|
description: SAI1 PLL clock ready flag
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
fieldset/CRRCR:
|
|
description: Clock recovery RC register
|
|
fields:
|
|
- name: HSI48ON
|
|
description: HSI48 oscillator enabled
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: HSI48RDY
|
|
description: HSI48 clock ready
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: HSI48CAL
|
|
description: HSI48 clock calibration
|
|
bit_offset: 7
|
|
bit_size: 9
|
|
fieldset/CSR:
|
|
description: CSR
|
|
fields:
|
|
- name: LSI1ON
|
|
description: LSI1 oscillator enabled
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSI1RDY
|
|
description: LSI1 oscillator ready
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: LSI2ON
|
|
description: LSI2 oscillator enabled
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: LSI2RDY
|
|
description: LSI2 oscillator ready
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: LSI2TRIMEN
|
|
description: LSI2 oscillator trimming enable
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: LSI2TRIMOK
|
|
description: LSI2 oscillator trim OK
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: LSI2BW
|
|
description: LSI2 oscillator bias configuration
|
|
bit_offset: 8
|
|
bit_size: 4
|
|
- name: RFWKPSEL
|
|
description: RF system wakeup clock source selection
|
|
bit_offset: 14
|
|
bit_size: 2
|
|
- name: RFRSTS
|
|
description: Radio system BLE and 802.15.4 reset status
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: RMVF
|
|
description: Remove reset flag
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: OBLRSTF
|
|
description: Option byte loader reset flag
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: PINRSTF
|
|
description: Pin reset flag
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: BORRSTF
|
|
description: BOR flag
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: SFTRSTF
|
|
description: Software reset flag
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: IWDGRSTF
|
|
description: Independent window watchdog reset flag
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: WWDGRSTF
|
|
description: Window watchdog reset flag
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: LPWRRSTF
|
|
description: Low-power reset flag
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/EXTCFGR:
|
|
description: Extended clock recovery register
|
|
fields:
|
|
- name: SHDHPRE
|
|
description: Shared AHB prescaler
|
|
bit_offset: 0
|
|
bit_size: 4
|
|
- name: C2HPRE
|
|
description: CPU2 AHB prescaler
|
|
bit_offset: 4
|
|
bit_size: 4
|
|
- name: SHDHPREF
|
|
description: Shared AHB prescaler flag
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: C2HPREF
|
|
description: CPU2 AHB prescaler flag
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: RFCSS
|
|
description: RF clock source selected
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
fieldset/HSECR:
|
|
description: Clock HSE register
|
|
fields:
|
|
- name: UNLOCKED
|
|
description: Register lock system
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: HSES
|
|
description: HSE Sense amplifier threshold
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: HSEGMC
|
|
description: HSE current control
|
|
bit_offset: 4
|
|
bit_size: 3
|
|
- name: HSETUNE
|
|
description: HSE capacitor tuning
|
|
bit_offset: 8
|
|
bit_size: 6
|
|
fieldset/ICSCR:
|
|
description: Internal clock sources calibration register
|
|
fields:
|
|
- name: MSICAL
|
|
description: MSI clock calibration
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
- name: MSITRIM
|
|
description: MSI clock trimming
|
|
bit_offset: 8
|
|
bit_size: 8
|
|
- name: HSICAL
|
|
description: HSI clock calibration
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
- name: HSITRIM
|
|
description: HSI clock trimming
|
|
bit_offset: 24
|
|
bit_size: 7
|
|
fieldset/PLLCFGR:
|
|
description: PLLSYS configuration register
|
|
fields:
|
|
- name: PLLSRC
|
|
description: Main PLL, PLLSAI1 and PLLSAI2 entry clock source
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: PLLM
|
|
description: Division factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
|
|
bit_offset: 4
|
|
bit_size: 3
|
|
- name: PLLN
|
|
description: Main PLLSYS multiplication factor N
|
|
bit_offset: 8
|
|
bit_size: 7
|
|
- name: PLLPEN
|
|
description: Main PLLSYSP output enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: PLLP
|
|
description: Main PLL division factor P for PPLSYSSAICLK
|
|
bit_offset: 17
|
|
bit_size: 5
|
|
- name: PLLQEN
|
|
description: Main PLLSYSQ output enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: PLLQ
|
|
description: Main PLLSYS division factor Q for PLLSYSUSBCLK
|
|
bit_offset: 25
|
|
bit_size: 3
|
|
- name: PLLREN
|
|
description: Main PLLSYSR PLLCLK output enable
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: PLLR
|
|
description: Main PLLSYS division factor R for SYSCLK (system clock)
|
|
bit_offset: 29
|
|
bit_size: 3
|
|
fieldset/PLLSAI1CFGR:
|
|
description: PLLSAI1 configuration register
|
|
fields:
|
|
- name: PLLN
|
|
description: SAIPLL multiplication factor for VCO
|
|
bit_offset: 8
|
|
bit_size: 7
|
|
- name: PLLPEN
|
|
description: SAIPLL PLLSAI1CLK output enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: PLLP
|
|
description: SAI1PLL division factor P for PLLSAICLK (SAI1clock)
|
|
bit_offset: 17
|
|
bit_size: 5
|
|
- name: PLLQEN
|
|
description: SAIPLL PLLSAIUSBCLK output enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: PLLQ
|
|
description: SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock)
|
|
bit_offset: 25
|
|
bit_size: 3
|
|
- name: PLLREN
|
|
description: PLLSAI PLLADC1CLK output enable
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: PLLR
|
|
description: PLLSAI division factor R for PLLADC1CLK (ADC clock)
|
|
bit_offset: 29
|
|
bit_size: 3
|
|
fieldset/SMPSCR:
|
|
description: Step Down converter control register
|
|
fields:
|
|
- name: SMPSSEL
|
|
description: Step Down converter clock selection
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: SMPSDIV
|
|
description: Step Down converter clock prescaler
|
|
bit_offset: 4
|
|
bit_size: 2
|
|
- name: SMPSSWS
|
|
description: Step Down converter clock switch status
|
|
bit_offset: 8
|
|
bit_size: 2
|