stm32-data/data/registers/timer_v1.yaml

block/TIM_1CH:
  extends: TIM_CORE
  description: 1-channel timers
  items:
  - name: CR1
    description: control register 1
    byte_offset: 0
    bit_size: 16
    fieldset: CR1_1CH
  - name: DIER
    description: DMA/Interrupt enable register
    byte_offset: 12
    fieldset: DIER_1CH
  - name: SR
    description: status register
    byte_offset: 16
    fieldset: SR_1CH
  - name: EGR
    description: event generation register
    byte_offset: 20
    access: Write
    bit_size: 16
    fieldset: EGR_1CH
  - name: CCMR_Input
    description: capture/compare mode register 1 (input mode)
    array:
      len: 1
      stride: 4
    byte_offset: 24
    fieldset: CCMR_Input_1CH
  - name: CCMR_Output
    description: capture/compare mode register 1 (output mode)
    array:
      len: 1
      stride: 4
    byte_offset: 24
    fieldset: CCMR_Output_1CH
  - name: CCER
    description: capture/compare enable register
    byte_offset: 32
    fieldset: CCER_1CH
  - name: CCR
    description: capture/compare register x (x=1)
    array:
      len: 1
      stride: 4
    byte_offset: 52
    fieldset: CCR_1CH
  - name: OR
    description: |-
      Option register 1
      Note: Check Reference Manual to parse this register content
    byte_offset: 80
  - name: TISEL
    description: input selection register
    byte_offset: 104
    fieldset: TISEL_1CH
block/TIM_1CH_CMP:
  extends: TIM_1CH
  description: 1-channel with one complementary output timers
  items:
  - name: CR2
    description: control register 2
    byte_offset: 4
    fieldset: CR2_1CH_CMP
  - name: DIER
    description: DMA/Interrupt enable register
    byte_offset: 12
    fieldset: DIER_1CH_CMP
  - name: SR
    description: status register
    byte_offset: 16
    fieldset: SR_1CH_CMP
  - name: EGR
    description: event generation register
    byte_offset: 20
    access: Write
    bit_size: 16
    fieldset: EGR_1CH_CMP
  - name: CCER
    description: capture/compare enable register
    byte_offset: 32
    fieldset: CCER_1CH_CMP
  - name: RCR
    description: repetition counter register
    byte_offset: 48
    bit_size: 16
    fieldset: RCR_1CH_CMP
  - name: BDTR
    description: break and dead-time register
    byte_offset: 68
    fieldset: BDTR_1CH_CMP
  - name: DCR
    description: DMA control register
    byte_offset: 72
    fieldset: DCR_1CH_CMP
  - name: DMAR
    description: DMA address for full transfer
    byte_offset: 76
    fieldset: DMAR_GP16
  - name: AF1
    description: alternate function register 1
    byte_offset: 96
    fieldset: AF1_1CH_CMP
block/TIM_2CH:
  extends: TIM_1CH
  description: 2-channel timers
  items:
  - name: CR2
    description: control register 2
    byte_offset: 4
    fieldset: CR2_2CH
  - name: SMCR
    description: slave mode control register
    byte_offset: 8
    fieldset: SMCR_2CH
  - name: DIER
    description: DMA/Interrupt enable register
    byte_offset: 12
    fieldset: DIER_2CH
  - name: SR
    description: status register
    byte_offset: 16
    fieldset: SR_2CH
  - name: EGR
    description: event generation register
    byte_offset: 20
    access: Write
    bit_size: 16
    fieldset: EGR_2CH
  - name: CCMR_Input
    description: capture/compare mode register 1 (input mode)
    array:
      len: 1
      stride: 4
    byte_offset: 24
    fieldset: CCMR_Input_2CH
  - name: CCMR_Output
    description: capture/compare mode register 1 (output mode)
    array:
      len: 1
      stride: 4
    byte_offset: 24
    fieldset: CCMR_Output_2CH
  - name: CCER
    description: capture/compare enable register
    byte_offset: 32
    fieldset: CCER_2CH
  - name: CCR
    description: capture/compare register x (x=1-2)
    array:
      len: 2
      stride: 4
    byte_offset: 52
    fieldset: CCR_1CH
  - name: TISEL
    description: input selection register
    byte_offset: 104
    fieldset: TISEL_2CH
block/TIM_2CH_CMP:
  extends: TIM_1CH_CMP
  description: 2-channel with one complementary output timers
  items:
  - name: CR2
    description: control register 2
    byte_offset: 4
    fieldset: CR2_2CH_CMP
  - name: SMCR
    description: slave mode control register
    byte_offset: 8
    fieldset: SMCR_2CH
  - name: DIER
    description: DMA/Interrupt enable register
    byte_offset: 12
    fieldset: DIER_2CH_CMP
  - name: SR
    description: status register
    byte_offset: 16
    fieldset: SR_2CH_CMP
  - name: EGR
    description: event generation register
    byte_offset: 20
    access: Write
    bit_size: 16
    fieldset: EGR_2CH_CMP
  - name: CCMR_Input
    description: capture/compare mode register 1 (input mode)
    array:
      len: 2
      stride: 4
    byte_offset: 24
    fieldset: CCMR_Input_1CH
  - name: CCMR_Output
    description: capture/compare mode register 1 (output mode)
    array:
      len: 2
      stride: 4
    byte_offset: 24
    fieldset: CCMR_Output_1CH
  - name: CCER
    description: capture/compare enable register
    byte_offset: 32
    fieldset: CCER_2CH_CMP
  - name: CCR
    description: capture/compare register x (x=1-2)
    array:
      len: 2
      stride: 4
    byte_offset: 52
    fieldset: CCR_1CH
  - name: BDTR
    description: break and dead-time register
    byte_offset: 68
    fieldset: BDTR_1CH_CMP
  - name: DCR
    description: DMA control register
    byte_offset: 72
    fieldset: DCR_1CH_CMP
  - name: DMAR
    description: DMA address for full transfer
    byte_offset: 76
    fieldset: DMAR_GP16
  - name: TISEL
    description: input selection register
    byte_offset: 104
    fieldset: TISEL_2CH
block/TIM_ADV:
  extends: TIM_2CH_CMP
  description: Advanced Control timers
  items:
  - name: CR1
    description: control register 1
    byte_offset: 0
    bit_size: 16
    fieldset: CR1_GP16
  - name: CR2
    description: control register 2
    byte_offset: 4
    fieldset: CR2_ADV
  - name: SMCR
    description: slave mode control register
    byte_offset: 8
    fieldset: SMCR_ADV
  - name: DIER
    description: DMA/Interrupt enable register
    byte_offset: 12
    fieldset: DIER_ADV
  - name: SR
    description: status register
    byte_offset: 16
    fieldset: SR_ADV
  - name: EGR
    description: event generation register
    byte_offset: 20
    access: Write
    bit_size: 16
    fieldset: EGR_ADV
  - name: CCMR_Input
    description: capture/compare mode register 1-2 (input mode)
    array:
      len: 2
      stride: 4
    byte_offset: 24
    fieldset: CCMR_Input_2CH
  - name: CCMR_Output
    description: capture/compare mode register 1-2 (output mode)
    array:
      len: 2
      stride: 4
    byte_offset: 24
    fieldset: CCMR_Output_GP16
  - name: CCER
    description: capture/compare enable register
    byte_offset: 32
    fieldset: CCER_ADV
  - name: RCR
    description: repetition counter register
    byte_offset: 48
    bit_size: 16
    fieldset: RCR_ADV
  - name: CCR
    description: capture/compare register x (x=1-4)
    array:
      len: 4
      stride: 4
    byte_offset: 52
    fieldset: CCR_1CH
  - name: BDTR
    description: break and dead-time register
    byte_offset: 68
    fieldset: BDTR_ADV
  - name: DMAR
    description: DMA address for full transfer
    byte_offset: 76
  - name: CCMR3
    description: capture/compare mode register 3
    byte_offset: 84
    fieldset: CCMR3_ADV
  - name: CCR5
    description: capture/compare register 5
    byte_offset: 88
    fieldset: CCR5_ADV
  - name: CCR6
    description: capture/compare register 6
    byte_offset: 92
    fieldset: CCR_1CH
  - name: AF1
    description: alternate function register 1
    byte_offset: 96
    fieldset: AF1_ADV
  - name: AF2
    description: alternate function register 2
    byte_offset: 100
    fieldset: AF2_ADV
  - name: TISEL
    description: input selection register
    byte_offset: 104
    fieldset: TISEL_GP16
block/TIM_BASIC:
  extends: TIM_BASIC_NO_CR2
  description: Basic timers
  items:
  - name: CR2
    description: control register 2
    byte_offset: 4
    fieldset: CR2_BASIC
block/TIM_BASIC_NO_CR2:
  extends: TIM_CORE
  description: Virtual Basic timers without CR2 register for common part of TIM_BASIC and TIM_1CH_CMP
  items:
  - name: DIER
    description: DMA/Interrupt enable register
    byte_offset: 12
    fieldset: DIER_BASIC_NO_CR2
block/TIM_CORE:
  description: Virtual timer for common part of TIM_BASIC and TIM_1CH
  items:
  - name: CR1
    description: control register 1
    byte_offset: 0
    bit_size: 16
    fieldset: CR1_CORE
  - name: DIER
    description: DMA/Interrupt enable register
    byte_offset: 12
    fieldset: DIER_CORE
  - name: SR
    description: status register
    byte_offset: 16
    fieldset: SR_CORE
  - name: EGR
    description: event generation register
    byte_offset: 20
    access: Write
    bit_size: 16
    fieldset: EGR_CORE
  - name: CNT
    description: counter
    byte_offset: 36
    fieldset: CNT_CORE
  - name: PSC
    description: prescaler
    byte_offset: 40
    bit_size: 16
  - name: ARR
    description: auto-reload register
    byte_offset: 44
    fieldset: ARR_CORE
block/TIM_GP16:
  extends: TIM_2CH
  description: General purpose 16-bit timers
  items:
  - name: CR1
    description: control register 1
    byte_offset: 0
    bit_size: 16
    fieldset: CR1_GP16
  - name: CR2
    description: control register 2
    byte_offset: 4
    fieldset: CR2_GP16
  - name: SMCR
    description: slave mode control register
    byte_offset: 8
    fieldset: SMCR_GP16
  - name: DIER
    description: DMA/Interrupt enable register
    byte_offset: 12
    fieldset: DIER_GP16
  - name: SR
    description: status register
    byte_offset: 16
    fieldset: SR_GP16
  - name: EGR
    description: event generation register
    byte_offset: 20
    access: Write
    bit_size: 16
    fieldset: EGR_GP16
  - name: CCMR_Input
    description: capture/compare mode register 1-2 (input mode)
    array:
      len: 2
      stride: 4
    byte_offset: 24
    fieldset: CCMR_Input_2CH
  - name: CCMR_Output
    description: capture/compare mode register 1-2 (output mode)
    array:
      len: 2
      stride: 4
    byte_offset: 24
    fieldset: CCMR_Output_GP16
  - name: CCER
    description: capture/compare enable register
    byte_offset: 32
    fieldset: CCER_GP16
  - name: CCR
    description: capture/compare register x (x=1-4)
    array:
      len: 4
      stride: 4
    byte_offset: 52
    fieldset: CCR_1CH
  - name: DCR
    description: DMA control register
    byte_offset: 72
    fieldset: DCR_GP16
  - name: DMAR
    description: DMA address for full transfer
    byte_offset: 76
    fieldset: DMAR_GP16
  - name: AF1
    description: alternate function register 1
    byte_offset: 96
    fieldset: AF1_GP16
  - name: TISEL
    description: input selection register
    byte_offset: 104
    fieldset: TISEL_GP16
block/TIM_GP32:
  extends: TIM_GP16
  description: General purpose 32-bit timers
  items:
  - name: CNT
    description: counter
    byte_offset: 36
  - name: ARR
    description: auto-reload register
    byte_offset: 44
  - name: CCR
    description: capture/compare register x (x=1-4)
    array:
      len: 4
      stride: 4
    byte_offset: 52
  - name: DCR
    description: DMA control register
    byte_offset: 72
    fieldset: DCR_1CH_CMP
fieldset/AF1_1CH_CMP:
  description: alternate function register 1
  fields:
  - name: BKINE
    description: TIMx_BKIN input enable
    bit_offset: 0
    bit_size: 1
  - name: BKCMPE
    description: TIM_BRK_CMPx (x=1-2) enable
    bit_offset: 1
    bit_size: 1
    array:
      len: 2
      stride: 1
  - name: BKDF1BKE
    description: BRK DFSDM1_BREAKx enable (x=0 if TIM15, x=1 if TIM16, x=2 if TIM17)
    bit_offset: 8
    bit_size: 1
  - name: BKINP
    description: TIMx_BKIN input polarity
    bit_offset: 9
    bit_size: 1
    enum: BKINP
  - name: BKCMPP
    description: TIM_BRK_CMPx (x=1-2) input polarity
    bit_offset: 10
    bit_size: 1
    array:
      len: 2
      stride: 1
    enum: BKINP
fieldset/AF1_ADV:
  extends: AF1_1CH_CMP
  description: alternate function register 1
  fields:
  - name: ETRSEL
    description: etr_in source selection
    bit_offset: 14
    bit_size: 4
fieldset/AF1_GP16:
  description: alternate function register 1
  fields:
  - name: ETRSEL
    description: etr_in source selection
    bit_offset: 14
    bit_size: 4
fieldset/AF2_ADV:
  description: alternate function register 2
  fields:
  - name: BK2INE
    description: TIMx_BKIN2 input enable
    bit_offset: 0
    bit_size: 1
  - name: BK2CMPE
    description: TIM_BRK2_CMPx (x=1-8) enable
    bit_offset: 1
    bit_size: 1
    array:
      len: 1
      stride: 8
  - name: BK2DF1BK1E
    description: BRK2 DFSDM1_BREAK1 enable
    bit_offset: 8
    bit_size: 1
  - name: BK2INP
    description: TIMx_BK2IN input polarity
    bit_offset: 9
    bit_size: 1
    enum: BKINP
  - name: BK2CMPP
    description: TIM_BRK2_CMPx (x=1-4) input polarity
    bit_offset: 10
    bit_size: 1
    array:
      len: 2
      stride: 1
    enum: BKINP
fieldset/ARR_CORE:
  description: auto-reload register
  fields:
  - name: ARR
    description: Auto-reload value
    bit_offset: 0
    bit_size: 16
fieldset/BDTR_1CH_CMP:
  description: break and dead-time register
  fields:
  - name: DTG
    description: Dead-time generator setup
    bit_offset: 0
    bit_size: 8
  - name: LOCK
    description: Lock configuration
    bit_offset: 8
    bit_size: 2
    enum: LOCK
  - name: OSSI
    description: Off-state selection for Idle mode
    bit_offset: 10
    bit_size: 1
    enum: OSSI
  - name: OSSR
    description: Off-state selection for Run mode
    bit_offset: 11
    bit_size: 1
    enum: OSSR
  - name: BKE
    description: Break x (x=1) enable
    bit_offset: 12
    bit_size: 1
    array:
      len: 1
      stride: 12
  - name: BKP
    description: Break x (x=1) polarity
    bit_offset: 13
    bit_size: 1
    array:
      len: 1
      stride: 12
    enum: BKP
  - name: AOE
    description: Automatic output enable
    bit_offset: 14
    bit_size: 1
  - name: MOE
    description: Main output enable
    bit_offset: 15
    bit_size: 1
  - name: BKF
    description: Break x (x=1) filter
    bit_offset: 16
    bit_size: 4
    array:
      len: 1
      stride: 4
    enum: FilterValue
fieldset/BDTR_ADV:
  extends: BDTR_1CH_CMP
  description: break and dead-time register
  fields:
  - name: BKE
    description: Break x (x=1,2) enable
    bit_offset: 12
    bit_size: 1
    array:
      len: 2
      stride: 12
  - name: BKP
    description: Break x (x=1,2) polarity
    bit_offset: 13
    bit_size: 1
    array:
      len: 2
      stride: 12
    enum: BKP
  - name: BKF
    description: Break x (x=1,2) filter
    bit_offset: 16
    bit_size: 4
    array:
      len: 2
      stride: 4
    enum: FilterValue
fieldset/CCER_1CH:
  description: capture/compare enable register
  fields:
  - name: CCE
    description: Capture/Compare x (x=1) output enable
    bit_offset: 0
    bit_size: 1
    array:
      len: 1
      stride: 4
  - name: CCP
    description: Capture/Compare x (x=1) output Polarity
    bit_offset: 1
    bit_size: 1
    array:
      len: 1
      stride: 4
  - name: CCNP
    description: Capture/Compare x (x=1) output Polarity
    bit_offset: 3
    bit_size: 1
    array:
      len: 1
      stride: 4
fieldset/CCER_1CH_CMP:
  extends: CCER_1CH
  description: capture/compare enable register
  fields:
  - name: CCNE
    description: Capture/Compare x (x=1) complementary output enable
    bit_offset: 2
    bit_size: 1
    array:
      len: 1
      stride: 4
fieldset/CCER_2CH:
  extends: CCER_1CH
  description: capture/compare enable register
  fields:
  - name: CCE
    description: Capture/Compare x (x=1-2) output enable
    bit_offset: 0
    bit_size: 1
    array:
      len: 2
      stride: 4
  - name: CCP
    description: Capture/Compare x (x=1-2) output Polarity
    bit_offset: 1
    bit_size: 1
    array:
      len: 2
      stride: 4
  - name: CCNP
    description: Capture/Compare x (x=1-2) output Polarity
    bit_offset: 3
    bit_size: 1
    array:
      len: 2
      stride: 4
fieldset/CCER_2CH_CMP:
  extends: CCER_2CH
  description: capture/compare enable register
  fields:
  - name: CCNE
    description: Capture/Compare x (x=1) complementary output enable
    bit_offset: 2
    bit_size: 1
    array:
      len: 1
      stride: 4
fieldset/CCER_ADV:
  extends: CCER_2CH_CMP
  description: capture/compare enable register
  fields:
  - name: CCE
    description: Capture/Compare x (x=1-6) output enable
    bit_offset: 0
    bit_size: 1
    array:
      len: 6
      stride: 4
  - name: CCP
    description: Capture/Compare x (x=1-6) output Polarity
    bit_offset: 1
    bit_size: 1
    array:
      len: 6
      stride: 4
  - name: CCNE
    description: Capture/Compare x (x=1-3) complementary output enable
    bit_offset: 2
    bit_size: 1
    array:
      len: 3
      stride: 4
  - name: CCNP
    description: Capture/Compare x (x=1-4) output Polarity
    bit_offset: 3
    bit_size: 1
    array:
      len: 4
      stride: 4
fieldset/CCER_GP16:
  description: capture/compare enable register
  fields:
  - name: CCE
    description: Capture/Compare x (x=1-4) output enable
    bit_offset: 0
    bit_size: 1
    array:
      len: 4
      stride: 4
  - name: CCP
    description: Capture/Compare x (x=1-4) output Polarity
    bit_offset: 1
    bit_size: 1
    array:
      len: 4
      stride: 4
  - name: CCNP
    description: Capture/Compare x (x=1-4) output Polarity
    bit_offset: 3
    bit_size: 1
    array:
      len: 4
      stride: 4
fieldset/CCMR3_ADV:
  description: capture/compare mode register 3
  fields:
  - name: OCFE
    description: Output compare x (x=5,6) fast enable
    bit_offset: 2
    bit_size: 1
    array:
      len: 2
      stride: 8
  - name: OCPE
    description: Output compare x (x=5,6) preload enable
    bit_offset: 3
    bit_size: 1
    array:
      len: 2
      stride: 8
  - name: OCM
    description: Output compare x (x=5,6) mode
    bit_offset: 4
    bit_size: 3
    array:
      len: 2
      stride: 8
    enum: OCM
  - name: OCCE
    description: Output compare x (x=5,6) clear enable
    bit_offset: 7
    bit_size: 1
    array:
      len: 2
      stride: 8
fieldset/CCMR_Input_1CH:
  description: capture/compare mode register x (x=1) (input mode)
  fields:
  - name: CCS
    description: Capture/Compare y selection
    bit_offset: 0
    bit_size: 2
    array:
      len: 1
      stride: 8
    enum: CCMR_Input_CCS
  - name: ICPSC
    description: Input capture y prescaler
    bit_offset: 2
    bit_size: 2
    array:
      len: 1
      stride: 8
  - name: ICF
    description: Input capture y filter
    bit_offset: 4
    bit_size: 4
    array:
      len: 1
      stride: 8
    enum: FilterValue
fieldset/CCMR_Input_2CH:
  extends: CCMR_Input_1CH
  description: capture/compare mode register x (x=1) (input mode)
  fields:
  - name: CCS
    description: Capture/Compare y selection
    bit_offset: 0
    bit_size: 2
    array:
      len: 2
      stride: 8
    enum: CCMR_Input_CCS
  - name: ICPSC
    description: Input capture y prescaler
    bit_offset: 2
    bit_size: 2
    array:
      len: 2
      stride: 8
  - name: ICF
    description: Input capture y filter
    bit_offset: 4
    bit_size: 4
    array:
      len: 2
      stride: 8
    enum: FilterValue
fieldset/CCMR_Output_1CH:
  description: capture/compare mode register x (x=1) (output mode)
  fields:
  - name: CCS
    description: Capture/Compare y selection
    bit_offset: 0
    bit_size: 2
    array:
      len: 1
      stride: 8
    enum: CCMR_Output_CCS
  - name: OCFE
    description: Output compare y fast enable
    bit_offset: 2
    bit_size: 1
    array:
      len: 1
      stride: 8
  - name: OCPE
    description: Output compare y preload enable
    bit_offset: 3
    bit_size: 1
    array:
      len: 1
      stride: 8
  - name: OCM
    description: Output compare y mode
    bit_offset: 4
    bit_size: 3
    array:
      len: 1
      stride: 8
    enum: OCM
fieldset/CCMR_Output_2CH:
  extends: CCMR_Output_1CH
  description: capture/compare mode register x (x=1) (output mode)
  fields:
  - name: CCS
    description: Capture/Compare y selection
    bit_offset: 0
    bit_size: 2
    array:
      len: 2
      stride: 8
    enum: CCMR_Output_CCS
  - name: OCFE
    description: Output compare y fast enable
    bit_offset: 2
    bit_size: 1
    array:
      len: 2
      stride: 8
  - name: OCPE
    description: Output compare y preload enable
    bit_offset: 3
    bit_size: 1
    array:
      len: 2
      stride: 8
  - name: OCM
    description: Output compare y mode
    bit_offset: 4
    bit_size: 3
    array:
      len: 2
      stride: 8
    enum: OCM
fieldset/CCMR_Output_GP16:
  extends: CCMR_Output_2CH
  description: capture/compare mode register x (x=1-2) (output mode)
  fields:
  - name: OCCE
    description: Output compare y clear enable
    bit_offset: 7
    bit_size: 1
    array:
      len: 2
      stride: 8
fieldset/CCR5_ADV:
  extends: CCR_1CH
  description: capture/compare register 5
  fields:
  - name: GC5C
    description: Group channel 5 and channel x (x=1-3)
    bit_offset: 29
    bit_size: 1
    array:
      len: 3
      stride: 1
    enum: GC5C
fieldset/CCR_1CH:
  description: capture/compare register x (x=1-4,6)
  fields:
  - name: CCR
    description: capture/compare x (x=1-4,6) value
    bit_offset: 0
    bit_size: 16
fieldset/CNT_CORE:
  description: counter
  fields:
  - name: CNT
    description: counter value
    bit_offset: 0
    bit_size: 16
  - name: UIFCPY
    description: UIF copy
    bit_offset: 31
    bit_size: 1
fieldset/CR1_1CH:
  extends: CR1_CORE
  description: control register 1
  fields:
  - name: CKD
    description: Clock division
    bit_offset: 8
    bit_size: 2
    enum: CKD
fieldset/CR1_CORE:
  description: control register 1
  fields:
  - name: CEN
    description: Counter enable
    bit_offset: 0
    bit_size: 1
  - name: UDIS
    description: Update disable
    bit_offset: 1
    bit_size: 1
  - name: URS
    description: Update request source
    bit_offset: 2
    bit_size: 1
    enum: URS
  - name: OPM
    description: One-pulse mode enbaled
    bit_offset: 3
    bit_size: 1
  - name: ARPE
    description: Auto-reload preload enable
    bit_offset: 7
    bit_size: 1
  - name: UIFREMAP
    description: UIF status bit remapping enable
    bit_offset: 11
    bit_size: 1
fieldset/CR1_GP16:
  extends: CR1_CORE
  description: control register 1
  fields:
  - name: DIR
    description: Direction
    bit_offset: 4
    bit_size: 1
    enum: DIR
  - name: CMS
    description: Center-aligned mode selection
    bit_offset: 5
    bit_size: 2
    enum: CMS
  - name: CKD
    description: Clock division
    bit_offset: 8
    bit_size: 2
    enum: CKD
fieldset/CR2_1CH_CMP:
  description: control register 2
  fields:
  - name: CCPC
    description: Capture/compare preloaded control
    bit_offset: 0
    bit_size: 1
  - name: CCUS
    description: Capture/compare control update selection
    bit_offset: 2
    bit_size: 1
  - name: CCDS
    description: Capture/compare DMA selection
    bit_offset: 3
    bit_size: 1
    enum: CCDS
  - name: OIS
    description: Output Idle state x (x=1)
    bit_offset: 8
    bit_size: 1
    array:
      len: 1
      stride: 2
  - name: OISN
    description: Output Idle state x (x=1)
    bit_offset: 9
    bit_size: 1
    array:
      len: 1
      stride: 2
fieldset/CR2_2CH:
  description: control register 2
  fields:
  - name: MMS
    description: Master mode selection
    bit_offset: 4
    bit_size: 3
    enum: MMS
  - name: TI1S
    description: TI1 selection
    bit_offset: 7
    bit_size: 1
    enum: TI1S
fieldset/CR2_2CH_CMP:
  extends: CR2_1CH_CMP
  description: control register 2
  fields:
  - name: MMS
    description: Master mode selection
    bit_offset: 4
    bit_size: 3
    enum: MMS
  - name: TI1S
    description: TI1 selection
    bit_offset: 7
    bit_size: 1
    enum: TI1S
  - name: OIS
    description: Output Idle state x (x=1,2)
    bit_offset: 8
    bit_size: 1
    array:
      len: 2
      stride: 2
fieldset/CR2_ADV:
  extends: CR2_2CH_CMP
  description: control register 2
  fields:
  - name: OIS
    description: Output Idle state x (x=1-6)
    bit_offset: 8
    bit_size: 1
    array:
      len: 6
      stride: 2
  - name: OISN
    description: Output Idle state x N x (x=1-4)
    bit_offset: 9
    bit_size: 1
    array:
      len: 4
      stride: 2
  - name: MMS2
    description: Master mode selection 2
    bit_offset: 20
    bit_size: 4
    enum: MMS2
fieldset/CR2_BASIC:
  description: control register 2
  fields:
  - name: MMS
    description: Master mode selection
    bit_offset: 4
    bit_size: 3
    enum: MMS
fieldset/CR2_GP16:
  extends: CR2_BASIC
  description: control register 2
  fields:
  - name: CCDS
    description: Capture/compare DMA selection
    bit_offset: 3
    bit_size: 1
    enum: CCDS
  - name: TI1S
    description: TI1 selection
    bit_offset: 7
    bit_size: 1
    enum: TI1S
fieldset/DCR_1CH_CMP:
  description: DMA control register
  fields:
  - name: DBA
    description: DMA base address
    bit_offset: 0
    bit_size: 5
  - name: DBL
    description: DMA burst length
    bit_offset: 8
    bit_size: 5
fieldset/DCR_GP16:
  extends: DCR_1CH_CMP
  description: DMA control register
  fields:
  - name: DBSS
    description: DMA burst source selection
    bit_offset: 16
    bit_size: 4
    enum: DBSS
fieldset/DIER_1CH:
  extends: DIER_CORE
  description: DMA/Interrupt enable register
  fields:
  - name: CCIE
    description: Capture/Compare x (x=1) interrupt enable
    bit_offset: 1
    bit_size: 1
    array:
      len: 1
      stride: 1
fieldset/DIER_1CH_CMP:
  extends: DIER_1CH
  description: DMA/Interrupt enable register
  fields:
  - name: COMIE
    description: COM interrupt enable
    bit_offset: 5
    bit_size: 1
  - name: BIE
    description: Break interrupt enable
    bit_offset: 7
    bit_size: 1
  - name: UDE
    description: Update DMA request enable
    bit_offset: 8
    bit_size: 1
  - name: CCDE
    description: Capture/Compare x (x=1) DMA request enable
    bit_offset: 9
    bit_size: 1
    array:
      len: 1
      stride: 1
fieldset/DIER_2CH:
  extends: DIER_1CH
  description: DMA/Interrupt enable register
  fields:
  - name: CCIE
    description: Capture/Compare x (x=1-2) interrupt enable
    bit_offset: 1
    bit_size: 1
    array:
      len: 2
      stride: 1
  - name: TIE
    description: Trigger interrupt enable
    bit_offset: 6
    bit_size: 1
fieldset/DIER_2CH_CMP:
  extends: DIER_1CH_CMP
  description: DMA/Interrupt enable register
  fields:
  - name: COMDE
    description: COM DMA request enable
    bit_offset: 13
    bit_size: 1
  - name: TDE
    description: Trigger DMA request enable
    bit_offset: 14
    bit_size: 1
fieldset/DIER_ADV:
  extends: DIER_2CH_CMP
  description: DMA/Interrupt enable register
  fields:
  - name: CCIE
    description: Capture/Compare x (x=1-4) interrupt enable
    bit_offset: 1
    bit_size: 1
    array:
      len: 4
      stride: 1
  - name: BIE
    description: Break interrupt enable
    bit_offset: 7
    bit_size: 1
  - name: CCDE
    description: Capture/Compare x (x=1-4) DMA request enable
    bit_offset: 9
    bit_size: 1
    array:
      len: 4
      stride: 1
fieldset/DIER_BASIC_NO_CR2:
  extends: DIER_CORE
  description: DMA/Interrupt enable register
  fields:
  - name: UDE
    description: Update DMA request enable
    bit_offset: 8
    bit_size: 1
fieldset/DIER_CORE:
  description: DMA/Interrupt enable register
  fields:
  - name: UIE
    description: Update interrupt enable
    bit_offset: 0
    bit_size: 1
fieldset/DIER_GP16:
  extends: DIER_BASIC_NO_CR2
  description: DMA/Interrupt enable register
  fields:
  - name: CCIE
    description: Capture/Compare x (x=1-4) interrupt enable
    bit_offset: 1
    bit_size: 1
    array:
      len: 4
      stride: 1
  - name: TIE
    description: Trigger interrupt enable
    bit_offset: 6
    bit_size: 1
  - name: CCDE
    description: Capture/Compare x (x=1-4) DMA request enable
    bit_offset: 9
    bit_size: 1
    array:
      len: 4
      stride: 1
  - name: TDE
    description: Trigger DMA request enable
    bit_offset: 14
    bit_size: 1
fieldset/DMAR_GP16:
  description: DMA address for full transfer
  fields:
  - name: DMAB
    description: DMA register for burst accesses
    bit_offset: 0
    bit_size: 16
fieldset/EGR_1CH:
  extends: EGR_CORE
  description: event generation register
  fields:
  - name: CCG
    description: Capture/compare x (x=1) generation
    bit_offset: 1
    bit_size: 1
    array:
      len: 1
      stride: 1
fieldset/EGR_1CH_CMP:
  extends: EGR_1CH
  description: event generation register
  fields:
  - name: COMG
    description: Capture/Compare control update generation
    bit_offset: 5
    bit_size: 1
  - name: BG
    description: Break x (x=1) generation
    bit_offset: 7
    bit_size: 1
    array:
      len: 1
      stride: 1
fieldset/EGR_2CH:
  extends: EGR_1CH
  description: event generation register
  fields:
  - name: CCG
    description: Capture/compare x (x=1-2) generation
    bit_offset: 1
    bit_size: 1
    array:
      len: 2
      stride: 1
  - name: TG
    description: Trigger generation
    bit_offset: 6
    bit_size: 1
fieldset/EGR_2CH_CMP:
  extends: EGR_1CH_CMP
  description: event generation register
  fields:
  - name: CCG
    description: Capture/compare x (x=1,2) generation
    bit_offset: 1
    bit_size: 1
    array:
      len: 2
      stride: 1
  - name: TG
    description: Trigger generation
    bit_offset: 6
    bit_size: 1
fieldset/EGR_ADV:
  extends: EGR_2CH_CMP
  description: event generation register
  fields:
  - name: CCG
    description: Capture/compare x (x=1-4) generation
    bit_offset: 1
    bit_size: 1
    array:
      len: 4
      stride: 1
  - name: BG
    description: Break x (x=1-2) generation
    bit_offset: 7
    bit_size: 1
    array:
      len: 2
      stride: 1
fieldset/EGR_CORE:
  description: event generation register
  fields:
  - name: UG
    description: Update generation
    bit_offset: 0
    bit_size: 1
fieldset/EGR_GP16:
  extends: EGR_CORE
  description: event generation register
  fields:
  - name: CCG
    description: Capture/compare x (x=1-4) generation
    bit_offset: 1
    bit_size: 1
    array:
      len: 4
      stride: 1
  - name: TG
    description: Trigger generation
    bit_offset: 6
    bit_size: 1
fieldset/RCR_1CH_CMP:
  description: repetition counter register
  fields:
  - name: REP
    description: Repetition counter value
    bit_offset: 0
    bit_size: 8
fieldset/RCR_ADV:
  description: repetition counter register
  fields:
  - name: REP
    description: Repetition counter value
    bit_offset: 0
    bit_size: 16
fieldset/SMCR_2CH:
  description: slave mode control register
  fields:
  - name: SMS
    description: Slave mode selection
    bit_offset:
    - start: 0
      end: 2
    - start: 16
      end: 16
    bit_size: 4
    enum: SMS
  - name: TS
    description: Trigger selection
    bit_offset:
    - start: 4
      end: 6
    - start: 20
      end: 21
    bit_size: 5
    enum: TS
  - name: MSM
    description: Master/Slave mode
    bit_offset: 7
    bit_size: 1
    enum: MSM
fieldset/SMCR_ADV:
  extends: SMCR_2CH
  description: slave mode control register
  fields:
  - name: ETF
    description: External trigger filter
    bit_offset: 8
    bit_size: 4
    enum: FilterValue
  - name: ETPS
    description: External trigger prescaler
    bit_offset: 12
    bit_size: 2
    enum: ETPS
  - name: ECE
    description: External clock mode 2 enable
    bit_offset: 14
    bit_size: 1
  - name: ETP
    description: External trigger polarity
    bit_offset: 15
    bit_size: 1
    enum: ETP
fieldset/SMCR_GP16:
  extends: SMCR_2CH
  description: slave mode control register
  fields:
  - name: ETF
    description: External trigger filter
    bit_offset: 8
    bit_size: 4
    enum: FilterValue
  - name: ETPS
    description: External trigger prescaler
    bit_offset: 12
    bit_size: 2
    enum: ETPS
  - name: ECE
    description: External clock mode 2 enable
    bit_offset: 14
    bit_size: 1
  - name: ETP
    description: External trigger polarity
    bit_offset: 15
    bit_size: 1
    enum: ETP
fieldset/SR_1CH:
  extends: SR_CORE
  description: status register
  fields:
  - name: CCIF
    description: Capture/compare x (x=1) interrupt flag
    bit_offset: 1
    bit_size: 1
    array:
      len: 1
      stride: 1
  - name: CCOF
    description: Capture/Compare x (x=1) overcapture flag
    bit_offset: 9
    bit_size: 1
    array:
      len: 1
      stride: 1
fieldset/SR_1CH_CMP:
  extends: SR_1CH
  description: status register
  fields:
  - name: COMIF
    description: COM interrupt flag
    bit_offset: 5
    bit_size: 1
  - name: BIF
    description: Break x (x=1) interrupt flag
    bit_offset: 7
    bit_size: 1
    array:
      len: 1
      stride: 1
fieldset/SR_2CH:
  extends: SR_1CH
  description: status register
  fields:
  - name: CCIF
    description: Capture/compare x (x=1-2) interrupt flag
    bit_offset: 1
    bit_size: 1
    array:
      len: 2
      stride: 1
  - name: TIF
    description: Trigger interrupt flag
    bit_offset: 6
    bit_size: 1
  - name: CCOF
    description: Capture/Compare x (x=1-2) overcapture flag
    bit_offset: 9
    bit_size: 1
    array:
      len: 2
      stride: 1
fieldset/SR_2CH_CMP:
  extends: SR_1CH_CMP
  description: status register
  fields:
  - name: CCIF
    description: Capture/compare x (x=1,2) interrupt flag
    bit_offset: 1
    bit_size: 1
    array:
      len: 2
      stride: 1
  - name: TIF
    description: Trigger interrupt flag
    bit_offset: 6
    bit_size: 1
  - name: CCOF
    description: Capture/Compare x (x=1,2) overcapture flag
    bit_offset: 9
    bit_size: 1
    array:
      len: 2
      stride: 1
fieldset/SR_ADV:
  extends: SR_2CH_CMP
  description: status register
  fields:
  - name: CCIF
    description: Capture/compare x (x=1-4) interrupt flag
    bit_offset: 1
    bit_size: 1
    array:
      len: 4
      stride: 1
  - name: BIF
    description: Break x (x=1,2) interrupt flag
    bit_offset: 7
    bit_size: 1
    array:
      len: 2
      stride: 1
  - name: CCOF
    description: Capture/Compare x (x=1-4) overcapture flag
    bit_offset: 9
    bit_size: 1
    array:
      len: 4
      stride: 1
  - name: SBIF
    description: System Break interrupt flag
    bit_offset: 13
    bit_size: 1
  - name: CCIF5
    description: Capture/compare 5 interrupt flag
    bit_offset: 16
    bit_size: 1
  - name: CCIF6
    description: Capture/compare 6 interrupt flag
    bit_offset: 17
    bit_size: 1
fieldset/SR_CORE:
  description: status register
  fields:
  - name: UIF
    description: Update interrupt flag
    bit_offset: 0
    bit_size: 1
fieldset/SR_GP16:
  extends: SR_CORE
  description: status register
  fields:
  - name: CCIF
    description: Capture/compare x (x=1-4) interrupt flag
    bit_offset: 1
    bit_size: 1
    array:
      len: 4
      stride: 1
  - name: TIF
    description: Trigger interrupt flag
    bit_offset: 6
    bit_size: 1
  - name: CCOF
    description: Capture/Compare x (x=1-4) overcapture flag
    bit_offset: 9
    bit_size: 1
    array:
      len: 4
      stride: 1
fieldset/TISEL_1CH:
  description: input selection register
  fields:
  - name: TISEL
    description: Selects TIM_TIx (x=1) input
    bit_offset: 0
    bit_size: 4
    array:
      len: 1
      stride: 8
fieldset/TISEL_2CH:
  extends: TISEL_1CH
  description: input selection register
  fields:
  - name: TISEL
    description: Selects TIM_TIx (x=1-2) input
    bit_offset: 0
    bit_size: 4
    array:
      len: 2
      stride: 8
fieldset/TISEL_GP16:
  description: input selection register
  fields:
  - name: TISEL
    description: Selects TIM_TIx (x=1-4) input
    bit_offset: 0
    bit_size: 4
    array:
      len: 4
      stride: 8
enum/BKINP:
  bit_size: 1
  variants:
  - name: NotInverted
    description: input polarity is not inverted (active low if BKxP = 0, active high if BKxP = 1)
    value: 0
  - name: Inverted
    description: input polarity is inverted (active high if BKxP = 0, active low if BKxP = 1)
    value: 1
enum/BKP:
  bit_size: 1
  variants:
  - name: ActiveLow
    description: Break input tim_brk is active low
    value: 0
  - name: ActiveHigh
    description: Break input tim_brk is active high
    value: 1
enum/CCDS:
  bit_size: 1
  variants:
  - name: OnCompare
    description: CCx DMA request sent when CCx event occurs
    value: 0
  - name: OnUpdate
    description: CCx DMA request sent when update event occurs
    value: 1
enum/CCMR_Input_CCS:
  bit_size: 2
  variants:
  - name: TI4
    description: 'CCx channel is configured as input, normal mapping: ICx mapped to TIx'
    value: 1
  - name: TI3
    description: CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4)
    value: 2
  - name: TRC
    description: CCx channel is configured as input, ICx is mapped on TRC
    value: 3
enum/CCMR_Output_CCS:
  bit_size: 2
  variants:
  - name: Output
    description: CCx channel is configured as output
    value: 0
enum/CKD:
  bit_size: 2
  variants:
  - name: Div1
    description: t_DTS = t_CK_INT
    value: 0
  - name: Div2
    description: t_DTS = 2 × t_CK_INT
    value: 1
  - name: Div4
    description: t_DTS = 4 × t_CK_INT
    value: 2
enum/CMS:
  bit_size: 2
  variants:
  - name: EdgeAligned
    description: The counter counts up or down depending on the direction bit
    value: 0
  - name: CenterAligned1
    description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
    value: 1
  - name: CenterAligned2
    description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
    value: 2
  - name: CenterAligned3
    description: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
    value: 3
enum/DBSS:
  bit_size: 4
  variants:
  - name: Update
    description: Update
    value: 1
  - name: CC1
    description: CC1
    value: 2
  - name: CC2
    description: CC2
    value: 3
  - name: CC3
    description: CC3
    value: 4
  - name: CC4
    description: CC4
    value: 5
  - name: COM
    description: COM
    value: 6
  - name: Trigger
    description: Trigger
    value: 7
enum/DIR:
  bit_size: 1
  variants:
  - name: Up
    description: Counter used as upcounter
    value: 0
  - name: Down
    description: Counter used as downcounter
    value: 1
enum/ETP:
  bit_size: 1
  variants:
  - name: NotInverted
    description: ETR is noninverted, active at high level or rising edge
    value: 0
  - name: Inverted
    description: ETR is inverted, active at low level or falling edge
    value: 1
enum/ETPS:
  bit_size: 2
  variants:
  - name: Div1
    description: Prescaler OFF
    value: 0
  - name: Div2
    description: ETRP frequency divided by 2
    value: 1
  - name: Div4
    description: ETRP frequency divided by 4
    value: 2
  - name: Div8
    description: ETRP frequency divided by 8
    value: 3
enum/FilterValue:
  bit_size: 4
  variants:
  - name: NoFilter
    description: No filter, sampling is done at fDTS
    value: 0
  - name: FCK_INT_N2
    description: fSAMPLING=fCK_INT, N=2
    value: 1
  - name: FCK_INT_N4
    description: fSAMPLING=fCK_INT, N=4
    value: 2
  - name: FCK_INT_N8
    description: fSAMPLING=fCK_INT, N=8
    value: 3
  - name: FDTS_Div2_N6
    description: fSAMPLING=fDTS/2, N=6
    value: 4
  - name: FDTS_Div2_N8
    description: fSAMPLING=fDTS/2, N=8
    value: 5
  - name: FDTS_Div4_N6
    description: fSAMPLING=fDTS/4, N=6
    value: 6
  - name: FDTS_Div4_N8
    description: fSAMPLING=fDTS/4, N=8
    value: 7
  - name: FDTS_Div8_N6
    description: fSAMPLING=fDTS/8, N=6
    value: 8
  - name: FDTS_Div8_N8
    description: fSAMPLING=fDTS/8, N=8
    value: 9
  - name: FDTS_Div16_N5
    description: fSAMPLING=fDTS/16, N=5
    value: 10
  - name: FDTS_Div16_N6
    description: fSAMPLING=fDTS/16, N=6
    value: 11
  - name: FDTS_Div16_N8
    description: fSAMPLING=fDTS/16, N=8
    value: 12
  - name: FDTS_Div32_N5
    description: fSAMPLING=fDTS/32, N=5
    value: 13
  - name: FDTS_Div32_N6
    description: fSAMPLING=fDTS/32, N=6
    value: 14
  - name: FDTS_Div32_N8
    description: fSAMPLING=fDTS/32, N=8
    value: 15
enum/GC5C:
  bit_size: 1
  variants:
  - name: NoEffect
    description: No effect of TIM_OC5REF on TIM_OCxREFC (x=1-3)
    value: 0
  - name: LogicalAND
    description: TIM_OCxREFC is the logical AND of TIM_OCxREF and TIM_OC5REF
    value: 1
enum/LOCK:
  bit_size: 2
  variants:
  - name: Disabled
    description: No bit is write protected
    value: 0
  - name: Level1
    description: DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written
    value: 1
  - name: Level2
    description: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.
    value: 2
  - name: Level3
    description: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.
    value: 3
enum/MMS:
  bit_size: 3
  variants:
  - name: Reset
    description: The UG bit from the TIMx_EGR register is used as trigger output
    value: 0
  - name: Enable
    description: The counter enable signal, CNT_EN, is used as trigger output
    value: 1
  - name: Update
    description: The update event is selected as trigger output
    value: 2
  - name: ComparePulse
    description: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
    value: 3
  - name: CompareOC1
    description: OC1REF signal is used as trigger output
    value: 4
  - name: CompareOC2
    description: OC2REF signal is used as trigger output
    value: 5
  - name: CompareOC3
    description: OC3REF signal is used as trigger output
    value: 6
  - name: CompareOC4
    description: OC4REF signal is used as trigger output
    value: 7
enum/MMS2:
  bit_size: 4
  variants:
  - name: Reset
    description: The UG bit from the TIMx_EGR register is used as TRGO2
    value: 0
  - name: Enable
    description: The counter enable signal, CNT_EN, is used as TRGO2
    value: 1
  - name: Update
    description: The update event is selected as TRGO2
    value: 2
  - name: ComparePulse
    description: TRGO2 send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
    value: 3
  - name: CompareOC1
    description: OC1REF signal is used as TRGO2
    value: 4
  - name: CompareOC2
    description: OC2REF signal is used as TRGO2
    value: 5
  - name: CompareOC3
    description: OC3REF signal is used as TRGO2
    value: 6
  - name: CompareOC4
    description: OC4REF signal is used as TRGO2
    value: 7
  - name: CompareOC5
    description: OC5REF signal is used as TRGO2
    value: 8
  - name: CompareOC6
    description: OC6REF signal is used as TRGO2
    value: 9
  - name: ComparePulse_OC4
    description: OC4REF rising or falling edges generate pulses on TRGO2
    value: 10
  - name: ComparePulse_OC6
    description: OC6REF rising or falling edges generate pulses on TRGO2
    value: 11
  - name: ComparePulse_OC4_Or_OC6_Rising
    description: OC4REF or OC6REF rising edges generate pulses on TRGO2
    value: 12
  - name: ComparePulse_OC4_Rising_Or_OC6_Falling
    description: OC4REF rising or OC6REF falling edges generate pulses on TRGO2
    value: 13
  - name: ComparePulse_OC5_Or_OC6_Rising
    description: OC5REF or OC6REF rising edges generate pulses on TRGO2
    value: 14
  - name: ComparePulse_OC5_Rising_Or_OC6_Falling
    description: OC5REF rising or OC6REF falling edges generate pulses on TRGO2
    value: 15
enum/MSM:
  bit_size: 1
  variants:
  - name: NoSync
    description: No action
    value: 0
  - name: Sync
    description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
    value: 1
enum/OCM:
  bit_size: 3
  variants:
  - name: Frozen
    description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
    value: 0
  - name: ActiveOnMatch
    description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
    value: 1
  - name: InactiveOnMatch
    description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
    value: 2
  - name: Toggle
    description: OCyREF toggles when TIMx_CNT=TIMx_CCRy
    value: 3
  - name: ForceInactive
    description: OCyREF is forced low
    value: 4
  - name: ForceActive
    description: OCyREF is forced high
    value: 5
  - name: PwmMode1
    description: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
    value: 6
  - name: PwmMode2
    description: Inversely to PwmMode1
    value: 7
enum/OSSI:
  bit_size: 1
  variants:
  - name: Disabled
    description: When inactive, OC/OCN outputs are disabled
    value: 0
  - name: IdleLevel
    description: When inactive, OC/OCN outputs are forced to idle level
    value: 1
enum/OSSR:
  bit_size: 1
  variants:
  - name: Disabled
    description: When inactive, OC/OCN outputs are disabled
    value: 0
  - name: IdleLevel
    description: When inactive, OC/OCN outputs are enabled with their inactive level
    value: 1
enum/SMS:
  bit_size: 4
  variants:
  - name: Disabled
    description: Slave mode disabled - if CEN = '1' then the prescaler is clocked directly by the internal clock.
    value: 0
  - name: Encoder_Mode_1
    description: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
    value: 1
  - name: Encoder_Mode_2
    description: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
    value: 2
  - name: Encoder_Mode_3
    description: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
    value: 3
  - name: Reset_Mode
    description: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
    value: 4
  - name: Gated_Mode
    description: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
    value: 5
  - name: Trigger_Mode
    description: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
    value: 6
  - name: Ext_Clock_Mode
    description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
    value: 7
  - name: Combined_Reset_Trigger
    description: Rising edge of the selected trigger input (tim_trgi) reinitializes the counter, generates an update of the registers and starts the counter.
    value: 8
enum/TI1S:
  bit_size: 1
  variants:
  - name: Normal
    description: The TIMx_CH1 pin is connected to TI1 input
    value: 0
  - name: XOR
    description: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
    value: 1
enum/TS:
  bit_size: 5
  variants:
  - name: ITR0
    description: Internal Trigger 0
    value: 0
  - name: ITR1
    description: Internal Trigger 1
    value: 1
  - name: ITR2
    description: Internal Trigger 2
    value: 2
  - name: ITR3
    description: Internal Trigger 3
    value: 3
  - name: TI1F_ED
    description: TI1 Edge Detector
    value: 4
  - name: TI1FP1
    description: Filtered Timer Input 1
    value: 5
  - name: TI2FP2
    description: Filtered Timer Input 2
    value: 6
  - name: ETRF
    description: External Trigger input
    value: 7
enum/URS:
  bit_size: 1
  variants:
  - name: AnyEvent
    description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
    value: 0
  - name: CounterOnly
    description: Only counter overflow/underflow generates an update interrupt or DMA request
    value: 1