guangzong/stm32-data
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
stm32-data/data/registers/dsihost_u5.yaml
JuliDi 804326f93f
add dsihost for u5 chip family
2024-04-15 09:20:50 +02:00

1719 lines
72 KiB
YAML
Raw Blame History

This file contains invisible Unicode characters

This file contains invisible Unicode characters that are indistinguishable to humans but may be processed differently by a computer. If you think that this is intentional, you can safely ignore this warning. Use the Escape button to reveal them.

block/DSIHOST:
description: DSI Host.
items:
- name: VR
description: DSI Host version register.
byte_offset: 0
fieldset: VR
- name: CR
description: DSI Host control register.
byte_offset: 4
fieldset: CR
- name: CCR
description: DSI Host clock control register.
byte_offset: 8
fieldset: CCR
- name: LVCIDR
description: DSI Host LTDC VCID register.
byte_offset: 12
fieldset: LVCIDR
- name: LCOLCR
description: DSI Host LTDC color coding register.
byte_offset: 16
fieldset: LCOLCR
- name: LPCR
description: DSI Host LTDC polarity configuration register.
byte_offset: 20
fieldset: LPCR
- name: LPMCR
description: DSI Host low-power mode configuration register.
byte_offset: 24
fieldset: LPMCR
- name: PCR
description: DSI Host protocol configuration register.
byte_offset: 44
fieldset: PCR
- name: GVCIDR
description: DSI Host generic VCID register.
byte_offset: 48
fieldset: GVCIDR
- name: MCR
description: DSI Host mode configuration register.
byte_offset: 52
fieldset: MCR
- name: VMCR
description: DSI Host video mode configuration register.
byte_offset: 56
fieldset: VMCR
- name: VPCR
description: DSI Host video packet configuration register.
byte_offset: 60
fieldset: VPCR
- name: VCCR
description: DSI Host video chunks configuration register.
byte_offset: 64
fieldset: VCCR
- name: VNPCR
description: DSI Host video null packet configuration register.
byte_offset: 68
fieldset: VNPCR
- name: VHSACR
description: DSI Host video HSA configuration register.
byte_offset: 72
fieldset: VHSACR
- name: VHBPCR
description: DSI Host video HBP configuration register.
byte_offset: 76
fieldset: VHBPCR
- name: VLCR
description: DSI Host video line configuration register.
byte_offset: 80
fieldset: VLCR
- name: VVSACR
description: DSI Host video VSA configuration register.
byte_offset: 84
fieldset: VVSACR
- name: VVBPCR
description: DSI Host video VBP configuration register.
byte_offset: 88
fieldset: VVBPCR
- name: VVFPCR
description: DSI Host video VFP configuration register.
byte_offset: 92
fieldset: VVFPCR
- name: VVACR
description: DSI Host video VA configuration register.
byte_offset: 96
fieldset: VVACR
- name: LCCR
description: DSI Host LTDC command configuration register.
byte_offset: 100
fieldset: LCCR
- name: CMCR
description: DSI Host command mode configuration register.
byte_offset: 104
fieldset: CMCR
- name: GHCR
description: DSI Host generic header configuration register.
byte_offset: 108
fieldset: GHCR
- name: GPDR
description: DSI Host generic payload data register.
byte_offset: 112
fieldset: GPDR
- name: GPSR
description: DSI Host generic packet status register.
byte_offset: 116
fieldset: GPSR
- name: TCCR0
description: DSI Host timeout counter configuration register 0.
byte_offset: 120
fieldset: TCCR0
- name: TCCR1
description: DSI Host timeout counter configuration register 1.
byte_offset: 124
fieldset: TCCR1
- name: TCCR2
description: DSI Host timeout counter configuration register 2.
byte_offset: 128
fieldset: TCCR2
- name: TCCR3
description: DSI Host timeout counter configuration register 3.
byte_offset: 132
fieldset: TCCR3
- name: TCCR4
description: DSI Host timeout counter configuration register 4.
byte_offset: 136
fieldset: TCCR4
- name: TCCR5
description: DSI Host timeout counter configuration register 5.
byte_offset: 140
fieldset: TCCR5
- name: CLCR
description: DSI Host clock lane configuration register.
byte_offset: 148
fieldset: CLCR
- name: CLTCR
description: DSI Host clock lane timer configuration register.
byte_offset: 152
fieldset: CLTCR
- name: DLTCR
description: DSI Host data lane timer configuration register.
byte_offset: 156
fieldset: DLTCR
- name: PCTLR
description: DSI Host PHY control register.
byte_offset: 160
fieldset: PCTLR
- name: PCONFR
description: DSI Host PHY configuration register.
byte_offset: 164
fieldset: PCONFR
- name: PUCR
description: DSI Host PHY ULPS control register.
byte_offset: 168
fieldset: PUCR
- name: PTTCR
description: DSI Host PHY TX triggers configuration register.
byte_offset: 172
fieldset: PTTCR
- name: PSR
description: DSI Host PHY status register.
byte_offset: 176
fieldset: PSR
- name: ISR0
description: DSI Host interrupt and status register 0.
byte_offset: 188
fieldset: ISR0
- name: ISR1
description: DSI Host interrupt and status register 1.
byte_offset: 192
fieldset: ISR1
- name: IER0
description: DSI Host interrupt enable register 0.
byte_offset: 196
fieldset: IER0
- name: IER1
description: DSI Host interrupt enable register 1.
byte_offset: 200
fieldset: IER1
- name: FIR0
description: DSI Host force interrupt register 0.
byte_offset: 216
fieldset: FIR0
- name: FIR1
description: DSI Host force interrupt register 1.
byte_offset: 220
fieldset: FIR1
- name: DLTRCR
description: DSI Host data lane timer read configuration register.
byte_offset: 244
fieldset: DLTRCR
- name: VSCR
description: DSI Host video shadow control register.
byte_offset: 256
fieldset: VSCR
- name: LCVCIDR
description: DSI Host LTDC current VCID register.
byte_offset: 268
fieldset: LCVCIDR
- name: LCCCR
description: DSI Host LTDC current color coding register.
byte_offset: 272
fieldset: LCCCR
- name: LPMCCR
description: DSI Host low-power mode current configuration register.
byte_offset: 280
fieldset: LPMCCR
- name: VMCCR
description: DSI Host video mode current configuration register.
byte_offset: 312
fieldset: VMCCR
- name: VPCCR
description: DSI Host video packet current configuration register.
byte_offset: 316
fieldset: VPCCR
- name: VCCCR
description: DSI Host video chunks current configuration register.
byte_offset: 320
fieldset: VCCCR
- name: VNPCCR
description: DSI Host video null packet current configuration register.
byte_offset: 324
fieldset: VNPCCR
- name: VHSACCR
description: DSI Host video HSA current configuration register.
byte_offset: 328
fieldset: VHSACCR
- name: VHBPCCR
description: DSI Host video HBP current configuration register.
byte_offset: 332
fieldset: VHBPCCR
- name: VLCCR
description: DSI Host video line current configuration register.
byte_offset: 336
fieldset: VLCCR
- name: VVSACCR
description: DSI Host video VSA current configuration register.
byte_offset: 340
fieldset: VVSACCR
- name: VVBPCCR
description: DSI Host video VBP current configuration register.
byte_offset: 344
fieldset: VVBPCCR
- name: VVFPCCR
description: DSI Host video VFP current configuration register.
byte_offset: 348
fieldset: VVFPCCR
- name: VVACCR
description: DSI Host video VA current configuration register.
byte_offset: 352
fieldset: VVACCR
- name: FBSR
description: DSI Host FIFO and buffer status register.
byte_offset: 360
fieldset: FBSR
- name: WCFGR
description: DSI Wrapper configuration register.
byte_offset: 1024
fieldset: WCFGR
- name: WCR
description: DSI Wrapper control register.
byte_offset: 1028
fieldset: WCR
- name: WIER
description: DSI Wrapper interrupt enable register.
byte_offset: 1032
fieldset: WIER
- name: WISR
description: DSI Wrapper interrupt and status register.
byte_offset: 1036
fieldset: WISR
- name: WIFCR
description: DSI Wrapper interrupt flag clear register.
byte_offset: 1040
fieldset: WIFCR
- name: WPCR0
description: DSI Wrapper PHY configuration register 0.
byte_offset: 1048
fieldset: WPCR0
- name: WRPCR
description: DSI Wrapper regulator and PLL control register.
byte_offset: 1072
fieldset: WRPCR
- name: BCFGR
description: DSI bias configuration register.
byte_offset: 2056
fieldset: BCFGR
- name: DPCBCR
description: DSI D-PHY clock band control register.
byte_offset: 3076
fieldset: DPCBCR
- name: DPCSRCR
description: DSI D-PHY clock skew rate control register.
byte_offset: 3124
fieldset: DPCSRCR
- name: DPDL0BCR
description: DSI D-PHY data lane 0 band control register.
byte_offset: 3184
fieldset: DPDL0BCR
- name: DPDL0SRCR
description: DSI D-PHY data lane 0 skew rate control register.
byte_offset: 3232
fieldset: DPDL0SRCR
- name: DPDL1BCR
description: DSI D-PHY data lane 1 band control register.
byte_offset: 3336
fieldset: DPDL1BCR
- name: DPDL1SRCR
description: DSI D-PHY data lane 1 skew rate control register.
byte_offset: 3384
fieldset: DPDL1SRCR
fieldset/BCFGR:
description: DSI bias configuration register.
fields:
- name: PWRUP
description: Power-up This bit powers-up the reference bias for the MIPI D-PHY.
bit_offset: 6
bit_size: 1
fieldset/CCR:
description: DSI Host clock control register.
fields:
- name: TXECKDIV
description: TX escape clock division This field indicates the division factor for the TX escape clock source (lanebyteclk). The values 0 and 1 stop the TX_ESC clock generation.
bit_offset: 0
bit_size: 8
- name: TOCKDIV
description: Timeout clock division This field indicates the division factor for the timeout clock used as the timing unit in the configuration of HS to LP and LP to HS transition error.
bit_offset: 8
bit_size: 8
fieldset/CLCR:
description: DSI Host clock lane configuration register.
fields:
- name: DPCC
description: D-PHY clock control This bit controls the D-PHY clock state:.
bit_offset: 0
bit_size: 1
- name: ACR
description: Automatic clock lane control This bit enables the automatic mechanism to stop providing clock in the clock lane when time allows.
bit_offset: 1
bit_size: 1
fieldset/CLTCR:
description: DSI Host clock lane timer configuration register.
fields:
- name: LP2HS_TIME
description: "Low-power to high-speed time This field configures the maximum time that the D-PHY clock lane takes to go from lowâ\x80\x91power to high-speed transmission measured in lane byte clock cycles."
bit_offset: 0
bit_size: 10
- name: HS2LP_TIME
description: "High-speed to low-power time This field configures the maximum time that the D-PHY clock lane takes to go from highâ\x80\x91speed to low-power transmission measured in lane byte clock cycles."
bit_offset: 16
bit_size: 10
fieldset/CMCR:
description: DSI Host command mode configuration register.
fields:
- name: TEARE
description: Tearing effect acknowledge request enable This bit enables the tearing effect acknowledge request:.
bit_offset: 0
bit_size: 1
- name: ARE
description: Acknowledge request enable This bit enables the acknowledge request after each packet transmission:.
bit_offset: 1
bit_size: 1
- name: GSW0TX
description: Generic short write zero parameters transmission This bit configures the generic short write packet with zero parameters command transmission type:.
bit_offset: 8
bit_size: 1
- name: GSW1TX
description: Generic short write one parameters transmission This bit configures the generic short write packet with one parameters command transmission type:.
bit_offset: 9
bit_size: 1
- name: GSW2TX
description: Generic short write two parameters transmission This bit configures the generic short write packet with two parameters command transmission type:.
bit_offset: 10
bit_size: 1
- name: GSR0TX
description: Generic short read zero parameters transmission This bit configures the generic short read packet with zero parameters command transmission type:.
bit_offset: 11
bit_size: 1
- name: GSR1TX
description: Generic short read one parameters transmission This bit configures the generic short read packet with one parameters command transmission type:.
bit_offset: 12
bit_size: 1
- name: GSR2TX
description: Generic short read two parameters transmission This bit configures the generic short read packet with two parameters command transmission type:.
bit_offset: 13
bit_size: 1
- name: GLWTX
description: Generic long write transmission This bit configures the generic long write packet command transmission type :.
bit_offset: 14
bit_size: 1
- name: DSW0TX
description: DCS short write zero parameter transmission This bit configures the DCS short write packet with zero parameter command transmission type:.
bit_offset: 16
bit_size: 1
- name: DSW1TX
description: DCS short read one parameter transmission This bit configures the DCS short read packet with one parameter command transmission type:.
bit_offset: 17
bit_size: 1
- name: DSR0TX
description: DCS short read zero parameter transmission This bit configures the DCS short read packet with zero parameter command transmission type:.
bit_offset: 18
bit_size: 1
- name: DLWTX
description: DCS long write transmission This bit configures the DCS long write packet command transmission type:.
bit_offset: 19
bit_size: 1
- name: MRDPS
description: Maximum read packet size This bit configures the maximum read packet size command transmission type:.
bit_offset: 24
bit_size: 1
fieldset/CR:
description: DSI Host control register.
fields:
- name: EN
description: Enable This bit configures the DSI Host in either power-up mode or to reset.
bit_offset: 0
bit_size: 1
fieldset/DLTCR:
description: DSI Host data lane timer configuration register.
fields:
- name: LP2HS_TIME
description: Low-power to high-speed time This field configures the maximum time that the D-PHY data lanes take to go from low-power to high-speed transmission measured in lane byte clock cycles.
bit_offset: 0
bit_size: 10
- name: HS2LP_TIME
description: High-speed to low-power time This field configures the maximum time that the D-PHY data lanes take to go from high-speed to low-power transmission measured in lane byte clock cycles.
bit_offset: 16
bit_size: 10
fieldset/DLTRCR:
description: DSI Host data lane timer read configuration register.
fields:
- name: MRD_TIME
description: Maximum read time This field configures the maximum time required to perform a read command in lane byte clock cycles. This register can only be modified when no read command is in progress.
bit_offset: 0
bit_size: 15
fieldset/DPCBCR:
description: DSI D-PHY clock band control register.
fields:
- name: BC
description: "Band control This field selects the frequency band used by the D-PHY. Others: Reserved."
bit_offset: 3
bit_size: 5
fieldset/DPCSRCR:
description: DSI D-PHY clock skew rate control register.
fields:
- name: SRC
description: "Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved."
bit_offset: 0
bit_size: 8
fieldset/DPDL0BCR:
description: DSI D-PHY data lane 0 band control register.
fields:
- name: BC
description: "Band control This field selects the frequency band used by the D-PHY. Others: Reserved."
bit_offset: 0
bit_size: 5
fieldset/DPDL0SRCR:
description: DSI D-PHY data lane 0 skew rate control register.
fields:
- name: SRC
description: "Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved."
bit_offset: 0
bit_size: 8
fieldset/DPDL1BCR:
description: DSI D-PHY data lane 1 band control register.
fields:
- name: BC
description: "Band control This field selects the frequency band used by the D-PHY. Others: Reserved."
bit_offset: 0
bit_size: 5
fieldset/DPDL1SRCR:
description: DSI D-PHY data lane 1 skew rate control register.
fields:
- name: SRC
description: "Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved."
bit_offset: 0
bit_size: 8
fieldset/FBSR:
description: DSI Host FIFO and buffer status register.
fields:
- name: VCWFE
description: Video mode command write FIFO empty This bit indicates the empty status of the video mode write command FIFO:.
bit_offset: 0
bit_size: 1
- name: VCWFF
description: Video mode command write FIFO full This bit indicates the full status of the video mode write command FIFO:.
bit_offset: 1
bit_size: 1
- name: VPWFE
description: Video mode payload write FIFO empty This bit indicates the empty status of the video mode write payload FIFO:.
bit_offset: 2
bit_size: 1
- name: VPWFF
description: Video mode payload write FIFO full This bit indicates the full status of the video mode write payload FIFO:.
bit_offset: 3
bit_size: 1
- name: ACWFE
description: Adapted command mode command write FIFO empty This bit indicates the empty status of the adapted command mode write command FIFO:.
bit_offset: 4
bit_size: 1
- name: ACWFF
description: Adapted command mode command write FIFO full This bit indicates the full status of the adapted command mode write command FIFO:.
bit_offset: 5
bit_size: 1
- name: APWFE
description: Adapted command mode payload write FIFO empty This bit indicates the empty status of the adapted command mode write payload FIFO:.
bit_offset: 6
bit_size: 1
- name: APWFF
description: Adapted command mode payload write FIFO full This bit indicates the full status of the adapted command mode write payload FIFO:.
bit_offset: 7
bit_size: 1
- name: VPBE
description: Video mode payload buffer empty This bit indicates the empty status of the video mode payload internal buffer:.
bit_offset: 16
bit_size: 1
- name: VPBF
description: Video mode payload buffer full This bit indicates the full status of the video mode payload internal buffer:.
bit_offset: 17
bit_size: 1
- name: ACBE
description: Adapted command mode command buffer empty This bit indicates the empty status of the adapted command mode command internal buffer:.
bit_offset: 20
bit_size: 1
- name: ACBF
description: Adapted command mode command buffer full This bit indicates the full status of the adapted command mode command internal buffer:.
bit_offset: 21
bit_size: 1
- name: APBE
description: Adapted command mode payload buffer empty This bit indicates the empty status of the adapted command mode payload internal buffer:.
bit_offset: 22
bit_size: 1
- name: APBF
description: Adapted command mode payload buffer full This bit indicates the full status of the adapted command mode payload internal buffer:.
bit_offset: 23
bit_size: 1
fieldset/FIR0:
description: DSI Host force interrupt register 0.
fields:
- name: FAE0
description: Force acknowledge error 0 Writing one to this bit forces an acknowledge error 0.
bit_offset: 0
bit_size: 1
- name: FAE1
description: Force acknowledge error 1 Writing one to this bit forces an acknowledge error 1.
bit_offset: 1
bit_size: 1
- name: FAE2
description: Force acknowledge error 2 Writing one to this bit forces an acknowledge error 2.
bit_offset: 2
bit_size: 1
- name: FAE3
description: Force acknowledge error 3 Writing one to this bit forces an acknowledge error 3.
bit_offset: 3
bit_size: 1
- name: FAE4
description: Force acknowledge error 4 Writing one to this bit forces an acknowledge error 4.
bit_offset: 4
bit_size: 1
- name: FAE5
description: Force acknowledge error 5 Writing one to this bit forces an acknowledge error 5.
bit_offset: 5
bit_size: 1
- name: FAE6
description: Force acknowledge error 6 Writing one to this bit forces an acknowledge error 6.
bit_offset: 6
bit_size: 1
- name: FAE7
description: Force acknowledge error 7 Writing one to this bit forces an acknowledge error 7.
bit_offset: 7
bit_size: 1
- name: FAE8
description: Force acknowledge error 8 Writing one to this bit forces an acknowledge error 8.
bit_offset: 8
bit_size: 1
- name: FAE9
description: Force acknowledge error 9 Writing one to this bit forces an acknowledge error 9.
bit_offset: 9
bit_size: 1
- name: FAE10
description: Force acknowledge error 10 Writing one to this bit forces an acknowledge error 10.
bit_offset: 10
bit_size: 1
- name: FAE11
description: Force acknowledge error 11 Writing one to this bit forces an acknowledge error 11.
bit_offset: 11
bit_size: 1
- name: FAE12
description: Force acknowledge error 12 Writing one to this bit forces an acknowledge error 12.
bit_offset: 12
bit_size: 1
- name: FAE13
description: Force acknowledge error 13 Writing one to this bit forces an acknowledge error 13.
bit_offset: 13
bit_size: 1
- name: FAE14
description: Force acknowledge error 14 Writing one to this bit forces an acknowledge error 14.
bit_offset: 14
bit_size: 1
- name: FAE15
description: Force acknowledge error 15 Writing one to this bit forces an acknowledge error 15.
bit_offset: 15
bit_size: 1
- name: FPE0
description: Force PHY error 0 Writing one to this bit forces a PHY error 0.
bit_offset: 16
bit_size: 1
- name: FPE1
description: Force PHY error 1 Writing one to this bit forces a PHY error 1.
bit_offset: 17
bit_size: 1
- name: FPE2
description: Force PHY error 2 Writing one to this bit forces a PHY error 2.
bit_offset: 18
bit_size: 1
- name: FPE3
description: Force PHY error 3 Writing one to this bit forces a PHY error 3.
bit_offset: 19
bit_size: 1
- name: FPE4
description: Force PHY error 4 Writing one to this bit forces a PHY error 4.
bit_offset: 20
bit_size: 1
fieldset/FIR1:
description: DSI Host force interrupt register 1.
fields:
- name: FTOHSTX
description: Force timeout high-speed transmission Writing one to this bit forces a timeout high-speed transmission.
bit_offset: 0
bit_size: 1
- name: FTOLPRX
description: Force timeout low-power reception Writing one to this bit forces a timeout low-power reception.
bit_offset: 1
bit_size: 1
- name: FECCSE
description: Force ECC single-bit error Writing one to this bit forces a ECC single-bit error.
bit_offset: 2
bit_size: 1
- name: FECCME
description: Force ECC multi-bit error Writing one to this bit forces a ECC multi-bit error.
bit_offset: 3
bit_size: 1
- name: FCRCE
description: Force CRC error Writing one to this bit forces a CRC error.
bit_offset: 4
bit_size: 1
- name: FPSE
description: Force packet size error Writing one to this bit forces a packet size error.
bit_offset: 5
bit_size: 1
- name: FEOTPE
description: Force EoTp error Writing one to this bit forces a EoTp error.
bit_offset: 6
bit_size: 1
- name: FLPWRE
description: Force LTDC payload write error Writing one to this bit forces a LTDC payload write error.
bit_offset: 7
bit_size: 1
- name: FGCWRE
description: Force generic command write error Writing one to this bit forces a generic command write error.
bit_offset: 8
bit_size: 1
- name: FGPWRE
description: Force generic payload write error Writing one to this bit forces a generic payload write error.
bit_offset: 9
bit_size: 1
- name: FGPTXE
description: Force generic payload transmit error Writing one to this bit forces a generic payload transmit error.
bit_offset: 10
bit_size: 1
- name: FGPRDE
description: Force generic payload read error Writing one to this bit forces a generic payload read error.
bit_offset: 11
bit_size: 1
- name: FGPRXE
description: Force generic payload receive error Writing one to this bit forces a generic payload receive error.
bit_offset: 12
bit_size: 1
- name: FPBUE
description: Force payload buffer underflow error Writing one to this bit forces a payload undrflow error.
bit_offset: 19
bit_size: 1
fieldset/GHCR:
description: DSI Host generic header configuration register.
fields:
- name: DT
description: Type This field configures the packet data type of the header packet.
bit_offset: 0
bit_size: 6
- name: VCID
description: Channel This field configures the virtual channel ID of the header packet.
bit_offset: 6
bit_size: 2
- name: WCLSB
description: WordCount LSB This field configures the less significant byte of the header packet word count for long packets, or data 0 for short packets.
bit_offset: 8
bit_size: 8
- name: WCMSB
description: WordCount MSB This field configures the most significant byte of the header packet's word count for long packets, or data 1 for short packets.
bit_offset: 16
bit_size: 8
fieldset/GPDR:
description: DSI Host generic payload data register.
fields:
- name: DATA1
description: Payload byte 1 This field indicates the byte 1 of the packet payload.
bit_offset: 0
bit_size: 8
- name: DATA2
description: Payload byte 2 This field indicates the byte 2 of the packet payload.
bit_offset: 8
bit_size: 8
- name: DATA3
description: Payload byte 3 This field indicates the byte 3 of the packet payload.
bit_offset: 16
bit_size: 8
- name: DATA4
description: Payload byte 4 This field indicates the byte 4 of the packet payload.
bit_offset: 24
bit_size: 8
fieldset/GPSR:
description: DSI Host generic packet status register.
fields:
- name: CMDFE
description: Command FIFO empty This bit indicates the empty status of the generic command FIFO:.
bit_offset: 0
bit_size: 1
- name: CMDFF
description: Command FIFO full This bit indicates the full status of the generic command FIFO:.
bit_offset: 1
bit_size: 1
- name: PWRFE
description: Payload write FIFO empty This bit indicates the empty status of the generic write payload FIFO:.
bit_offset: 2
bit_size: 1
- name: PWRFF
description: Payload write FIFO full This bit indicates the full status of the generic write payload FIFO:.
bit_offset: 3
bit_size: 1
- name: PRDFE
description: Payload read FIFO empty This bit indicates the empty status of the generic read payload FIFO:.
bit_offset: 4
bit_size: 1
- name: PRDFF
description: Payload read FIFO full This bit indicates the full status of the generic read payload FIFO:.
bit_offset: 5
bit_size: 1
- name: RCB
description: Read command busy This bit is set when a read command is issued and cleared when the entire response is stored in the FIFO:.
bit_offset: 6
bit_size: 1
- name: CMDBE
description: Command buffer empty This bit indicates the empty status of the generic payload internal buffer:.
bit_offset: 16
bit_size: 1
- name: CMDBF
description: Command buffer full This bit indicates the full status of the generic command internal buffer:.
bit_offset: 17
bit_size: 1
- name: PBE
description: Payload buffer empty This bit indicates the empty status of the generic payload internal buffer:.
bit_offset: 18
bit_size: 1
- name: PBF
description: Payload buffer full This bit indicates the full status of the generic payload internal buffer:.
bit_offset: 19
bit_size: 1
fieldset/GVCIDR:
description: DSI Host generic VCID register.
fields:
- name: VCIDRX
description: Virtual channel ID for reception This field indicates the generic interface read-back virtual channel identification.
bit_offset: 0
bit_size: 2
- name: VCIDTX
description: Virtual channel ID for transmission This field indicates the generic interface virtual channel identification where the generic packet is automatically generated and transmitted.
bit_offset: 16
bit_size: 2
fieldset/IER0:
description: DSI Host interrupt enable register 0.
fields:
- name: AE0IE
description: Acknowledge error 0 interrupt enable This bit enables the interrupt generation on acknowledge error 0.
bit_offset: 0
bit_size: 1
- name: AE1IE
description: Acknowledge error 1 interrupt enable This bit enables the interrupt generation on acknowledge error 1.
bit_offset: 1
bit_size: 1
- name: AE2IE
description: Acknowledge error 2 interrupt enable This bit enables the interrupt generation on acknowledge error 2.
bit_offset: 2
bit_size: 1
- name: AE3IE
description: Acknowledge error 3 interrupt enable This bit enables the interrupt generation on acknowledge error 3.
bit_offset: 3
bit_size: 1
- name: AE4IE
description: Acknowledge error 4 interrupt enable This bit enables the interrupt generation on acknowledge error 4.
bit_offset: 4
bit_size: 1
- name: AE5IE
description: Acknowledge error 5 interrupt enable This bit enables the interrupt generation on acknowledge error 5.
bit_offset: 5
bit_size: 1
- name: AE6IE
description: Acknowledge error 6 interrupt enable This bit enables the interrupt generation on acknowledge error 6.
bit_offset: 6
bit_size: 1
- name: AE7IE
description: Acknowledge error 7 interrupt enable This bit enables the interrupt generation on acknowledge error 7.
bit_offset: 7
bit_size: 1
- name: AE8IE
description: Acknowledge error 8 interrupt enable This bit enables the interrupt generation on acknowledge error 8.
bit_offset: 8
bit_size: 1
- name: AE9IE
description: Acknowledge error 9 interrupt enable This bit enables the interrupt generation on acknowledge error 9.
bit_offset: 9
bit_size: 1
- name: AE10IE
description: Acknowledge error 10 interrupt enable This bit enables the interrupt generation on acknowledge error 10.
bit_offset: 10
bit_size: 1
- name: AE11IE
description: Acknowledge error 11 interrupt enable This bit enables the interrupt generation on acknowledge error 11.
bit_offset: 11
bit_size: 1
- name: AE12IE
description: Acknowledge error 12 interrupt enable This bit enables the interrupt generation on acknowledge error 12.
bit_offset: 12
bit_size: 1
- name: AE13IE
description: Acknowledge error 13 interrupt enable This bit enables the interrupt generation on acknowledge error 13.
bit_offset: 13
bit_size: 1
- name: AE14IE
description: Acknowledge error 14 interrupt enable This bit enables the interrupt generation on acknowledge error 14.
bit_offset: 14
bit_size: 1
- name: AE15IE
description: Acknowledge error 15 interrupt enable This bit enables the interrupt generation on acknowledge error 15.
bit_offset: 15
bit_size: 1
- name: PE0IE
description: PHY error 0 interrupt enable This bit enables the interrupt generation on PHY error 0.
bit_offset: 16
bit_size: 1
- name: PE1IE
description: PHY error 1 interrupt enable This bit enables the interrupt generation on PHY error 1.
bit_offset: 17
bit_size: 1
- name: PE2IE
description: PHY error 2 interrupt enable This bit enables the interrupt generation on PHY error 2.
bit_offset: 18
bit_size: 1
- name: PE3IE
description: PHY error 3 interrupt enable This bit enables the interrupt generation on PHY error 4.
bit_offset: 19
bit_size: 1
- name: PE4IE
description: PHY error 4 interrupt enable This bit enables the interrupt generation on PHY error 4.
bit_offset: 20
bit_size: 1
fieldset/IER1:
description: DSI Host interrupt enable register 1.
fields:
- name: TOHSTXIE
description: Timeout high-speed transmission interrupt enable This bit enables the interrupt generation on timeout high-speed transmission.
bit_offset: 0
bit_size: 1
- name: TOLPRXIE
description: Timeout low-power reception interrupt enable This bit enables the interrupt generation on timeout low-power reception.
bit_offset: 1
bit_size: 1
- name: ECCSEIE
description: ECC single-bit error interrupt enable This bit enables the interrupt generation on ECC single-bit error.
bit_offset: 2
bit_size: 1
- name: ECCMEIE
description: ECC multi-bit error interrupt enable This bit enables the interrupt generation on ECC multi-bit error.
bit_offset: 3
bit_size: 1
- name: CRCEIE
description: CRC error interrupt enable This bit enables the interrupt generation on CRC error.
bit_offset: 4
bit_size: 1
- name: PSEIE
description: Packet size error interrupt enable This bit enables the interrupt generation on packet size error.
bit_offset: 5
bit_size: 1
- name: EOTPEIE
description: EoTp error interrupt enable This bit enables the interrupt generation on EoTp error.
bit_offset: 6
bit_size: 1
- name: LPWREIE
description: LTDC payload write error interrupt enable This bit enables the interrupt generation on LTDC payload write error.
bit_offset: 7
bit_size: 1
- name: GCWREIE
description: Generic command write error interrupt enable This bit enables the interrupt generation on generic command write error.
bit_offset: 8
bit_size: 1
- name: GPWREIE
description: Generic payload write error interrupt enable This bit enables the interrupt generation on generic payload write error.
bit_offset: 9
bit_size: 1
- name: GPTXEIE
description: Generic payload transmit error interrupt enable This bit enables the interrupt generation on generic payload transmit error.
bit_offset: 10
bit_size: 1
- name: GPRDEIE
description: Generic payload read error interrupt enable This bit enables the interrupt generation on generic payload read error.
bit_offset: 11
bit_size: 1
- name: GPRXEIE
description: Generic payload receive error interrupt enable This bit enables the interrupt generation on generic payload receive error.
bit_offset: 12
bit_size: 1
- name: PBUEIE
description: Payload buffer underflow error interrupt enable This bit enables the interrupt generation on payload buffer underflow error.
bit_offset: 19
bit_size: 1
fieldset/ISR0:
description: DSI Host interrupt and status register 0.
fields:
- name: AE0
description: Acknowledge error 0 This bit retrieves the SoT error from the acknowledge error report.
bit_offset: 0
bit_size: 1
- name: AE1
description: Acknowledge error 1 This bit retrieves the SoT sync error from the acknowledge error report.
bit_offset: 1
bit_size: 1
- name: AE2
description: Acknowledge error 2 This bit retrieves the EoT sync error from the acknowledge error report.
bit_offset: 2
bit_size: 1
- name: AE3
description: Acknowledge error 3 This bit retrieves the escape mode entry command error from the acknowledge error report.
bit_offset: 3
bit_size: 1
- name: AE4
description: Acknowledge error 4 This bit retrieves the LP transmit sync error from the acknowledge error report.
bit_offset: 4
bit_size: 1
- name: AE5
description: Acknowledge error 5 This bit retrieves the peripheral timeout error from the acknowledge error report.
bit_offset: 5
bit_size: 1
- name: AE6
description: Acknowledge error 6 This bit retrieves the false control error from the acknowledge error report.
bit_offset: 6
bit_size: 1
- name: AE7
description: Acknowledge error 7 This bit retrieves the reserved (specific to the device) from the acknowledge error report.
bit_offset: 7
bit_size: 1
- name: AE8
description: Acknowledge error 8 This bit retrieves the ECC error, single-bit (detected and corrected) from the acknowledge error report.
bit_offset: 8
bit_size: 1
- name: AE9
description: Acknowledge error 9 This bit retrieves the ECC error, multi-bit (detected, not corrected) from the acknowledge error report.
bit_offset: 9
bit_size: 1
- name: AE10
description: Acknowledge error 10 This bit retrieves the checksum error (long packet only) from the acknowledge error report.
bit_offset: 10
bit_size: 1
- name: AE11
description: Acknowledge error 11 This bit retrieves the not recognized DSI data type from the acknowledge error report.
bit_offset: 11
bit_size: 1
- name: AE12
description: Acknowledge error 12 This bit retrieves the DSI VC ID Invalid from the acknowledge error report.
bit_offset: 12
bit_size: 1
- name: AE13
description: Acknowledge error 13 This bit retrieves the invalid transmission length from the acknowledge error report.
bit_offset: 13
bit_size: 1
- name: AE14
description: Acknowledge error 14 This bit retrieves the reserved (specific to the device) from the acknowledge error report.
bit_offset: 14
bit_size: 1
- name: AE15
description: Acknowledge error 15 This bit retrieves the DSI protocol violation from the acknowledge error report.
bit_offset: 15
bit_size: 1
- name: PE0
description: PHY error 0 This bit indicates the ErrEsc escape entry error from lane 0.
bit_offset: 16
bit_size: 1
- name: PE1
description: PHY error 1 This bit indicates the ErrSyncEsc low-power transmission synchronization error from lane 0.
bit_offset: 17
bit_size: 1
- name: PE2
description: PHY error 2 This bit indicates the ErrControl error from lane 0.
bit_offset: 18
bit_size: 1
- name: PE3
description: PHY error 3 This bit indicates the LP0 contention error ErrContentionLP0 from lane 0.
bit_offset: 19
bit_size: 1
- name: PE4
description: PHY error 4 This bit indicates the LP1 contention error ErrContentionLP1 from lane 0.
bit_offset: 20
bit_size: 1
fieldset/ISR1:
description: DSI Host interrupt and status register 1.
fields:
- name: TOHSTX
description: Timeout high-speed transmission This bit indicates that the high-speed transmission timeout counter reached the end and contention is detected.
bit_offset: 0
bit_size: 1
- name: TOLPRX
description: Timeout low-power reception This bit indicates that the low-power reception timeout counter reached the end and contention is detected.
bit_offset: 1
bit_size: 1
- name: ECCSE
description: ECC single-bit error This bit indicates that the ECC single error is detected and corrected in a received packet.
bit_offset: 2
bit_size: 1
- name: ECCME
description: ECC multi-bit error This bit indicates that the ECC multiple error is detected in a received packet.
bit_offset: 3
bit_size: 1
- name: CRCE
description: CRC error This bit indicates that the CRC error is detected in the received packet payload.
bit_offset: 4
bit_size: 1
- name: PSE
description: Packet size error This bit indicates that the packet size error is detected during the packet reception.
bit_offset: 5
bit_size: 1
- name: EOTPE
description: EoTp error This bit indicates that the EoTp packet is not received at the end of the incoming peripheral transmission.
bit_offset: 6
bit_size: 1
- name: LPWRE
description: LTDC payload write error This bit indicates that during a DPI pixel line storage, the payload FIFO becomes full and the data stored is corrupted.
bit_offset: 7
bit_size: 1
- name: GCWRE
description: Generic command write error This bit indicates that the system tried to write a command through the generic interface and the FIFO is full. Therefore, the command is not written.
bit_offset: 8
bit_size: 1
- name: GPWRE
description: Generic payload write error This bit indicates that the system tried to write a payload data through the generic interface and the FIFO is full. Therefore, the payload is not written.
bit_offset: 9
bit_size: 1
- name: GPTXE
description: Generic payload transmit error This bit indicates that during a generic interface packet build, the payload FIFO becomes empty and corrupt data is sent.
bit_offset: 10
bit_size: 1
- name: GPRDE
description: Generic payload read error This bit indicates that during a DCS read data, the payload FIFO becomes empty and the data sent to the interface is corrupted.
bit_offset: 11
bit_size: 1
- name: GPRXE
description: Generic payload receive error This bit indicates that during a generic interface packet read back, the payload FIFO becomes full and the received data is corrupted.
bit_offset: 12
bit_size: 1
- name: PBUE
description: Payload buffer underflow error This bit indicates that underflow has occurred when reading payload to build DSI packet for video mode.
bit_offset: 19
bit_size: 1
fieldset/LCCCR:
description: DSI Host LTDC current color coding register.
fields:
- name: COLC
description: "Color coding This field returns the current LTDC interface color coding. 0110-1111: reserved If LTDC interface in command mode is chosen and currently works in the command mode (CMDM=1), then 0110-1111: 24-bit."
bit_offset: 0
bit_size: 4
- name: LPE
description: Loosely packed enable This bit returns the current state of the loosely packed variant to 18-bit configurations.
bit_offset: 8
bit_size: 1
fieldset/LCCR:
description: DSI Host LTDC command configuration register.
fields:
- name: CMDSIZE
description: Command size This field configures the maximum allowed size for an LTDC write memory command, measured in pixels. Automatic partitioning of data obtained from LTDC is permanently enabled.
bit_offset: 0
bit_size: 16
fieldset/LCOLCR:
description: DSI Host LTDC color coding register.
fields:
- name: COLC
description: "Color coding This field configures the DPI color coding. Others: Reserved."
bit_offset: 0
bit_size: 4
- name: LPE
description: Loosely packet enable This bit enables the loosely packed variant to 18-bit configuration.
bit_offset: 8
bit_size: 1
fieldset/LCVCIDR:
description: DSI Host LTDC current VCID register.
fields:
- name: VCID
description: Virtual channel ID This field returns the virtual channel ID for the LTDC interface.
bit_offset: 0
bit_size: 2
fieldset/LPCR:
description: DSI Host LTDC polarity configuration register.
fields:
- name: DEP
description: Data enable polarity This bit configures the polarity of data enable pin.
bit_offset: 0
bit_size: 1
- name: VSP
description: VSYNC polarity This bit configures the polarity of VSYNC pin.
bit_offset: 1
bit_size: 1
- name: HSP
description: HSYNC polarity This bit configures the polarity of HSYNC pin.
bit_offset: 2
bit_size: 1
fieldset/LPMCCR:
description: DSI Host low-power mode current configuration register.
fields:
- name: VLPSIZE
description: VACT largest packet size This field returns the current size, in bytes, of the largest packet that can fit in a line during VACT regions, for the transmission of commands in low-power mode.
bit_offset: 0
bit_size: 8
- name: LPSIZE
description: Largest packet size This field is returns the current size, in bytes, of the largest packet that can fit in a line during VSA, VBP and VFP regions, for the transmission of commands in low-power mode.
bit_offset: 16
bit_size: 8
fieldset/LPMCR:
description: DSI Host low-power mode configuration register.
fields:
- name: VLPSIZE
description: VACT largest packet size This field is used for the transmission of commands in low-power mode. It defines the size, in bytes, of the largest packet that can fit in a line during VACT regions.
bit_offset: 0
bit_size: 8
- name: LPSIZE
description: Largest packet size This field is used for the transmission of commands in low-power mode. It defines the size, in bytes, of the largest packet that can fit in a line during VSA, VBP and VFP regions.
bit_offset: 16
bit_size: 8
fieldset/LVCIDR:
description: DSI Host LTDC VCID register.
fields:
- name: VCID
description: Virtual channel ID These bits configure the virtual channel ID for the LTDC interface traffic.
bit_offset: 0
bit_size: 2
fieldset/MCR:
description: DSI Host mode configuration register.
fields:
- name: CMDM
description: Command mode This bit configures the DSI Host in either video or command mode.
bit_offset: 0
bit_size: 1
fieldset/PCONFR:
description: DSI Host PHY configuration register.
fields:
- name: NL
description: "Number of lanes This field configures the number of active data lanes: Others: Reserved."
bit_offset: 0
bit_size: 2
- name: SW_TIME
description: Stop wait time This field configures the minimum wait period to request a high-speed transmission after the Stop state.
bit_offset: 8
bit_size: 8
fieldset/PCR:
description: DSI Host protocol configuration register.
fields:
- name: ETTXE
description: EoTp transmission enable This bit enables the EoTP transmission.
bit_offset: 0
bit_size: 1
- name: ETRXE
description: EoTp reception enable This bit enables the EoTp reception.
bit_offset: 1
bit_size: 1
- name: BTAE
description: Bus-turn-around enable This bit enables the bus-turn-around (BTA) request.
bit_offset: 2
bit_size: 1
- name: ECCRXE
description: ECC reception enable This bit enables the ECC reception, error correction and reporting.
bit_offset: 3
bit_size: 1
- name: CRCRXE
description: CRC reception enable This bit enables the CRC reception and error reporting.
bit_offset: 4
bit_size: 1
- name: ETTXLPE
description: EoTp transmission in low-power enable This bit enables the EoTP transmission in low-power.
bit_offset: 5
bit_size: 1
fieldset/PCTLR:
description: DSI Host PHY control register.
fields:
- name: DEN
description: Digital enable When set to 0, this bit places the digital section of the D-PHY in the reset state.
bit_offset: 1
bit_size: 1
- name: CKE
description: Clock enable This bit enables the D-PHY clock lane module:.
bit_offset: 2
bit_size: 1
fieldset/PSR:
description: DSI Host PHY status register.
fields:
- name: PD
description: PHY direction This bit indicates the status of phydirection D-PHY signal.
bit_offset: 1
bit_size: 1
- name: PSSC
description: PHY stop state clock lane This bit indicates the status of phystopstateclklane D-PHY signal.
bit_offset: 2
bit_size: 1
- name: UANC
description: ULPS active not clock lane This bit indicates the status of ulpsactivenotclklane D-PHY signal.
bit_offset: 3
bit_size: 1
- name: PSS0
description: PHY stop state lane 0 This bit indicates the status of phystopstate0lane D-PHY signal.
bit_offset: 4
bit_size: 1
- name: UAN0
description: ULPS active not lane 1 This bit indicates the status of ulpsactivenot0lane D-PHY signal.
bit_offset: 5
bit_size: 1
- name: RUE0
description: RX ULPS escape lane 0 This bit indicates the status of rxulpsesc0lane D-PHY signal.
bit_offset: 6
bit_size: 1
- name: PSS1
description: PHY stop state lane 1 This bit indicates the status of phystopstate1lane D-PHY signal.
bit_offset: 7
bit_size: 1
- name: UAN1
description: ULPS active not lane 1 This bit indicates the status of ulpsactivenot1lane D-PHY signal.
bit_offset: 8
bit_size: 1
fieldset/PTTCR:
description: DSI Host PHY TX triggers configuration register.
fields:
- name: TX_TRIG
description: Transmission trigger Escape mode transmit trigger 0-3. Only one bit of TX_TRIG is asserted at any given time.
bit_offset: 0
bit_size: 4
fieldset/PUCR:
description: DSI Host PHY ULPS control register.
fields:
- name: URCL
description: ULPS request on clock lane ULPS mode request on clock lane.
bit_offset: 0
bit_size: 1
- name: UECL
description: ULPS exit on clock lane ULPS mode exit on clock lane.
bit_offset: 1
bit_size: 1
- name: URDL
description: ULPS request on data lane ULPS mode request on all active data lanes.
bit_offset: 2
bit_size: 1
- name: UEDL
description: ULPS exit on data lane ULPS mode exit on all active data lanes.
bit_offset: 3
bit_size: 1
fieldset/TCCR0:
description: DSI Host timeout counter configuration register 0.
fields:
- name: LPRX_TOCNT
description: Low-power reception timeout counter This field configures the timeout counter that triggers a low-power reception timeout contention detection (measured in TOCKDIV cycles).
bit_offset: 0
bit_size: 16
- name: HSTX_TOCNT
description: "High-speed transmission timeout counter This field configures the timeout counter that triggers a high-speed transmission timeout contention detection (measured in TOCKDIV cycles). If using the non-burst mode and there is no enough time to switch from high-speed to low-power and back in the period from one line data finishing to the next line sync start, the DSI link returns the low-power state once per frame, then configure the TOCKDIV and HSTX_TOCNT to be in accordance with: HSTX_TOCNT * lanebyteclkperiod * TOCKDIV â\x89¥ the time of one FRAME data transmission * (1 + 10%) In burst mode, RGB pixel packets are time-compressed, leaving more time during a scan line. Therefore, if in burst mode and there is enough time to switch from high-speed to low-power and back in the period from one line data finishing to the next line sync start, the DSI link can return low-power mode and back in this time interval to save power. For this, configure the TOCKDIV and HSTX_TOCNT to be in accordance with: HSTX_TOCNT * lanebyteclkperiod * TOCKDIV â\x89¥ the time of one LINE data transmission * (1 + 10%)."
bit_offset: 16
bit_size: 16
fieldset/TCCR1:
description: DSI Host timeout counter configuration register 1.
fields:
- name: HSRD_TOCNT
description: High-speed read timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a high-speed read operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts.
bit_offset: 0
bit_size: 16
fieldset/TCCR2:
description: DSI Host timeout counter configuration register 2.
fields:
- name: LPRD_TOCNT
description: Low-power read timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a low-power read operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts.
bit_offset: 0
bit_size: 16
fieldset/TCCR3:
description: DSI Host timeout counter configuration register 3.
fields:
- name: HSWR_TOCNT
description: High-speed write timeout counter This field sets a period for which the DSI Host keeps the link inactive after sending a high-speed write operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts.
bit_offset: 0
bit_size: 16
- name: PM
description: "Presp mode When set to 1, this bit ensures that the peripheral response timeout caused by HSWR_TOCNT is used only once per LTDC frame in command mode, when both the following conditions are met: dpivsync_edpiwms has risen and fallen. Packets originated from LTDC in command mode have been transmitted and its FIFO is empty again. In this scenario no non-LTDC command requests are sent to the D-PHY, even if there is traffic from generic interface ready to be sent, making it return to stop state. When it does so, PRESP_TO counter is activated and only when it finishes does the controller send any other traffic that is ready."
bit_offset: 24
bit_size: 1
fieldset/TCCR4:
description: DSI Host timeout counter configuration register 4.
fields:
- name: LPWR_TOCNT
description: Low-power write timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a low-power write operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts.
bit_offset: 0
bit_size: 16
fieldset/TCCR5:
description: DSI Host timeout counter configuration register 5.
fields:
- name: BTA_TOCNT
description: "Bus-turn-around timeout counter This field sets a period for which the DSI Host keeps the link still, after completing a bus-turn-around. This period is measured in cycles of lanebyteclk. The counting starts when the Dâ\x80\x91PHY enters the Stop state and causes no interrupts."
bit_offset: 0
bit_size: 16
fieldset/VCCCR:
description: DSI Host video chunks current configuration register.
fields:
- name: NUMC
description: Number of chunks This field returns the number of chunks being transmitted during a line period.
bit_offset: 0
bit_size: 13
fieldset/VCCR:
description: DSI Host video chunks configuration register.
fields:
- name: NUMC
description: Number of chunks This register configures the number of chunks to be transmitted during a line period (a chunk consists of a video packet and a null packet). If set to 0 or 1, the video line is transmitted in a single packet. If set to 1, the packet is part of a chunk, so a null packet follows it if NPSIZE > 0. Otherwise, multiple chunks are used to transmit each video line.
bit_offset: 0
bit_size: 13
fieldset/VHBPCCR:
description: DSI Host video HBP current configuration register.
fields:
- name: HBP
description: Horizontal back-porch duration This field returns the horizontal back-porch period in lane byte clock cycles.
bit_offset: 0
bit_size: 12
fieldset/VHBPCR:
description: DSI Host video HBP configuration register.
fields:
- name: HBP
description: Horizontal back-porch duration This fields configures the horizontal back-porch period in lane byte clock cycles.
bit_offset: 0
bit_size: 12
fieldset/VHSACCR:
description: DSI Host video HSA current configuration register.
fields:
- name: HSA
description: Horizontal synchronism active duration This fields returns the horizontal synchronism active period in lane byte clock cycles.
bit_offset: 0
bit_size: 12
fieldset/VHSACR:
description: DSI Host video HSA configuration register.
fields:
- name: HSA
description: Horizontal synchronism active duration This fields configures the horizontal synchronism active period in lane byte clock cycles.
bit_offset: 0
bit_size: 12
fieldset/VLCCR:
description: DSI Host video line current configuration register.
fields:
- name: HLINE
description: Horizontal line duration This field returns the current total of the horizontal line period (HSA+HBP+HACT+HFP) counted in lane byte clock cycles.
bit_offset: 0
bit_size: 15
fieldset/VLCR:
description: DSI Host video line configuration register.
fields:
- name: HLINE
description: Horizontal line duration This fields configures the total of the horizontal line period (HSA+HBP+HACT+HFP) counted in lane byte clock cycles.
bit_offset: 0
bit_size: 15
fieldset/VMCCR:
description: DSI Host video mode current configuration register.
fields:
- name: VMT
description: "Video mode type This field returns the current video mode transmission type: 1x: Burst mode."
bit_offset: 0
bit_size: 2
- name: LPVSAE
description: Low-power vertical sync time enable This bit returns the current state of return to low-power inside the vertical sync time (VSA) period when timing allows.
bit_offset: 2
bit_size: 1
- name: LPVBPE
description: Low-power vertical back-porch enable This bit returns the current state of return to low-power inside the vertical back-porch (VBP) period when timing allows.
bit_offset: 3
bit_size: 1
- name: LPVFPE
description: Low-power vertical front-porch enable This bit returns the current state of return to low-power inside the vertical front-porch (VFP) period when timing allows.
bit_offset: 4
bit_size: 1
- name: LPVAE
description: Low-power vertical active enable This bit returns the current state of return to low-power inside the vertical active (VACT) period when timing allows.
bit_offset: 5
bit_size: 1
- name: LPHBPE
description: Low-power horizontal back-porch enable This bit returns the current state of return to low-power inside the horizontal back-porch (HBP) period when timing allows.
bit_offset: 6
bit_size: 1
- name: LPHFE
description: Low-power horizontal front-porch enable This bit returns the current state of return to low-power inside the horizontal front-porch (HFP) period when timing allows.
bit_offset: 7
bit_size: 1
- name: FBTAAE
description: Frame BTA acknowledge enable This bit returns the current state of request for an acknowledge response at the end of a frame.
bit_offset: 8
bit_size: 1
- name: LPCE
description: Low-power command enable This bit returns the current command transmission state in low-power mode.
bit_offset: 9
bit_size: 1
fieldset/VMCR:
description: DSI Host video mode configuration register.
fields:
- name: VMT
description: "Video mode type This field configures the video mode transmission type : 1x: Burst mode."
bit_offset: 0
bit_size: 2
- name: LPVSAE
description: Low-power vertical sync active enable This bit enables to return to low-power inside the vertical sync time (VSA) period when timing allows.
bit_offset: 8
bit_size: 1
- name: LPVBPE
description: Low-power vertical back-porch enable This bit enables to return to low-power inside the vertical back-porch (VBP) period when timing allows.
bit_offset: 9
bit_size: 1
- name: LPVFPE
description: Low-power vertical front-porch enable This bit enables to return to low-power inside the vertical front-porch (VFP) period when timing allows.
bit_offset: 10
bit_size: 1
- name: LPVAE
description: Low-power vertical active enable This bit enables to return to low-power inside the vertical active (VACT) period when timing allows.
bit_offset: 11
bit_size: 1
- name: LPHBPE
description: Low-power horizontal back-porch enable This bit enables the return to low-power inside the horizontal back-porch (HBP) period when timing allows.
bit_offset: 12
bit_size: 1
- name: LPHFPE
description: Low-power horizontal front-porch enable This bit enables the return to low-power inside the horizontal front-porch (HFP) period when timing allows.
bit_offset: 13
bit_size: 1
- name: FBTAAE
description: Frame bus-turn-around acknowledge enable This bit enables the request for an acknowledge response at the end of a frame.
bit_offset: 14
bit_size: 1
- name: LPCE
description: Low-power command enable This bit enables the command transmission only in low-power mode.
bit_offset: 15
bit_size: 1
- name: PGE
description: Pattern generator enable This bit enables the video mode pattern generator.
bit_offset: 16
bit_size: 1
- name: PGM
description: Pattern generator mode This bit configures the pattern generator mode.
bit_offset: 20
bit_size: 1
- name: PGO
description: Pattern generator orientation This bit configures the color bar orientation.
bit_offset: 24
bit_size: 1
fieldset/VNPCCR:
description: DSI Host video null packet current configuration register.
fields:
- name: NPSIZE
description: Null packet size This field returns the number of bytes inside a null packet.
bit_offset: 0
bit_size: 13
fieldset/VNPCR:
description: DSI Host video null packet configuration register.
fields:
- name: NPSIZE
description: Null packet size This field configures the number of bytes inside a null packet. Setting to 0 disables the null packets.
bit_offset: 0
bit_size: 13
fieldset/VPCCR:
description: DSI Host video packet current configuration register.
fields:
- name: VPSIZE
description: Video packet size This field returns the number of pixels in a single video packet.
bit_offset: 0
bit_size: 14
fieldset/VPCR:
description: DSI Host video packet configuration register.
fields:
- name: VPSIZE
description: Video packet size This field configures the number of pixels in a single video packet. For 18-bit not loosely packed data types, this number must be a multiple of 4. For YCbCr data types, it must be a multiple of 2 as described in the DSI specification.
bit_offset: 0
bit_size: 14
fieldset/VR:
description: DSI Host version register.
fields:
- name: VERSION
description: Version of the DSI Host This read-only register contains the version of the DSI Host.
bit_offset: 0
bit_size: 32
fieldset/VSCR:
description: DSI Host video shadow control register.
fields:
- name: EN
description: Enable When set to 1, DSI Host LTDC interface receives the active configuration from the auxiliary registers. When this bit is set along with the UR bit, the auxiliary registers are automatically updated.
bit_offset: 0
bit_size: 1
- name: UR
description: Update register When set to 1, the LTDC registers are copied to the auxiliary registers. After copying, this bit is auto cleared.
bit_offset: 8
bit_size: 1
fieldset/VVACCR:
description: DSI Host video VA current configuration register.
fields:
- name: VA
description: Vertical active duration This field returns the current vertical active period measured in number of horizontal lines.
bit_offset: 0
bit_size: 14
fieldset/VVACR:
description: DSI Host video VA configuration register.
fields:
- name: VA
description: Vertical active duration This fields configures the vertical active period measured in number of horizontal lines.
bit_offset: 0
bit_size: 14
fieldset/VVBPCCR:
description: DSI Host video VBP current configuration register.
fields:
- name: VBP
description: Vertical back-porch duration This field returns the current vertical back-porch period measured in number of horizontal lines.
bit_offset: 0
bit_size: 10
fieldset/VVBPCR:
description: DSI Host video VBP configuration register.
fields:
- name: VBP
description: Vertical back-porch duration This fields configures the vertical back-porch period measured in number of horizontal lines.
bit_offset: 0
bit_size: 10
fieldset/VVFPCCR:
description: DSI Host video VFP current configuration register.
fields:
- name: VFP
description: Vertical front-porch duration This field returns the current vertical front-porch period measured in number of horizontal lines.
bit_offset: 0
bit_size: 10
fieldset/VVFPCR:
description: DSI Host video VFP configuration register.
fields:
- name: VFP
description: Vertical front-porch duration This fields configures the vertical front-porch period measured in number of horizontal lines.
bit_offset: 0
bit_size: 10
fieldset/VVSACCR:
description: DSI Host video VSA current configuration register.
fields:
- name: VSA
description: Vertical synchronism active duration This field returns the current vertical synchronism active period measured in number of horizontal lines.
bit_offset: 0
bit_size: 10
fieldset/VVSACR:
description: DSI Host video VSA configuration register.
fields:
- name: VSA
description: Vertical synchronism active duration This fields configures the vertical synchronism active period measured in number of horizontal lines.
bit_offset: 0
bit_size: 10
fieldset/WCFGR:
description: DSI Wrapper configuration register.
fields:
- name: DSIM
description: DSI mode This bit selects the mode for the video transmission. This bit must only be changed when DSI Host is stopped (CR.EN = 0).
bit_offset: 0
bit_size: 1
- name: COLMUX
description: Color multiplexing This bit selects the color multiplexing used by DSI Host. This field must only be changed when DSI is stopped (WCR.DSIEN = 0 and CR.EN = 0).
bit_offset: 1
bit_size: 3
- name: TESRC
description: TE source This bit selects the tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (CR.EN = 0).
bit_offset: 4
bit_size: 1
- name: TEPOL
description: TE polarity This bit selects the polarity of the external pin tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (CR.EN = 0).
bit_offset: 5
bit_size: 1
- name: AR
description: Automatic refresh This bit selects the refresh mode in DBI mode. This bit must only be changed when DSI Host is stopped (CR.EN = 0).
bit_offset: 6
bit_size: 1
- name: VSPOL
description: VSync polarity This bit selects the VSync edge on which the LTDC is halted. This bit must only be changed when DSI is stopped (WCR.DSIEN = 0 and CR.EN = 0).
bit_offset: 7
bit_size: 1
fieldset/WCR:
description: DSI Wrapper control register.
fields:
- name: COLM
description: Color mode This bit controls the display color mode in video mode.
bit_offset: 0
bit_size: 1
- name: SHTDN
description: Shutdown This bit controls the display shutdown in video mode.
bit_offset: 1
bit_size: 1
- name: LTDCEN
description: LTDC enable This bit enables the LTDC for a frame transfer in adapted command mode.
bit_offset: 2
bit_size: 1
- name: DSIEN
description: DSI enable This bit enables the DSI Wrapper.
bit_offset: 3
bit_size: 1
fieldset/WIER:
description: DSI Wrapper interrupt enable register.
fields:
- name: TEIE
description: Tearing effect interrupt enable This bit enables the tearing effect interrupt.
bit_offset: 0
bit_size: 1
- name: ERIE
description: End of refresh interrupt enable This bit enables the end of refresh interrupt.
bit_offset: 1
bit_size: 1
- name: PLLLIE
description: PLL lock interrupt enable This bit enables the PLL lock interrupt.
bit_offset: 9
bit_size: 1
- name: PLLUIE
description: PLL unlock interrupt enable This bit enables the PLL unlock interrupt.
bit_offset: 10
bit_size: 1
fieldset/WIFCR:
description: DSI Wrapper interrupt flag clear register.
fields:
- name: CTEIF
description: Clear tearing effect interrupt flag Write 1 clears the TEIF flag in the WSR register.
bit_offset: 0
bit_size: 1
- name: CERIF
description: Clear end of refresh interrupt flag Write 1 clears the ERIF flag in the WSR register.
bit_offset: 1
bit_size: 1
- name: CPLLLIF
description: Clear PLL lock interrupt flag Write 1 clears the PLLLIF flag in the WSR register.
bit_offset: 9
bit_size: 1
- name: CPLLUIF
description: Clear PLL unlock interrupt flag Write 1 clears the PLLUIF flag in the WSR register.
bit_offset: 10
bit_size: 1
fieldset/WISR:
description: DSI Wrapper interrupt and status register.
fields:
- name: TEIF
description: Tearing effect interrupt flag This bit is set when a tearing effect event occurs.
bit_offset: 0
bit_size: 1
- name: ERIF
description: End of refresh interrupt flag This bit is set when the transfer of a frame in adapted command mode is finished.
bit_offset: 1
bit_size: 1
- name: BUSY
description: Busy flag This bit is set when the transfer of a frame in adapted command mode is ongoing.
bit_offset: 2
bit_size: 1
- name: PLLLS
description: PLL lock status This bit is set when the PLL is locked and cleared when it is unlocked.
bit_offset: 8
bit_size: 1
- name: PLLLIF
description: PLL lock interrupt flag This bit is set when the PLL becomes locked.
bit_offset: 9
bit_size: 1
- name: PLLUIF
description: PLL unlock interrupt flag This bit is set when the PLL becomes unlocked.
bit_offset: 10
bit_size: 1
fieldset/WPCR0:
description: DSI Wrapper PHY configuration register 0.
fields:
- name: SWCL
description: Swap clock lane pins This bit swaps the pins on clock lane.
bit_offset: 6
bit_size: 1
- name: SWDL0
description: Swap data lane 0 pins This bit swaps the pins on data lane 0.
bit_offset: 7
bit_size: 1
- name: SWDL1
description: Swap data lane 1 pins This bit swaps the pins on clock lane.
bit_offset: 8
bit_size: 1
- name: FTXSMCL
description: Force in TX Stop mode the clock lane This bit forces the clock lane in TX stop mode. It is used to initialize a lane module in transmit mode. It causes the lane module to immediately jump to transmit control mode and to begin transmitting a stop state (LP-11). It can be used to go back in TX mode after a wrong BTA sequence.
bit_offset: 12
bit_size: 1
- name: FTXSMDL
description: Force in TX Stop mode the data lanes This bit forces the data lanes in TX stop mode. It is used to initialize a lane module in transmit mode. It causes the lane module to immediately jump to transmit control mode and to begin transmitting a stop state (LP-11). It can be used to go back in TX mode after a wrong BTA sequence.
bit_offset: 13
bit_size: 1
fieldset/WRPCR:
description: DSI Wrapper regulator and PLL control register.
fields:
- name: PLLEN
description: PLL enable This bit enables the D-PHY PLL.
bit_offset: 0
bit_size: 1
- name: NDIV
description: "PLL loop division factor This field configures the PLL loop division factor. 2: PLL loop divided by 2x2 ... 511: PLL loop divided by 511x2."
bit_offset: 2
bit_size: 9
- name: IDF
description: "PLL input division factor This field configures the PLL input division factor. 2: PLL input divided by 2 ... 511: PLL input divided by 511."
bit_offset: 11
bit_size: 9
- name: ODF
description: "PLL output division factor This field configures the PLL output division factor. 2: PLL output divided by 2 ... 511: PLL output divided by 511."
bit_offset: 20
bit_size: 9
Reference in New Issue View Git Blame Copy Permalink