659 lines
16 KiB
YAML
659 lines
16 KiB
YAML
block/ADC:
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description: Analog to Digital Converter
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items:
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- name: ISR
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description: ADC interrupt and status register
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byte_offset: 0
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fieldset: ISR
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- name: IER
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description: ADC interrupt enable register
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byte_offset: 4
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fieldset: IER
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- name: CR
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description: ADC control register
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byte_offset: 8
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fieldset: CR
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- name: CFGR1
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description: ADC configuration register 1
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byte_offset: 12
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fieldset: CFGR1
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- name: CFGR2
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description: ADC configuration register 2
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byte_offset: 16
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fieldset: CFGR2
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- name: SMPR
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description: ADC sampling time register
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byte_offset: 20
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fieldset: SMPR
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- name: AWD1TR
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description: watchdog threshold register
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byte_offset: 32
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fieldset: AWD1TR
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- name: AWD2TR
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description: watchdog threshold register
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byte_offset: 36
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fieldset: AWD2TR
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- name: CHSELR
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description: channel selection register
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byte_offset: 40
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fieldset: CHSELR
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- name: CHSELR_1
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description: channel selection register CHSELRMOD = 1 in ADC_CFGR1
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byte_offset: 40
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fieldset: CHSELR_1
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- name: AWD3TR
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description: watchdog threshold register
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byte_offset: 44
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fieldset: AWD3TR
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- name: DR
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description: ADC group regular conversion data register
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byte_offset: 64
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access: Read
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fieldset: DR
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- name: AWD2CR
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description: ADC analog watchdog 2 configuration register
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byte_offset: 160
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fieldset: AWD2CR
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- name: AWD3CR
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description: ADC analog watchdog 3 configuration register
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byte_offset: 164
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fieldset: AWD3CR
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- name: CALFACT
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description: ADC calibration factors register
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byte_offset: 180
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fieldset: CALFACT
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- name: CCR
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description: ADC common control register
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byte_offset: 776
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fieldset: CCR
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- name: HWCFGR6
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description: Hardware Configuration Register
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byte_offset: 984
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fieldset: HWCFGR6
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- name: HWCFGR5
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description: Hardware Configuration Register
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byte_offset: 988
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fieldset: HWCFGR5
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- name: HWCFGR4
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description: Hardware Configuration Register
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byte_offset: 992
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fieldset: HWCFGR4
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- name: HWCFGR3
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description: Hardware Configuration Register
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byte_offset: 996
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fieldset: HWCFGR3
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- name: HWCFGR2
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description: Hardware Configuration Register
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byte_offset: 1000
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fieldset: HWCFGR2
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- name: HWCFGR1
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description: Hardware Configuration Register
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byte_offset: 1004
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fieldset: HWCFGR1
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- name: HWCFGR0
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description: Hardware Configuration Register
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byte_offset: 1008
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access: Read
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fieldset: HWCFGR0
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- name: VERR
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description: EXTI IP Version register
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byte_offset: 1012
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access: Read
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fieldset: VERR
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- name: IPIDR
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description: EXTI Identification register
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byte_offset: 1016
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access: Read
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fieldset: IPIDR
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- name: SIDR
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description: EXTI Size ID register
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byte_offset: 1020
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access: Read
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fieldset: SIDR
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fieldset/AWD1TR:
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description: watchdog threshold register
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fields:
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- name: LT1
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description: ADC analog watchdog 1 threshold low
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bit_offset: 0
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bit_size: 12
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- name: HT1
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description: ADC analog watchdog 1 threshold high
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bit_offset: 16
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bit_size: 12
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fieldset/AWD2CR:
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description: ADC analog watchdog 2 configuration register
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fields:
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- name: AWD2CH
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description: ADC analog watchdog 2 monitored channel selection
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bit_offset: 0
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bit_size: 19
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fieldset/AWD2TR:
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description: watchdog threshold register
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fields:
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- name: LT2
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description: ADC analog watchdog 2 threshold low
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bit_offset: 0
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bit_size: 12
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- name: HT2
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description: ADC analog watchdog 2 threshold high
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bit_offset: 16
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bit_size: 12
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fieldset/AWD3CR:
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description: ADC analog watchdog 3 configuration register
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fields:
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- name: AWD3CH
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description: ADC analog watchdog 3 monitored channel selection
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bit_offset: 0
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bit_size: 19
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fieldset/AWD3TR:
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description: watchdog threshold register
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fields:
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- name: LT3
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description: ADC analog watchdog 3 threshold high
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bit_offset: 0
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bit_size: 12
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- name: HT3
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description: ADC analog watchdog 3 threshold high
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bit_offset: 16
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bit_size: 12
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fieldset/CALFACT:
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description: ADC calibration factors register
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fields:
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- name: CALFACT
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description: ADC calibration factor in single-ended mode
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bit_offset: 0
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bit_size: 7
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fieldset/CCR:
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description: ADC common control register
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fields:
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- name: PRESC
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description: ADC prescaler
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bit_offset: 18
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bit_size: 4
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- name: VREFEN
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description: VREFINT enable
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bit_offset: 22
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bit_size: 1
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- name: TSEN
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description: Temperature sensor enable
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bit_offset: 23
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bit_size: 1
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- name: VBATEN
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description: VBAT enable
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bit_offset: 24
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bit_size: 1
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fieldset/CFGR1:
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description: ADC configuration register 1
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fields:
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- name: DMAEN
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description: ADC DMA transfer enable
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bit_offset: 0
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bit_size: 1
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- name: DMACFG
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description: ADC DMA transfer configuration
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bit_offset: 1
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bit_size: 1
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- name: SCANDIR
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description: Scan sequence direction
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bit_offset: 2
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bit_size: 1
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- name: RES
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description: ADC data resolution
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bit_offset: 3
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bit_size: 2
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enum: RES
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- name: ALIGN
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description: ADC data alignement
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bit_offset: 5
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bit_size: 1
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- name: EXTSEL
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description: ADC group regular external trigger source
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bit_offset: 6
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bit_size: 3
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- name: EXTEN
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description: ADC group regular external trigger polarity
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bit_offset: 10
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bit_size: 2
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- name: OVRMOD
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description: ADC group regular overrun configuration
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bit_offset: 12
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bit_size: 1
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- name: CONT
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description: ADC group regular continuous conversion mode
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bit_offset: 13
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bit_size: 1
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- name: WAIT
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description: Wait conversion mode
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bit_offset: 14
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bit_size: 1
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- name: AUTOFF
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description: Auto-off mode
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bit_offset: 15
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bit_size: 1
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- name: DISCEN
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description: ADC group regular sequencer discontinuous mode
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bit_offset: 16
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bit_size: 1
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- name: CHSELRMOD
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description: Mode selection of the ADC_CHSELR register
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bit_offset: 21
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bit_size: 1
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- name: AWD1SGL
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description: ADC analog watchdog 1 monitoring a single channel or all channels
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bit_offset: 22
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bit_size: 1
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- name: AWD1EN
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description: ADC analog watchdog 1 enable on scope ADC group regular
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bit_offset: 23
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bit_size: 1
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- name: AWDCH1CH
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description: ADC analog watchdog 1 monitored channel selection
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bit_offset: 26
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bit_size: 5
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fieldset/CFGR2:
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description: ADC configuration register 2
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fields:
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- name: OVSE
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description: ADC oversampler enable on scope ADC group regular
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bit_offset: 0
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bit_size: 1
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- name: OVSR
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description: ADC oversampling ratio
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bit_offset: 2
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bit_size: 3
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- name: OVSS
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description: ADC oversampling shift
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bit_offset: 5
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bit_size: 4
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- name: TOVS
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description: ADC oversampling discontinuous mode (triggered mode) for ADC group regular
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bit_offset: 9
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bit_size: 1
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- name: LFTRIG
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description: Low frequency trigger mode enable
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bit_offset: 29
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bit_size: 1
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- name: CKMODE
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description: ADC clock mode
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bit_offset: 30
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bit_size: 2
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fieldset/CHSELR:
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description: channel selection register
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fields:
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- name: CHSEL
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description: Channel-x selection
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bit_offset: 0
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bit_size: 19
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fieldset/CHSELR_1:
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description: channel selection register CHSELRMOD = 1 in ADC_CFGR1
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fields:
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- name: SQ1
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description: conversion of the sequence
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bit_offset: 0
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bit_size: 4
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- name: SQ2
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description: conversion of the sequence
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bit_offset: 4
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bit_size: 4
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- name: SQ3
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description: conversion of the sequence
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bit_offset: 8
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bit_size: 4
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- name: SQ4
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description: conversion of the sequence
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bit_offset: 12
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bit_size: 4
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- name: SQ5
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description: conversion of the sequence
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bit_offset: 16
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bit_size: 4
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- name: SQ6
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description: conversion of the sequence
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bit_offset: 20
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bit_size: 4
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- name: SQ7
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description: conversion of the sequence
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bit_offset: 24
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bit_size: 4
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- name: SQ8
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description: conversion of the sequence
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bit_offset: 28
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bit_size: 4
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fieldset/CR:
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description: ADC control register
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fields:
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- name: ADEN
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description: ADC enable
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bit_offset: 0
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bit_size: 1
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- name: ADDIS
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description: ADC disable
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bit_offset: 1
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bit_size: 1
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- name: ADSTART
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description: ADC group regular conversion start
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bit_offset: 2
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bit_size: 1
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- name: ADSTP
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description: ADC group regular conversion stop
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bit_offset: 4
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bit_size: 1
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- name: ADVREGEN
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description: ADC voltage regulator enable
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bit_offset: 28
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bit_size: 1
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- name: ADCAL
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description: ADC calibration
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bit_offset: 31
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bit_size: 1
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fieldset/DR:
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description: ADC group regular conversion data register
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fields:
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- name: regularDATA
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description: ADC group regular conversion data
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bit_offset: 0
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bit_size: 16
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fieldset/HWCFGR0:
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description: Hardware Configuration Register
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fields:
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- name: NUM_CHAN_24
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description: NUM_CHAN_24
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bit_offset: 0
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bit_size: 4
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- name: EXTRA_AWDS
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description: Extra analog watchdog
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bit_offset: 4
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bit_size: 4
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- name: OVS
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description: Oversampling
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bit_offset: 8
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bit_size: 4
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fieldset/HWCFGR1:
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description: Hardware Configuration Register
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fields:
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- name: CHMAP3
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description: Input channel mapping
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bit_offset: 0
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bit_size: 5
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- name: CHMAP2
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description: Input channel mapping
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bit_offset: 8
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bit_size: 5
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- name: CHMAP1
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description: Input channel mapping
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bit_offset: 16
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bit_size: 5
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- name: CHMAP0
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description: Input channel mapping
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bit_offset: 24
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bit_size: 5
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fieldset/HWCFGR2:
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description: Hardware Configuration Register
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fields:
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- name: CHMAP7
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description: Input channel mapping
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bit_offset: 0
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bit_size: 5
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- name: CHMAP6
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description: Input channel mapping
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bit_offset: 8
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bit_size: 5
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- name: CHMAP5
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description: Input channel mapping
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bit_offset: 16
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bit_size: 5
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- name: CHMAP4
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description: Input channel mapping
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bit_offset: 24
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bit_size: 5
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fieldset/HWCFGR3:
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description: Hardware Configuration Register
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fields:
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- name: CHMAP11
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description: Input channel mapping
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bit_offset: 0
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bit_size: 5
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- name: CHMAP10
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description: Input channel mapping
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bit_offset: 8
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bit_size: 5
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- name: CHMAP9
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description: Input channel mapping
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bit_offset: 16
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bit_size: 5
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- name: CHMAP8
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description: Input channel mapping
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bit_offset: 24
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bit_size: 5
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fieldset/HWCFGR4:
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description: Hardware Configuration Register
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fields:
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- name: CHMAP15
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description: Input channel mapping
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bit_offset: 0
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bit_size: 5
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- name: CHMAP14
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description: Input channel mapping
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bit_offset: 8
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bit_size: 5
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- name: CHMAP13
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description: Input channel mapping
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bit_offset: 16
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bit_size: 5
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- name: CHMAP12
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description: Input channel mapping
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bit_offset: 24
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bit_size: 5
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fieldset/HWCFGR5:
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description: Hardware Configuration Register
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fields:
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- name: CHMAP19
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description: Input channel mapping
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bit_offset: 0
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bit_size: 5
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- name: CHMAP18
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description: Input channel mapping
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bit_offset: 8
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bit_size: 5
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- name: CHMAP17
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description: Input channel mapping
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bit_offset: 16
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bit_size: 5
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- name: CHMAP16
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description: Input channel mapping
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bit_offset: 24
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bit_size: 5
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fieldset/HWCFGR6:
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description: Hardware Configuration Register
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fields:
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- name: CHMAP20
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description: Input channel mapping
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bit_offset: 0
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bit_size: 5
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- name: CHMAP21
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description: Input channel mapping
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bit_offset: 8
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bit_size: 5
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- name: CHMAP22
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description: Input channel mapping
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bit_offset: 16
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bit_size: 5
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- name: CHMAP23
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description: Input channel mapping
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bit_offset: 24
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bit_size: 5
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fieldset/IER:
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description: ADC interrupt enable register
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fields:
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- name: ADRDYIE
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description: ADC ready interrupt
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bit_offset: 0
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bit_size: 1
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- name: EOSMPIE
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description: ADC group regular end of sampling interrupt
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bit_offset: 1
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bit_size: 1
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- name: EOCIE
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description: ADC group regular end of unitary conversion interrupt
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bit_offset: 2
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bit_size: 1
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- name: EOSIE
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description: ADC group regular end of sequence conversions interrupt
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bit_offset: 3
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bit_size: 1
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- name: OVRIE
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description: ADC group regular overrun interrupt
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bit_offset: 4
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bit_size: 1
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- name: AWD1IE
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description: ADC analog watchdog 1 interrupt
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bit_offset: 7
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bit_size: 1
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- name: AWD2IE
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description: ADC analog watchdog 2 interrupt
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bit_offset: 8
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bit_size: 1
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- name: AWD3IE
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description: ADC analog watchdog 3 interrupt
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bit_offset: 9
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bit_size: 1
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- name: EOCALIE
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description: End of calibration interrupt enable
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bit_offset: 11
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bit_size: 1
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- name: CCRDYIE
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description: Channel Configuration Ready Interrupt enable
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bit_offset: 13
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bit_size: 1
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fieldset/IPIDR:
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description: EXTI Identification register
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fields:
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- name: IPID
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description: IP Identification
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bit_offset: 0
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bit_size: 32
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fieldset/ISR:
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description: ADC interrupt and status register
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fields:
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- name: ADRDY
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description: ADC ready flag
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bit_offset: 0
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bit_size: 1
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- name: EOSMP
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description: ADC group regular end of sampling flag
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bit_offset: 1
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bit_size: 1
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- name: EOC
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description: ADC group regular end of unitary conversion flag
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bit_offset: 2
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bit_size: 1
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- name: EOS
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description: ADC group regular end of sequence conversions flag
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bit_offset: 3
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bit_size: 1
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- name: OVR
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description: ADC group regular overrun flag
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bit_offset: 4
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bit_size: 1
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- name: AWD1
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description: ADC analog watchdog 1 flag
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bit_offset: 7
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bit_size: 1
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- name: AWD2
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description: ADC analog watchdog 2 flag
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bit_offset: 8
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bit_size: 1
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- name: AWD3
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description: ADC analog watchdog 3 flag
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bit_offset: 9
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bit_size: 1
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- name: EOCAL
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description: End Of Calibration flag
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bit_offset: 11
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bit_size: 1
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- name: CCRDY
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description: Channel Configuration Ready flag
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bit_offset: 13
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bit_size: 1
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fieldset/SIDR:
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description: EXTI Size ID register
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fields:
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- name: SID
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description: Size Identification
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bit_offset: 0
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bit_size: 32
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fieldset/SMPR:
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description: ADC sampling time register
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fields:
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- name: SMP1
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description: Sampling time selection
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bit_offset: 0
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bit_size: 3
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enum: SAMPLE_TIME
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- name: SMP2
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description: Sampling time selection
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bit_offset: 4
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bit_size: 3
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enum: SAMPLE_TIME
|
|
- name: SMPSEL
|
|
description: Channel sampling time selection
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
array:
|
|
len: 19
|
|
stride: 0
|
|
fieldset/VERR:
|
|
description: EXTI IP Version register
|
|
fields:
|
|
- name: MINREV
|
|
description: Minor Revision number
|
|
bit_offset: 0
|
|
bit_size: 4
|
|
- name: MAJREV
|
|
description: Major Revision number
|
|
bit_offset: 4
|
|
bit_size: 4
|
|
enum/RES:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Bits12
|
|
description: 12-bit resolution
|
|
value: 0
|
|
- name: Bits10
|
|
description: 10-bit resolution
|
|
value: 1
|
|
- name: Bits8
|
|
description: 8-bit resolution
|
|
value: 2
|
|
- name: Bits6
|
|
description: 6-bit resolution
|
|
value: 3
|
|
enum/SAMPLE_TIME:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Cycles1_5
|
|
description: 1.5 ADC cycles
|
|
value: 0
|
|
- name: Cycles3_5
|
|
description: 3.5 ADC cycles
|
|
value: 1
|
|
- name: Cycles7_5
|
|
description: 7.5 ADC cycles
|
|
value: 2
|
|
- name: Cycles12_5
|
|
description: 12.5 ADC cycles
|
|
value: 3
|
|
- name: Cycles19_5
|
|
description: 19.5 ADC cycles
|
|
value: 4
|
|
- name: Cycles39_5
|
|
description: 39.5 ADC cycles
|
|
value: 5
|
|
- name: Cycles79_5
|
|
description: 79.5 ADC cycles
|
|
value: 6
|
|
- name: Cycles160_5
|
|
description: 160.5 ADC cycles
|
|
value: 7
|