380 lines
8.7 KiB
YAML
380 lines
8.7 KiB
YAML
# DAC v6, used in H5 and U5.
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# Adds DMADOUBLE and SINFORMAT fields to MCR, DACRDY and DORSTAT fields to SR
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# Adds B data fields to data holding registers
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# Moves HFSEL from CR to MCR and makes it 2 bits.
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block/DAC:
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description: Digital-to-analog converter
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items:
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- name: CR
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description: control register
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byte_offset: 0
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fieldset: CR
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- name: SWTRIGR
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description: software trigger register
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byte_offset: 4
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access: Write
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fieldset: SWTRIGR
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- name: DHR12R
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description: channel 12-bit right-aligned data holding register
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array:
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len: 2
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stride: 12
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byte_offset: 8
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fieldset: DHR12R
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- name: DHR12L
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description: channel 12-bit left-aligned data holding register
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array:
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len: 2
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stride: 12
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byte_offset: 12
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fieldset: DHR12L
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- name: DHR8R
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description: channel 8-bit right-aligned data holding register
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array:
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len: 2
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stride: 12
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byte_offset: 16
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fieldset: DHR8R
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- name: DHR12RD
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description: dual 12-bit right-aligned data holding register
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byte_offset: 32
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fieldset: DHR12RD
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- name: DHR12LD
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description: dual 12-bit left aligned data holding register
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byte_offset: 36
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fieldset: DHR12LD
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- name: DHR8RD
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description: dual 8-bit right aligned data holding register
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byte_offset: 40
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fieldset: DHR8RD
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- name: DOR
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description: channel data output register
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array:
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len: 2
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stride: 4
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byte_offset: 44
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access: Read
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fieldset: DOR
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- name: SR
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description: status register
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byte_offset: 52
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fieldset: SR
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- name: CCR
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description: calibration control register
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byte_offset: 56
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fieldset: CCR
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- name: MCR
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description: mode control register
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byte_offset: 60
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fieldset: MCR
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- name: SHSR
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description: sample and hold sample time register
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array:
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len: 2
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stride: 4
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byte_offset: 64
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fieldset: SHSR
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- name: SHHR
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description: sample and hold hold time register
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byte_offset: 72
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fieldset: SHHR
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- name: SHRR
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description: sample and hold refresh time register
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byte_offset: 76
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fieldset: SHRR
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fieldset/CCR:
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description: calibration control register
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fields:
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- name: OTRIM
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description: channel offset trimming value
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bit_offset: 0
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bit_size: 5
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array:
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len: 2
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stride: 16
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fieldset/CR:
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description: control register
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fields:
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- name: EN
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description: channel enable
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bit_offset: 0
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bit_size: 1
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array:
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len: 2
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stride: 16
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- name: TEN
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description: channel trigger enable
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bit_offset: 1
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bit_size: 1
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array:
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len: 2
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stride: 16
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- name: TSEL
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description: channel trigger selection
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bit_offset: 2
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bit_size: 4
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array:
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len: 2
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stride: 16
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- name: WAVE
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description: channel noise/triangle wave generation enable
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bit_offset: 6
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bit_size: 2
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array:
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len: 2
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stride: 16
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enum: WAVE
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- name: MAMP
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description: channel mask/amplitude selector
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bit_offset: 8
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bit_size: 4
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array:
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len: 2
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stride: 16
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- name: DMAEN
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description: channel DMA enable
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bit_offset: 12
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bit_size: 1
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array:
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len: 2
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stride: 16
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- name: DMAUDRIE
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description: channel DMA Underrun Interrupt enable
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bit_offset: 13
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bit_size: 1
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array:
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len: 2
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stride: 16
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- name: CEN
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description: DAC channel calibration enable
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bit_offset: 14
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bit_size: 1
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array:
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len: 2
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stride: 16
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fieldset/DHR12L:
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description: channel 12-bit left-aligned data holding register
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fields:
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- name: DHR
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description: channel 12-bit left-aligned data
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bit_offset: 4
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bit_size: 12
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- name: DHRB
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description: channel 12-bit left-aligned data B
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bit_offset: 20
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bit_size: 12
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fieldset/DHR12LD:
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description: dual 12-bit left aligned data holding register
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fields:
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- name: DHR
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description: channel 12-bit left-aligned data
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bit_offset: 4
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bit_size: 12
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array:
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len: 2
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stride: 16
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fieldset/DHR12R:
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description: channel 12-bit right-aligned data holding register
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fields:
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- name: DHR
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description: channel 12-bit right-aligned data
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bit_offset: 0
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bit_size: 12
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- name: DHRB
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description: channel 12-bit right-aligned data B
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bit_offset: 16
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bit_size: 12
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fieldset/DHR12RD:
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description: dual 12-bit right-aligned data holding register
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fields:
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- name: DHR
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description: channel 12-bit right-aligned data
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bit_offset: 0
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bit_size: 12
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array:
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len: 2
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stride: 16
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fieldset/DHR8R:
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description: channel 8-bit right-aligned data holding register
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fields:
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- name: DHR
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description: channel 8-bit right-aligned data
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bit_offset: 0
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bit_size: 8
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- name: DHRB
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description: channel 8-bit right-aligned data B
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bit_offset: 8
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bit_size: 8
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fieldset/DHR8RD:
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description: dual 8-bit right aligned data holding register
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fields:
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- name: DHR
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description: channel 8-bit right-aligned data
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bit_offset: 0
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bit_size: 8
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array:
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len: 2
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stride: 8
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fieldset/DOR:
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description: channel data output register
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fields:
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- name: DOR
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description: channel data output
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bit_offset: 0
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bit_size: 12
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- name: DORB
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description: channel data output B
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bit_offset: 16
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bit_size: 12
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fieldset/MCR:
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description: mode control register
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fields:
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- name: MODE
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description: DAC channel mode
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bit_offset: 0
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bit_size: 3
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enum: MODE
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array:
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len: 2
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stride: 16
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- name: DMADOUBLE
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description: channel DMA double data mode.
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bit_offset: 8
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bit_size: 1
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array:
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len: 2
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stride: 16
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- name: SINFORMAT
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description: enable signed format for DAC channel
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bit_offset: 9
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bit_size: 1
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array:
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len: 2
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stride: 16
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- name: HFSEL
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description: high frequency interface mode selection
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bit_offset: 14
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bit_size: 2
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fieldset/SHHR:
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description: sample and hold hold time register
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fields:
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- name: THOLD
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description: channel hold time
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bit_offset: 0
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bit_size: 10
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array:
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len: 2
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stride: 16
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fieldset/SHRR:
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description: sample and hold refresh time register
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fields:
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- name: TREFRESH
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description: channel refresh time
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bit_offset: 0
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bit_size: 8
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array:
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len: 2
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stride: 16
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fieldset/SHSR:
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description: sample and hold sample time register
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fields:
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- name: TSAMPLE
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description: channel sample time
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bit_offset: 0
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bit_size: 10
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fieldset/SR:
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description: status register
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fields:
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- name: DACRDY
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description: channel ready status bit
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bit_offset: 11
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bit_size: 1
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array:
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len: 2
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stride: 16
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- name: DORSTAT
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description: channel output register status bit
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bit_offset: 12
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bit_size: 1
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array:
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len: 2
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stride: 16
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- name: DMAUDR
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description: channel DMA underrun flag
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bit_offset: 13
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bit_size: 1
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array:
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len: 2
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stride: 16
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- name: CAL_FLAG
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description: channel calibration offset status
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bit_offset: 14
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bit_size: 1
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array:
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len: 2
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stride: 16
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- name: BWST
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description: channel busy writing sample time flag
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bit_offset: 15
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bit_size: 1
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array:
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len: 2
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stride: 16
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fieldset/SWTRIGR:
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description: software trigger register
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fields:
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- name: SWTRIG
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description: channel software trigger
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bit_offset: 0
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bit_size: 1
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array:
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len: 2
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stride: 1
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- name: SWTRIGB
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description: channel software trigger B
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bit_offset: 16
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bit_size: 1
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array:
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len: 2
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stride: 1
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enum/MODE:
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bit_size: 3
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variants:
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- name: NORMAL_EXT_BUFEN
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description: Normal mode, external pin only, buffer enabled
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value: 0
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- name: NORMAL_EXT_INT_BUFEN
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description: Normal mode, external pin and internal peripherals, buffer enabled
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value: 1
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- name: NORMAL_EXT_BUFDIS
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description: Normal mode, external pin only, buffer disabled
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value: 2
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- name: NORMAL_INT_BUFDIS
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description: Normal mode, internal peripherals only, buffer disabled
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value: 3
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- name: SAMPHOLD_EXT_BUFEN
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description: Sample and hold mode, external pin only, buffer enabled
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value: 4
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- name: SAMPHOLD_EXT_INT_BUFEN
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description: Sample and hold mode, external pin and internal peripherals, buffer enabled
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value: 5
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- name: SAMPHOLD_EXT_INT_BUFDIS
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description: Sample and hold mode, external pin and internal peripherals, buffer disabled
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value: 6
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- name: SAMPHOLD_INT_BUFDIS
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description: Sample and hold mode, internal peripherals only, buffer disabled
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value: 7
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enum/WAVE:
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bit_size: 2
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variants:
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- name: Disabled
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description: Wave generation disabled
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value: 0
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- name: Noise
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description: Noise wave generation enabled
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value: 1
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- name: Triangle
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description: Triangle wave generation enabled
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value: 2
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