stm32-data/data/registers/lptim_v2a.yaml

block/LPTIM:
  description: Low power timer.
  items:
  - name: ISR
    description: Interrupt and Status Register.
    byte_offset: 0
    access: Read
    fieldset: ISR
  - name: ICR
    description: Interrupt Clear Register.
    byte_offset: 4
    access: Write
    fieldset: ICR
  - name: IER
    description: Interrupt Enable Register.
    byte_offset: 8
    fieldset: IER
  - name: CFGR
    description: Configuration Register.
    byte_offset: 12
    fieldset: CFGR
  - name: CR
    description: Control Register.
    byte_offset: 16
    fieldset: CR
  - name: CMP
    description: Compare Register.
    byte_offset: 20
    fieldset: CMP
  - name: ARR
    description: Autoreload Register.
    byte_offset: 24
    fieldset: ARR
  - name: CNT
    description: Counter Register.
    byte_offset: 28
    access: Read
    fieldset: CNT
  - name: OR
    description: LPTIM option register.
    byte_offset: 32
  - name: RCR
    description: LPTIM repetition register.
    byte_offset: 40
    fieldset: RCR
fieldset/ARR:
  description: Autoreload Register.
  fields:
  - name: ARR
    description: Auto reload value.
    bit_offset: 0
    bit_size: 16
fieldset/CFGR:
  description: Configuration Register.
  fields:
  - name: CKSEL
    description: Clock selector.
    bit_offset: 0
    bit_size: 1
    enum: CKSEL
  - name: CKPOL
    description: Clock Polarity.
    bit_offset: 1
    bit_size: 2
    enum: CKPOL
  - name: CKFLT
    description: Configurable digital filter for external clock.
    bit_offset: 3
    bit_size: 2
    enum: Filter
  - name: TRGFLT
    description: Configurable digital filter for trigger.
    bit_offset: 6
    bit_size: 2
    enum: Filter
  - name: PRESC
    description: Clock prescaler.
    bit_offset: 9
    bit_size: 3
    enum: PRESC
  - name: TRIGSEL
    description: Trigger selector.
    bit_offset: 13
    bit_size: 3
  - name: TRIGEN
    description: Trigger enable and polarity.
    bit_offset: 17
    bit_size: 2
  - name: TIMOUT
    description: Timeout enable.
    bit_offset: 19
    bit_size: 1
  - name: WAVE
    description: Waveform shape.
    bit_offset: 20
    bit_size: 1
  - name: WAVPOL
    description: Waveform shape polarity.
    bit_offset: 21
    bit_size: 1
  - name: PRELOAD
    description: Registers update mode.
    bit_offset: 22
    bit_size: 1
  - name: COUNTMODE
    description: counter mode enabled.
    bit_offset: 23
    bit_size: 1
  - name: ENC
    description: Encoder mode enable.
    bit_offset: 24
    bit_size: 1
fieldset/CMP:
  description: Compare Register.
  fields:
  - name: CMP
    description: Compare value.
    bit_offset: 0
    bit_size: 16
fieldset/CNT:
  description: Counter Register.
  fields:
  - name: CNT
    description: Counter value.
    bit_offset: 0
    bit_size: 16
fieldset/CR:
  description: Control Register.
  fields:
  - name: ENABLE
    description: LPTIM Enable.
    bit_offset: 0
    bit_size: 1
  - name: SNGSTRT
    description: LPTIM start in single mode.
    bit_offset: 1
    bit_size: 1
  - name: CNTSTRT
    description: Timer start in continuous mode.
    bit_offset: 2
    bit_size: 1
  - name: RSTARE
    description: Reset after read enable.
    bit_offset: 3
    bit_size: 1
  - name: COUNTRST
    description: Counter reset.
    bit_offset: 4
    bit_size: 1
fieldset/ICR:
  description: Interrupt Clear Register.
  fields:
  - name: CMPMCF
    description: compare match Clear Flag.
    bit_offset: 0
    bit_size: 1
  - name: ARRMCF
    description: Autoreload match Clear Flag.
    bit_offset: 1
    bit_size: 1
  - name: EXTTRIGCF
    description: External trigger valid edge Clear Flag.
    bit_offset: 2
    bit_size: 1
  - name: CMPOKCF
    description: Compare register update OK Clear Flag.
    bit_offset: 3
    bit_size: 1
  - name: ARROKCF
    description: Autoreload register update OK Clear Flag.
    bit_offset: 4
    bit_size: 1
  - name: UPCF
    description: Direction change to UP Clear Flag.
    bit_offset: 5
    bit_size: 1
  - name: DOWNCF
    description: Direction change to down Clear Flag.
    bit_offset: 6
    bit_size: 1
  - name: UECF
    description: Update event clear flag.
    bit_offset: 7
    bit_size: 1
  - name: REPOKCF
    description: Repetition register update OK clear flag.
    bit_offset: 8
    bit_size: 1
fieldset/IER:
  description: Interrupt Enable Register.
  fields:
  - name: CMPMIE
    description: Compare match Interrupt Enable.
    bit_offset: 0
    bit_size: 1
  - name: ARRMIE
    description: Autoreload match Interrupt Enable.
    bit_offset: 1
    bit_size: 1
  - name: EXTTRIGIE
    description: External trigger valid edge Interrupt Enable.
    bit_offset: 2
    bit_size: 1
  - name: CMPOKIE
    description: Compare register update OK Interrupt Enable.
    bit_offset: 3
    bit_size: 1
  - name: ARROKIE
    description: Autoreload register update OK Interrupt Enable.
    bit_offset: 4
    bit_size: 1
  - name: UPIE
    description: Direction change to UP Interrupt Enable.
    bit_offset: 5
    bit_size: 1
  - name: DOWNIE
    description: Direction change to down Interrupt Enable.
    bit_offset: 6
    bit_size: 1
  - name: UEIE
    description: Update event interrupt enable.
    bit_offset: 7
    bit_size: 1
  - name: REPOKIE
    description: REPOKIE.
    bit_offset: 8
    bit_size: 1
fieldset/ISR:
  description: Interrupt and Status Register.
  fields:
  - name: CMPM
    description: Compare match.
    bit_offset: 0
    bit_size: 1
  - name: ARRM
    description: Autoreload match.
    bit_offset: 1
    bit_size: 1
  - name: EXTTRIG
    description: External trigger edge event.
    bit_offset: 2
    bit_size: 1
  - name: CMPOK
    description: Compare register update OK.
    bit_offset: 3
    bit_size: 1
  - name: ARROK
    description: Autoreload register update OK.
    bit_offset: 4
    bit_size: 1
  - name: UP
    description: Counter direction change down to up.
    bit_offset: 5
    bit_size: 1
  - name: DOWN
    description: Counter direction change up to down.
    bit_offset: 6
    bit_size: 1
  - name: UE
    description: LPTIM update event occurred.
    bit_offset: 7
    bit_size: 1
  - name: REPOK
    description: Repetition register update Ok.
    bit_offset: 8
    bit_size: 1
fieldset/RCR:
  description: LPTIM repetition register.
  fields:
  - name: REP
    description: Repetition register value.
    bit_offset: 0
    bit_size: 8
enum/CKPOL:
  bit_size: 2
  variants:
  - name: Rising
    description: the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active.
    value: 0
  - name: Falling
    description: the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active.
    value: 1
  - name: Both
    description: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.
    value: 2
enum/CKSEL:
  bit_size: 1
  variants:
  - name: Internal
    description: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)
    value: 0
  - name: External
    description: LPTIM is clocked by an external clock source through the LPTIM external Input1
    value: 1
enum/Filter:
  bit_size: 2
  variants:
  - name: Count1
    value: 0
  - name: Count2
    value: 1
  - name: Count4
    value: 2
  - name: Count8
    value: 3
enum/PRESC:
  bit_size: 3
  variants:
  - name: Div1
    value: 0
  - name: Div2
    value: 1
  - name: Div4
    value: 2
  - name: Div8
    value: 3
  - name: Div16
    value: 4
  - name: Div32
    value: 5
  - name: Div64
    value: 6
  - name: Div128
    value: 7