1644 lines
36 KiB
YAML
1644 lines
36 KiB
YAML
block/RCC:
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description: Reset and clock control
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items:
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- name: CR
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description: Clock control register
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byte_offset: 0
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fieldset: CR
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- name: ICSCR
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description: Internal clock sources calibration register
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byte_offset: 4
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fieldset: ICSCR
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- name: CFGR
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description: Clock configuration register
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byte_offset: 8
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fieldset: CFGR
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- name: PLLCFGR
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description: PLL configuration register
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byte_offset: 12
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fieldset: PLLCFGR
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- name: CIER
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description: Clock interrupt enable register
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byte_offset: 24
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fieldset: CIER
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- name: CIFR
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description: Clock interrupt flag register
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byte_offset: 28
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access: Read
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fieldset: CIFR
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- name: CICR
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description: Clock interrupt clear register
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byte_offset: 32
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access: Write
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fieldset: CICR
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- name: AHB1RSTR
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description: AHB1 peripheral reset register
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byte_offset: 40
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fieldset: AHB1RSTR
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- name: AHB2RSTR
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description: AHB2 peripheral reset register
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byte_offset: 44
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fieldset: AHB2RSTR
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- name: AHB3RSTR
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description: AHB3 peripheral reset register
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byte_offset: 48
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fieldset: AHB3RSTR
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- name: APB1RSTR1
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description: APB1 peripheral reset register 1
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byte_offset: 56
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fieldset: APB1RSTR1
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- name: APB1RSTR2
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description: APB1 peripheral reset register 2
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byte_offset: 60
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fieldset: APB1RSTR2
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- name: APB2RSTR
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description: APB2 peripheral reset register
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byte_offset: 64
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fieldset: APB2RSTR
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- name: APB3RSTR
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description: APB3 peripheral reset register
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byte_offset: 68
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fieldset: APB3RSTR
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- name: AHB1ENR
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description: AHB1 peripheral clock enable register
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byte_offset: 72
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fieldset: AHB1ENR
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- name: AHB2ENR
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description: AHB2 peripheral clock enable register
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byte_offset: 76
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fieldset: AHB2ENR
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- name: AHB3ENR
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description: AHB3 peripheral clock enable register
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byte_offset: 80
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fieldset: AHB3ENR
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- name: APB1ENR1
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description: APB1 peripheral clock enable register 1
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byte_offset: 88
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fieldset: APB1ENR1
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- name: APB1ENR2
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description: APB1 peripheral clock enable register 2
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byte_offset: 92
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fieldset: APB1ENR2
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- name: APB2ENR
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description: APB2 peripheral clock enable register
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byte_offset: 96
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fieldset: APB2ENR
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- name: APB3ENR
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description: APB3 peripheral clock enable register
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byte_offset: 100
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fieldset: APB3ENR
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- name: AHB1SMENR
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description: AHB1 peripheral clocks enable in Sleep modes register
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byte_offset: 104
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fieldset: AHB1SMENR
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- name: AHB2SMENR
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description: AHB2 peripheral clocks enable in Sleep modes register
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byte_offset: 108
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fieldset: AHB2SMENR
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- name: AHB3SMENR
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description: AHB3 peripheral clocks enable in Sleep and Stop modes register
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byte_offset: 112
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fieldset: AHB3SMENR
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- name: APB1SMENR1
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description: APB1 peripheral clocks enable in Sleep mode register 1
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byte_offset: 120
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fieldset: APB1SMENR1
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- name: APB1SMENR2
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description: APB1 peripheral clocks enable in Sleep mode register 2
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byte_offset: 124
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fieldset: APB1SMENR2
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- name: APB2SMENR
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description: APB2 peripheral clocks enable in Sleep mode register
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byte_offset: 128
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fieldset: APB2SMENR
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- name: APB3SMENR
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description: APB3 peripheral clock enable in Sleep mode register
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byte_offset: 132
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fieldset: APB3SMENR
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- name: CCIPR
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description: Peripherals independent clock configuration register
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byte_offset: 136
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fieldset: CCIPR
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- name: BDCR
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description: Backup domain control register
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byte_offset: 144
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fieldset: BDCR
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- name: CSR
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description: Control/status register
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byte_offset: 148
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fieldset: CSR
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- name: EXTCFGR
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description: Extended clock recovery register
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byte_offset: 264
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fieldset: EXTCFGR
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fieldset/AHB1ENR:
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description: AHB1 peripheral clock enable register
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fields:
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- name: DMA1EN
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description: CPU1 DMA1 clock enable
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bit_offset: 0
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bit_size: 1
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- name: DMA2EN
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description: CPU1 DMA2 clock enable
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bit_offset: 1
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bit_size: 1
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- name: DMAMUX1EN
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description: CPU1 DMAMUX1 clock enable
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bit_offset: 2
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bit_size: 1
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- name: CRCEN
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description: CPU1 CRC clock enable
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bit_offset: 12
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bit_size: 1
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fieldset/AHB1RSTR:
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description: AHB1 peripheral reset register
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fields:
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- name: DMA1RST
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description: DMA1 reset
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bit_offset: 0
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bit_size: 1
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- name: DMA2RST
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description: DMA2 reset
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bit_offset: 1
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bit_size: 1
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- name: DMAMUX1RST
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description: DMAMUX1 reset
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bit_offset: 2
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bit_size: 1
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- name: CRCRST
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description: CRC reset
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bit_offset: 12
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bit_size: 1
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fieldset/AHB1SMENR:
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description: AHB1 peripheral clocks enable in Sleep modes register
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fields:
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- name: DMA1SMEN
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description: DMA1 clock enable during CPU1 CSleep mode.
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bit_offset: 0
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bit_size: 1
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- name: DMA2SMEN
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description: DMA2 clock enable during CPU1 CSleep mode
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bit_offset: 1
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bit_size: 1
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- name: DMAMUX1SMEN
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description: DMAMUX1 clock enable during CPU1 CSleep mode.
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bit_offset: 2
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bit_size: 1
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- name: CRCSMEN
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description: CRC clock enable during CPU1 CSleep mode.
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bit_offset: 12
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bit_size: 1
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fieldset/AHB2ENR:
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description: AHB2 peripheral clock enable register
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fields:
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- name: GPIOAEN
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description: CPU1 IO port A clock enable
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bit_offset: 0
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bit_size: 1
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- name: GPIOBEN
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description: CPU1 IO port B clock enable
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bit_offset: 1
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bit_size: 1
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- name: GPIOCEN
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description: CPU1 IO port C clock enable
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bit_offset: 2
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bit_size: 1
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- name: GPIOHEN
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description: CPU1 IO port H clock enable
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bit_offset: 7
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bit_size: 1
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fieldset/AHB2RSTR:
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description: AHB2 peripheral reset register
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fields:
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- name: GPIOARST
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description: IO port A reset
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bit_offset: 0
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bit_size: 1
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- name: GPIOBRST
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description: IO port B reset
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bit_offset: 1
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bit_size: 1
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- name: GPIOCRST
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description: IO port C reset
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bit_offset: 2
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bit_size: 1
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- name: GPIOHRST
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description: IO port H reset
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bit_offset: 7
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bit_size: 1
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fieldset/AHB2SMENR:
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description: AHB2 peripheral clocks enable in Sleep modes register
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fields:
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- name: GPIOASMEN
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description: IO port A clock enable during CPU1 CSleep mode.
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bit_offset: 0
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bit_size: 1
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- name: GPIOBSMEN
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description: IO port B clock enable during CPU1 CSleep mode.
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bit_offset: 1
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bit_size: 1
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- name: GPIOCSMEN
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description: IO port C clock enable during CPU1 CSleep mode.
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bit_offset: 2
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bit_size: 1
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- name: GPIOHSMEN
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description: IO port H clock enable during CPU1 CSleep mode.
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bit_offset: 7
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bit_size: 1
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fieldset/AHB3ENR:
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description: AHB3 peripheral clock enable register
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fields:
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- name: PKAEN
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description: PKAEN
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bit_offset: 16
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bit_size: 1
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- name: AESEN
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description: AESEN
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bit_offset: 17
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bit_size: 1
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- name: RNGEN
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description: RNGEN
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bit_offset: 18
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bit_size: 1
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- name: HSEMEN
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description: HSEMEN
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bit_offset: 19
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bit_size: 1
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- name: FLASHEN
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description: CPU1 Flash interface clock enable
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bit_offset: 25
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bit_size: 1
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fieldset/AHB3RSTR:
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description: AHB3 peripheral reset register
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fields:
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- name: PKARST
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description: PKARST
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bit_offset: 16
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bit_size: 1
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- name: AESRST
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description: AESRST
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bit_offset: 17
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bit_size: 1
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- name: RNGRST
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description: RNGRST
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bit_offset: 18
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bit_size: 1
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- name: HSEMRST
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description: HSEMRST
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bit_offset: 19
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bit_size: 1
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- name: FLASHRST
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description: Flash interface reset
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bit_offset: 25
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bit_size: 1
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fieldset/AHB3SMENR:
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description: AHB3 peripheral clocks enable in Sleep and Stop modes register
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fields:
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- name: PKASMEN
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description: PKA accelerator clock enable during CPU1 CSleep mode.
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bit_offset: 16
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bit_size: 1
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- name: AESSMEN
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description: AES accelerator clock enable during CPU1 CSleep mode.
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bit_offset: 17
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bit_size: 1
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- name: RNGSMEN
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description: True RNG clocks enable during CPU1 Csleep and CStop modes
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bit_offset: 18
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bit_size: 1
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- name: SRAM1SMEN
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description: SRAM1 interface clock enable during CPU1 CSleep mode.
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bit_offset: 23
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bit_size: 1
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- name: SRAM2SMEN
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description: SRAM2 memory interface clock enable during CPU1 CSleep mode
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bit_offset: 24
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bit_size: 1
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- name: FLASHSMEN
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description: Flash interface clock enable during CPU1 CSleep mode.
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bit_offset: 25
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bit_size: 1
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fieldset/APB1ENR1:
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description: APB1 peripheral clock enable register 1
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fields:
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- name: TIM2EN
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description: CPU1 TIM2 timer clock enable
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bit_offset: 0
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bit_size: 1
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- name: RTCAPBEN
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description: CPU1 RTC APB clock enable
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bit_offset: 10
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bit_size: 1
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- name: WWDGEN
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description: CPU1 Window watchdog clock enable
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bit_offset: 11
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bit_size: 1
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- name: SPI2EN
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description: CPU1 SPI2 clock enable
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bit_offset: 14
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bit_size: 1
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- name: USART2EN
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description: CPU1 USART2 clock enable
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bit_offset: 17
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bit_size: 1
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- name: I2C1EN
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description: CPU1 I2C1 clocks enable
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bit_offset: 21
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bit_size: 1
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- name: I2C2EN
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description: CPU1 I2C2 clocks enable
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bit_offset: 22
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bit_size: 1
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- name: I2C3EN
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description: CPU1 I2C3 clocks enable
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bit_offset: 23
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bit_size: 1
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- name: DAC1EN
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description: CPU1 DAC1 clock enable
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bit_offset: 29
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bit_size: 1
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- name: LPTIM1EN
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description: CPU1 Low power timer 1 clocks enable
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bit_offset: 31
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bit_size: 1
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fieldset/APB1ENR2:
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description: APB1 peripheral clock enable register 2
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fields:
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- name: LPUART1EN
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description: CPU1 Low power UART 1 clocks enable
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bit_offset: 0
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bit_size: 1
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- name: LPTIM2EN
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description: CPU1 Low power timer 2 clocks enable
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bit_offset: 5
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bit_size: 1
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- name: LPTIM3EN
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description: CPU1 Low power timer 3 clocks enable
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bit_offset: 6
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bit_size: 1
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fieldset/APB1RSTR1:
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description: APB1 peripheral reset register 1
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fields:
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- name: TIM2RST
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description: TIM2 timer reset
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bit_offset: 0
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bit_size: 1
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- name: SPI2RST
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description: SPI2 reset
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bit_offset: 14
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bit_size: 1
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- name: USART2RST
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description: USART2 reset
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bit_offset: 17
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bit_size: 1
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- name: I2C1RST
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description: I2C1 reset
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bit_offset: 21
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bit_size: 1
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- name: I2C2RST
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description: I2C2 reset
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bit_offset: 22
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bit_size: 1
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- name: I2C3RST
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description: I2C3 reset
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bit_offset: 23
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bit_size: 1
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- name: DACRST
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description: DAC reset
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bit_offset: 29
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bit_size: 1
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- name: LPTIM1RST
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description: Low Power Timer 1 reset
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bit_offset: 31
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bit_size: 1
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fieldset/APB1RSTR2:
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description: APB1 peripheral reset register 2
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fields:
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- name: LPUART1RST
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description: Low-power UART 1 reset
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bit_offset: 0
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bit_size: 1
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- name: LPTIM2RST
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description: Low-power timer 2 reset
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bit_offset: 5
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bit_size: 1
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- name: LPTIM3RST
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description: Low-power timer 3 reset
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bit_offset: 6
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bit_size: 1
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fieldset/APB1SMENR1:
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description: APB1 peripheral clocks enable in Sleep mode register 1
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fields:
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- name: TIM2SMEN
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description: TIM2 timer clock enable during CPU1 CSleep mode.
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bit_offset: 0
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bit_size: 1
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- name: RTCAPBSMEN
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description: RTC bus clock enable during CPU1 CSleep mode.
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bit_offset: 10
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bit_size: 1
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- name: WWDGSMEN
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description: Window watchdog clocks enable during CPU1 CSleep mode.
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bit_offset: 11
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bit_size: 1
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- name: SPI2SMEN
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description: SPI2 clock enable during CPU1 CSleep mode.
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bit_offset: 14
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bit_size: 1
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- name: USART2SMEN
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description: USART2 clock enable during CPU1 CSleep mode.
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bit_offset: 17
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bit_size: 1
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- name: I2C1SMEN
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description: I2C1 clock enable during CPU1 Csleep and CStop modes
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bit_offset: 21
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bit_size: 1
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- name: I2C2SMEN
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description: I2C2 clock enable during CPU1 Csleep and CStop modes
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bit_offset: 22
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bit_size: 1
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- name: I2C3SMEN
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description: I2C3 clock enable during CPU1 Csleep and CStop modes
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bit_offset: 23
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bit_size: 1
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- name: DACSMEN
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description: DAC clock enable during CPU1 CSleep mode.
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bit_offset: 29
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bit_size: 1
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- name: LPTIM1SMEN
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description: Low power timer 1 clock enable during CPU1 Csleep and CStop mode
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bit_offset: 31
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bit_size: 1
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fieldset/APB1SMENR2:
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description: APB1 peripheral clocks enable in Sleep mode register 2
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fields:
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- name: LPUART1SMEN
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description: Low power UART 1 clock enable during CPU1 Csleep and CStop modes.
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bit_offset: 0
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bit_size: 1
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- name: LPTIM2SMEN
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description: Low power timer 2 clock enable during CPU1 Csleep and CStop modes
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bit_offset: 5
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bit_size: 1
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- name: LPTIM3SMEN
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description: Low power timer 3 clock enable during CPU1 Csleep and CStop modes
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bit_offset: 6
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bit_size: 1
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fieldset/APB2ENR:
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description: APB2 peripheral clock enable register
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fields:
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- name: ADCEN
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description: CPU1 ADC clocks enable
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bit_offset: 9
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bit_size: 1
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- name: TIM1EN
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description: CPU1 TIM1 timer clock enable
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bit_offset: 11
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bit_size: 1
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- name: SPI1EN
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description: CPU1 SPI1 clock enable
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bit_offset: 12
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bit_size: 1
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- name: USART1EN
|
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description: CPU1 USART1clocks enable
|
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bit_offset: 14
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bit_size: 1
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- name: TIM16EN
|
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description: CPU1 TIM16 timer clock enable
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bit_offset: 17
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bit_size: 1
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- name: TIM17EN
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description: CPU1 TIM17 timer clock enable
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bit_offset: 18
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bit_size: 1
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fieldset/APB2RSTR:
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description: APB2 peripheral reset register
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fields:
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- name: ADCRST
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description: ADC reset
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bit_offset: 9
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bit_size: 1
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- name: TIM1RST
|
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description: TIM1 timer reset
|
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bit_offset: 11
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bit_size: 1
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- name: SPI1RST
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description: SPI1 reset
|
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bit_offset: 12
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bit_size: 1
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- name: USART1RST
|
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description: USART1 reset
|
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bit_offset: 14
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bit_size: 1
|
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- name: TIM16RST
|
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description: TIM16 timer reset
|
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bit_offset: 17
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bit_size: 1
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- name: TIM17RST
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description: TIM17 timer reset
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bit_offset: 18
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bit_size: 1
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fieldset/APB2SMENR:
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description: APB2 peripheral clocks enable in Sleep mode register
|
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fields:
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- name: ADCSMEN
|
|
description: ADC clocks enable during CPU1 Csleep and CStop modes
|
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bit_offset: 9
|
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bit_size: 1
|
|
- name: TIM1SMEN
|
|
description: TIM1 timer clock enable during CPU1 CSleep mode.
|
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bit_offset: 11
|
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bit_size: 1
|
|
- name: SPI1SMEN
|
|
description: SPI1 clock enable during CPU1 CSleep mode.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: USART1SMEN
|
|
description: USART1 clock enable during CPU1 Csleep and CStop modes.
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TIM16SMEN
|
|
description: TIM16 timer clock enable during CPU1 CSleep mode.
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM17SMEN
|
|
description: TIM17 timer clock enable during CPU1 CSleep mode.
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
fieldset/APB3ENR:
|
|
description: APB3 peripheral clock enable register
|
|
fields:
|
|
- name: SUBGHZSPIEN
|
|
description: sub-GHz radio SPI clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
fieldset/APB3RSTR:
|
|
description: APB3 peripheral reset register
|
|
fields:
|
|
- name: SUBGHZSPIRST
|
|
description: Sub-GHz radio SPI reset
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
fieldset/APB3SMENR:
|
|
description: APB3 peripheral clock enable in Sleep mode register
|
|
fields:
|
|
- name: SUBGHZSPISMEN
|
|
description: Sub-GHz radio SPI clock enable during Sleep and Stop modes
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
fieldset/BDCR:
|
|
description: Backup domain control register
|
|
fields:
|
|
- name: LSEON
|
|
description: LSE oscillator enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDY
|
|
description: LSE oscillator ready
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: LSEBYP
|
|
description: LSE oscillator bypass
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: LSEDRV
|
|
description: LSE oscillator drive capability
|
|
bit_offset: 3
|
|
bit_size: 2
|
|
enum: LSEDRV
|
|
- name: LSECSSON
|
|
description: CSS on LSE enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: LSECSSD
|
|
description: CSS on LSE failure Detection
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: LSESYSEN
|
|
description: LSE system clock enable
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: RTCSEL
|
|
description: RTC clock source selection
|
|
bit_offset: 8
|
|
bit_size: 2
|
|
enum: RTCSEL
|
|
- name: LSESYSRDY
|
|
description: LSE system clock ready
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: RTCEN
|
|
description: RTC clock enable
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: BDRST
|
|
description: Backup domain software reset
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: LSCOEN
|
|
description: Low speed clock output enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: LSCOSEL
|
|
description: Low speed clock output selection
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
fieldset/CCIPR:
|
|
description: Peripherals independent clock configuration register
|
|
fields:
|
|
- name: USART1SEL
|
|
description: USART1 clock source selection
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: USART2SEL
|
|
description: USART2 clock source selection
|
|
bit_offset: 2
|
|
bit_size: 2
|
|
- name: SPI2SEL
|
|
description: SPI2 I2S clock source selection
|
|
bit_offset: 8
|
|
bit_size: 2
|
|
- name: LPUART1SEL
|
|
description: LPUART1 clock source selection
|
|
bit_offset: 10
|
|
bit_size: 2
|
|
- name: I2C1SEL
|
|
description: I2C1 clock source selection
|
|
bit_offset: 12
|
|
bit_size: 2
|
|
- name: I2C2SEL
|
|
description: I2C2 clock source selection
|
|
bit_offset: 14
|
|
bit_size: 2
|
|
- name: I2C3SEL
|
|
description: I2C3 clock source selection
|
|
bit_offset: 16
|
|
bit_size: 2
|
|
- name: LPTIM1SEL
|
|
description: Low power timer 1 clock source selection
|
|
bit_offset: 18
|
|
bit_size: 2
|
|
- name: LPTIM2SEL
|
|
description: Low power timer 2 clock source selection
|
|
bit_offset: 20
|
|
bit_size: 2
|
|
- name: LPTIM3SEL
|
|
description: Low power timer 3 clock source selection
|
|
bit_offset: 22
|
|
bit_size: 2
|
|
- name: ADCSEL
|
|
description: ADC clock source selection
|
|
bit_offset: 28
|
|
bit_size: 2
|
|
enum: ADCSEL
|
|
- name: RNGSEL
|
|
description: RNG clock source selection
|
|
bit_offset: 30
|
|
bit_size: 2
|
|
fieldset/CFGR:
|
|
description: Clock configuration register
|
|
fields:
|
|
- name: SW
|
|
description: System clock switch
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
enum: SW
|
|
- name: SWS
|
|
description: System clock switch status
|
|
bit_offset: 2
|
|
bit_size: 2
|
|
enum: SW
|
|
- name: HPRE
|
|
description: HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.)
|
|
bit_offset: 4
|
|
bit_size: 4
|
|
enum: HPRE
|
|
- name: PPRE1
|
|
description: PCLK1 low-speed prescaler (APB1)
|
|
bit_offset: 8
|
|
bit_size: 3
|
|
enum: PPRE
|
|
- name: PPRE2
|
|
description: PCLK2 high-speed prescaler (APB2)
|
|
bit_offset: 11
|
|
bit_size: 3
|
|
enum: PPRE
|
|
- name: STOPWUCK
|
|
description: Wakeup from Stop and CSS backup clock selection
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: HPREF
|
|
description: HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1)
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: PPRE1F
|
|
description: PCLK1 prescaler flag (APB1)
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: PPRE2F
|
|
description: PCLK2 prescaler flag (APB2)
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: MCOSEL
|
|
description: Microcontroller clock output
|
|
bit_offset: 24
|
|
bit_size: 4
|
|
enum: MCOSEL
|
|
- name: MCOPRE
|
|
description: Microcontroller clock output prescaler
|
|
bit_offset: 28
|
|
bit_size: 3
|
|
enum: MCOPRE
|
|
fieldset/CICR:
|
|
description: Clock interrupt clear register
|
|
fields:
|
|
- name: LSIRDYC
|
|
description: LSI ready interrupt clear
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYC
|
|
description: LSE ready interrupt clear
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: MSIRDYC
|
|
description: MSI ready interrupt clear
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSIRDYC
|
|
description: HSI16 ready interrupt clear
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: HSERDYC
|
|
description: HSE ready interrupt clear
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: PLLRDYC
|
|
description: PLL ready interrupt clear
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: CSSC
|
|
description: HSE Clock security system interrupt clear
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LSECSSC
|
|
description: LSE Clock security system interrupt clear
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
fieldset/CIER:
|
|
description: Clock interrupt enable register
|
|
fields:
|
|
- name: LSIRDYIE
|
|
description: LSI ready interrupt enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYIE
|
|
description: LSE ready interrupt enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: MSIRDYIE
|
|
description: MSI ready interrupt enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSIRDYIE
|
|
description: HSI16 ready interrupt enable
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: HSERDYIE
|
|
description: HSE ready interrupt enable
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: PLLRDYIE
|
|
description: PLL ready interrupt enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: LSECSSIE
|
|
description: LSE clock security system interrupt enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
fieldset/CIFR:
|
|
description: Clock interrupt flag register
|
|
fields:
|
|
- name: LSIRDYF
|
|
description: LSI ready interrupt flag
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYF
|
|
description: LSE ready interrupt flag
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: MSIRDYF
|
|
description: MSI ready interrupt flag
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSIRDYF
|
|
description: HSI16 ready interrupt flag
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: HSERDYF
|
|
description: HSE ready interrupt flag
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: PLLRDYF
|
|
description: PLL ready interrupt flag
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: CSSF
|
|
description: HSE Clock security system interrupt flag
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LSECSSF
|
|
description: LSE Clock security system interrupt flag
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
fieldset/CR:
|
|
description: Clock control register
|
|
fields:
|
|
- name: MSION
|
|
description: MSI clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: MSIRDY
|
|
description: MSI clock ready flag (After reset this bit will be read 1 once the MSI is ready)
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: MSIPLLEN
|
|
description: MSI clock PLL enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: MSIRGSEL
|
|
description: MSI range control selection
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: MSIRANGE
|
|
description: MSI clock ranges
|
|
bit_offset: 4
|
|
bit_size: 4
|
|
enum: MSIRANGE
|
|
- name: HSION
|
|
description: HSI16 clock enable
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: HSIKERON
|
|
description: HSI16 always enable for peripheral kernel clocks.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HSIRDY
|
|
description: HSI16 clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI16 is ready)
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: HSIASFS
|
|
description: HSI16 automatic start from Stop
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: HSIKERDY
|
|
description: HSI16 kernel clock ready flag for peripherals requests.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: HSEON
|
|
description: HSE clock enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: HSERDY
|
|
description: HSE clock ready flag
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: CSSON
|
|
description: HSE Clock security system enable
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: HSEPRE
|
|
description: HSE sysclk prescaler
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: HSEBYPPWR
|
|
description: Enable HSE VDDTCXO output on package pin PB0-VDDTCXO.
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: PLLON
|
|
description: Main PLL enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: PLLRDY
|
|
description: Main PLL clock ready flag
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
fieldset/CSR:
|
|
description: Control/status register
|
|
fields:
|
|
- name: LSION
|
|
description: LSI oscillator enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSIRDY
|
|
description: LSI oscillator ready
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: LSIPRE
|
|
description: LSI frequency prescaler
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: MSISRANGE
|
|
description: MSI clock ranges
|
|
bit_offset: 8
|
|
bit_size: 4
|
|
- name: RFRSTF
|
|
description: Radio in reset status flag
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: RFRST
|
|
description: Radio reset
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: RMVF
|
|
description: Remove reset flag
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: RFILARSTF
|
|
description: Radio illegal access flag
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: OBLRSTF
|
|
description: Option byte loader reset flag
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: PINRSTF
|
|
description: Pin reset flag
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: BORRSTF
|
|
description: BOR flag
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: SFTRSTF
|
|
description: Software reset flag
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: IWDGRSTF
|
|
description: Independent window watchdog reset flag
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: WWDGRSTF
|
|
description: Window watchdog reset flag
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: LPWRRSTF
|
|
description: Low-power reset flag
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/EXTCFGR:
|
|
description: Extended clock recovery register
|
|
fields:
|
|
- name: SHDHPRE
|
|
description: HCLK3 shared prescaler (AHB3, Flash, and SRAM2)
|
|
bit_offset: 0
|
|
bit_size: 4
|
|
enum: HPRE
|
|
- name: SHDHPREF
|
|
description: HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2)
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
fieldset/ICSCR:
|
|
description: Internal clock sources calibration register
|
|
fields:
|
|
- name: MSICAL
|
|
description: MSI clock calibration
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
- name: MSITRIM
|
|
description: MSI clock trimming
|
|
bit_offset: 8
|
|
bit_size: 8
|
|
- name: HSICAL
|
|
description: HSI16 clock calibration
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
- name: HSITRIM
|
|
description: HSI16 clock trimming
|
|
bit_offset: 24
|
|
bit_size: 7
|
|
fieldset/PLLCFGR:
|
|
description: PLL configuration register
|
|
fields:
|
|
- name: PLLSRC
|
|
description: Main PLL entry clock source
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
enum: PLLSRC
|
|
- name: PLLM
|
|
description: Division factor for the main PLL input clock
|
|
bit_offset: 4
|
|
bit_size: 3
|
|
enum: PLLM
|
|
- name: PLLN
|
|
description: Main PLL multiplication factor for VCO
|
|
bit_offset: 8
|
|
bit_size: 7
|
|
enum: PLLN
|
|
- name: PLLPEN
|
|
description: Main PLL PLLPCLK output enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: PLLP
|
|
description: Main PLL division factor for PLLPCLK.
|
|
bit_offset: 17
|
|
bit_size: 5
|
|
enum: PLLP
|
|
- name: PLLQEN
|
|
description: Main PLL PLLQCLK output enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: PLLQ
|
|
description: Main PLL division factor for PLLQCLK
|
|
bit_offset: 25
|
|
bit_size: 3
|
|
enum: PLLQ
|
|
- name: PLLREN
|
|
description: Main PLL PLLRCLK output enable
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: PLLR
|
|
description: Main PLL division factor for PLLRCLK
|
|
bit_offset: 29
|
|
bit_size: 3
|
|
enum: PLLR
|
|
enum/ADCSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: HSI16
|
|
description: HSI16 used as ADC clock source
|
|
value: 1
|
|
- name: PLLPCLK
|
|
description: PLLPCLK used as ADC clock source
|
|
value: 2
|
|
- name: SYSCLK
|
|
description: SYSCLK used as ADC clock source
|
|
value: 3
|
|
enum/HPRE:
|
|
bit_size: 4
|
|
variants:
|
|
- name: Div1
|
|
description: DCLK not divided
|
|
value: 0
|
|
- name: Div3
|
|
description: hclk = SYSCLK divided by 3
|
|
value: 1
|
|
- name: Div5
|
|
description: hclk = SYSCLK divided by 5
|
|
value: 2
|
|
- name: Div6
|
|
description: hclk = SYSCLK divided by 6
|
|
value: 5
|
|
- name: Div10
|
|
description: hclk = SYSCLK divided by 8
|
|
value: 6
|
|
- name: Div32
|
|
description: hclk = SYSCLK divided by 32
|
|
value: 7
|
|
- name: Div2
|
|
description: hclk = SYSCLK divided by 2
|
|
value: 8
|
|
- name: Div4
|
|
description: hclk = SYSCLK divided by 4
|
|
value: 9
|
|
- name: Div8
|
|
description: hclk = SYSCLK divided by 8
|
|
value: 10
|
|
- name: Div16
|
|
description: hclk = SYSCLK divided by 16
|
|
value: 11
|
|
- name: Div64
|
|
description: hclk = SYSCLK divided by 64
|
|
value: 12
|
|
- name: Div128
|
|
description: hclk = SYSCLK divided by 128
|
|
value: 13
|
|
- name: Div256
|
|
description: hclk = SYSCLK divided by 256
|
|
value: 14
|
|
- name: Div512
|
|
description: hclk = SYSCLK divided by 256
|
|
value: 15
|
|
enum/LSEDRV:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Low
|
|
description: Low driving capability
|
|
value: 0
|
|
- name: MediumLow
|
|
description: Medium low driving capability
|
|
value: 1
|
|
- name: MediumHigh
|
|
description: Medium high driving capability
|
|
value: 2
|
|
- name: High
|
|
description: High driving capability
|
|
value: 3
|
|
enum/MCOPRE:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Div1
|
|
description: No division
|
|
value: 0
|
|
- name: Div2
|
|
description: Division by 2
|
|
value: 1
|
|
- name: Div4
|
|
description: Division by 4
|
|
value: 2
|
|
- name: Div8
|
|
description: Division by 8
|
|
value: 3
|
|
- name: Div16
|
|
description: Division by 16
|
|
value: 4
|
|
enum/MCOSEL:
|
|
bit_size: 4
|
|
variants:
|
|
- name: NoClock
|
|
description: No clock
|
|
value: 0
|
|
- name: SYSCLK
|
|
description: SYSCLK clock selected
|
|
value: 1
|
|
- name: MSI
|
|
description: MSI oscillator clock selected
|
|
value: 2
|
|
- name: HSI16
|
|
description: HSI oscillator clock selected
|
|
value: 3
|
|
- name: HSE
|
|
description: HSE oscillator clock selected
|
|
value: 4
|
|
- name: PLLRCLK
|
|
description: Main PLLRCLK clock selected
|
|
value: 5
|
|
- name: LSI
|
|
description: LSI oscillator clock selected
|
|
value: 6
|
|
- name: LSE
|
|
description: LSE oscillator clock selected
|
|
value: 8
|
|
- name: PLLPCLK
|
|
description: Main PLLCLK oscillator clock selected
|
|
value: 13
|
|
- name: PLLQCLK
|
|
description: Main PLLQCLK oscillator clock selected
|
|
value: 14
|
|
enum/MSIRANGE:
|
|
bit_size: 4
|
|
variants:
|
|
- name: Range100K
|
|
description: range 0 around 100 kHz
|
|
value: 0
|
|
- name: Range200K
|
|
description: range 1 around 200 kHz
|
|
value: 1
|
|
- name: Range400K
|
|
description: range 2 around 400 kHz
|
|
value: 2
|
|
- name: Range800K
|
|
description: range 3 around 800 kHz
|
|
value: 3
|
|
- name: Range1M
|
|
description: range 4 around 1 MHz
|
|
value: 4
|
|
- name: Range2M
|
|
description: range 5 around 2 MHz
|
|
value: 5
|
|
- name: Range4M
|
|
description: range 6 around 4 MHz
|
|
value: 6
|
|
- name: Range8M
|
|
description: range 7 around 8 MHz
|
|
value: 7
|
|
- name: Range16M
|
|
description: range 8 around 16 MHz
|
|
value: 8
|
|
- name: Range24M
|
|
description: range 9 around 24 MHz
|
|
value: 9
|
|
- name: Range32M
|
|
description: range 10 around 32 MHz
|
|
value: 10
|
|
- name: Range48M
|
|
description: range 11 around 48 MHz
|
|
value: 11
|
|
enum/PLLM:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Div1
|
|
value: 0
|
|
- name: Div2
|
|
value: 1
|
|
- name: Div3
|
|
value: 2
|
|
- name: Div4
|
|
value: 3
|
|
- name: Div5
|
|
value: 4
|
|
- name: Div6
|
|
value: 5
|
|
- name: Div7
|
|
value: 6
|
|
- name: Div8
|
|
value: 7
|
|
enum/PLLN:
|
|
bit_size: 7
|
|
variants:
|
|
- name: Mul6
|
|
value: 6
|
|
- name: Mul7
|
|
value: 7
|
|
- name: Mul8
|
|
value: 8
|
|
- name: Mul9
|
|
value: 9
|
|
- name: Mul10
|
|
value: 10
|
|
- name: Mul11
|
|
value: 11
|
|
- name: Mul12
|
|
value: 12
|
|
- name: Mul13
|
|
value: 13
|
|
- name: Mul14
|
|
value: 14
|
|
- name: Mul15
|
|
value: 15
|
|
- name: Mul16
|
|
value: 16
|
|
- name: Mul17
|
|
value: 17
|
|
- name: Mul18
|
|
value: 18
|
|
- name: Mul19
|
|
value: 19
|
|
- name: Mul20
|
|
value: 20
|
|
- name: Mul21
|
|
value: 21
|
|
- name: Mul22
|
|
value: 22
|
|
- name: Mul23
|
|
value: 23
|
|
- name: Mul24
|
|
value: 24
|
|
- name: Mul25
|
|
value: 25
|
|
- name: Mul26
|
|
value: 26
|
|
- name: Mul27
|
|
value: 27
|
|
- name: Mul28
|
|
value: 28
|
|
- name: Mul29
|
|
value: 29
|
|
- name: Mul30
|
|
value: 30
|
|
- name: Mul31
|
|
value: 31
|
|
- name: Mul32
|
|
value: 32
|
|
- name: Mul33
|
|
value: 33
|
|
- name: Mul34
|
|
value: 34
|
|
- name: Mul35
|
|
value: 35
|
|
- name: Mul36
|
|
value: 36
|
|
- name: Mul37
|
|
value: 37
|
|
- name: Mul38
|
|
value: 38
|
|
- name: Mul39
|
|
value: 39
|
|
- name: Mul40
|
|
value: 40
|
|
- name: Mul41
|
|
value: 41
|
|
- name: Mul42
|
|
value: 42
|
|
- name: Mul43
|
|
value: 43
|
|
- name: Mul44
|
|
value: 44
|
|
- name: Mul45
|
|
value: 45
|
|
- name: Mul46
|
|
value: 46
|
|
- name: Mul47
|
|
value: 47
|
|
- name: Mul48
|
|
value: 48
|
|
- name: Mul49
|
|
value: 49
|
|
- name: Mul50
|
|
value: 50
|
|
- name: Mul51
|
|
value: 51
|
|
- name: Mul52
|
|
value: 52
|
|
- name: Mul53
|
|
value: 53
|
|
- name: Mul54
|
|
value: 54
|
|
- name: Mul55
|
|
value: 55
|
|
- name: Mul56
|
|
value: 56
|
|
- name: Mul57
|
|
value: 57
|
|
- name: Mul58
|
|
value: 58
|
|
- name: Mul59
|
|
value: 59
|
|
- name: Mul60
|
|
value: 60
|
|
- name: Mul61
|
|
value: 61
|
|
- name: Mul62
|
|
value: 62
|
|
- name: Mul63
|
|
value: 63
|
|
- name: Mul64
|
|
value: 64
|
|
- name: Mul65
|
|
value: 65
|
|
- name: Mul66
|
|
value: 66
|
|
- name: Mul67
|
|
value: 67
|
|
- name: Mul68
|
|
value: 68
|
|
- name: Mul69
|
|
value: 69
|
|
- name: Mul70
|
|
value: 70
|
|
- name: Mul71
|
|
value: 71
|
|
- name: Mul72
|
|
value: 72
|
|
- name: Mul73
|
|
value: 73
|
|
- name: Mul74
|
|
value: 74
|
|
- name: Mul75
|
|
value: 75
|
|
- name: Mul76
|
|
value: 76
|
|
- name: Mul77
|
|
value: 77
|
|
- name: Mul78
|
|
value: 78
|
|
- name: Mul79
|
|
value: 79
|
|
- name: Mul80
|
|
value: 80
|
|
- name: Mul81
|
|
value: 81
|
|
- name: Mul82
|
|
value: 82
|
|
- name: Mul83
|
|
value: 83
|
|
- name: Mul84
|
|
value: 84
|
|
- name: Mul85
|
|
value: 85
|
|
- name: Mul86
|
|
value: 86
|
|
- name: Mul87
|
|
value: 87
|
|
- name: Mul88
|
|
value: 88
|
|
- name: Mul89
|
|
value: 89
|
|
- name: Mul90
|
|
value: 90
|
|
- name: Mul91
|
|
value: 91
|
|
- name: Mul92
|
|
value: 92
|
|
- name: Mul93
|
|
value: 93
|
|
- name: Mul94
|
|
value: 94
|
|
- name: Mul95
|
|
value: 95
|
|
- name: Mul96
|
|
value: 96
|
|
- name: Mul97
|
|
value: 97
|
|
- name: Mul98
|
|
value: 98
|
|
- name: Mul99
|
|
value: 99
|
|
- name: Mul100
|
|
value: 100
|
|
- name: Mul101
|
|
value: 101
|
|
- name: Mul102
|
|
value: 102
|
|
- name: Mul103
|
|
value: 103
|
|
- name: Mul104
|
|
value: 104
|
|
- name: Mul105
|
|
value: 105
|
|
- name: Mul106
|
|
value: 106
|
|
- name: Mul107
|
|
value: 107
|
|
- name: Mul108
|
|
value: 108
|
|
- name: Mul109
|
|
value: 109
|
|
- name: Mul110
|
|
value: 110
|
|
- name: Mul111
|
|
value: 111
|
|
- name: Mul112
|
|
value: 112
|
|
- name: Mul113
|
|
value: 113
|
|
- name: Mul114
|
|
value: 114
|
|
- name: Mul115
|
|
value: 115
|
|
- name: Mul116
|
|
value: 116
|
|
- name: Mul117
|
|
value: 117
|
|
- name: Mul118
|
|
value: 118
|
|
- name: Mul119
|
|
value: 119
|
|
- name: Mul120
|
|
value: 120
|
|
- name: Mul121
|
|
value: 121
|
|
- name: Mul122
|
|
value: 122
|
|
- name: Mul123
|
|
value: 123
|
|
- name: Mul124
|
|
value: 124
|
|
- name: Mul125
|
|
value: 125
|
|
- name: Mul126
|
|
value: 126
|
|
- name: Mul127
|
|
value: 127
|
|
enum/PLLP:
|
|
bit_size: 5
|
|
variants:
|
|
- name: Div2
|
|
value: 1
|
|
- name: Div3
|
|
value: 2
|
|
- name: Div4
|
|
value: 3
|
|
- name: Div5
|
|
value: 4
|
|
- name: Div6
|
|
value: 5
|
|
- name: Div7
|
|
value: 6
|
|
- name: Div8
|
|
value: 7
|
|
- name: Div9
|
|
value: 8
|
|
- name: Div10
|
|
value: 9
|
|
- name: Div11
|
|
value: 10
|
|
- name: Div12
|
|
value: 11
|
|
- name: Div13
|
|
value: 12
|
|
- name: Div14
|
|
value: 13
|
|
- name: Div15
|
|
value: 14
|
|
- name: Div16
|
|
value: 15
|
|
- name: Div17
|
|
value: 16
|
|
- name: Div18
|
|
value: 17
|
|
- name: Div19
|
|
value: 18
|
|
- name: Div20
|
|
value: 19
|
|
- name: Div21
|
|
value: 20
|
|
- name: Div22
|
|
value: 21
|
|
- name: Div23
|
|
value: 22
|
|
- name: Div24
|
|
value: 23
|
|
- name: Div25
|
|
value: 24
|
|
- name: Div26
|
|
value: 25
|
|
- name: Div27
|
|
value: 26
|
|
- name: Div28
|
|
value: 27
|
|
- name: Div29
|
|
value: 28
|
|
- name: Div30
|
|
value: 29
|
|
- name: Div31
|
|
value: 30
|
|
enum/PLLQ:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Div2
|
|
value: 1
|
|
- name: Div3
|
|
value: 2
|
|
- name: Div4
|
|
value: 3
|
|
- name: Div5
|
|
value: 4
|
|
- name: Div6
|
|
value: 5
|
|
- name: Div7
|
|
value: 6
|
|
enum/PLLR:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Div2
|
|
value: 1
|
|
- name: Div3
|
|
value: 2
|
|
- name: Div4
|
|
value: 3
|
|
- name: Div5
|
|
value: 4
|
|
- name: Div6
|
|
value: 5
|
|
- name: Div7
|
|
value: 6
|
|
enum/PLLSRC:
|
|
bit_size: 2
|
|
variants:
|
|
- name: NoClock
|
|
description: No clock selected as PLL entry clock source
|
|
value: 0
|
|
- name: MSI
|
|
description: MSI selected as PLL entry clock source
|
|
value: 1
|
|
- name: HSI16
|
|
description: HSI16 selected as PLL entry clock source
|
|
value: 2
|
|
- name: HSE
|
|
description: HSE selected as PLL entry clock source
|
|
value: 3
|
|
enum/PPRE:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Div1
|
|
description: HCLK not divided
|
|
value: 0
|
|
- name: Div2
|
|
description: HCLK divided by 2
|
|
value: 4
|
|
- name: Div4
|
|
description: HCLK divided by 4
|
|
value: 5
|
|
- name: Div8
|
|
description: HCLK divided by 8
|
|
value: 6
|
|
- name: Div16
|
|
description: HCLK divided by 16
|
|
value: 7
|
|
enum/RTCSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: NoClock
|
|
description: No clock selected
|
|
value: 0
|
|
- name: LSE
|
|
description: LSE oscillator clock selected
|
|
value: 1
|
|
- name: LSI
|
|
description: LSI oscillator clock selected
|
|
value: 2
|
|
- name: HSE
|
|
description: HSE oscillator clock divided by 32 selected
|
|
value: 3
|
|
enum/SW:
|
|
bit_size: 2
|
|
variants:
|
|
- name: MSI
|
|
value: 0
|
|
- name: HSI16
|
|
value: 1
|
|
- name: HSE
|
|
value: 2
|
|
- name: PLLR
|
|
value: 3
|