995 lines
23 KiB
YAML
995 lines
23 KiB
YAML
block/RCC:
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description: Reset and clock control
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items:
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- name: CR
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description: clock control register
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byte_offset: 0
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fieldset: CR
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- name: PLLCFGR
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description: PLL configuration register
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byte_offset: 4
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fieldset: PLLCFGR
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- name: CFGR
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description: clock configuration register
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byte_offset: 8
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fieldset: CFGR
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- name: CIR
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description: clock interrupt register
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byte_offset: 12
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fieldset: CIR
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- name: AHB1RSTR
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description: AHB1 peripheral reset register
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byte_offset: 16
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fieldset: AHB1RSTR
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- name: APB1RSTR
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description: APB1 peripheral reset register
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byte_offset: 32
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fieldset: APB1RSTR
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- name: APB2RSTR
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description: APB2 peripheral reset register
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byte_offset: 36
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fieldset: APB2RSTR
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- name: AHB1ENR
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description: AHB1 peripheral clock register
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byte_offset: 48
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fieldset: AHB1ENR
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- name: APB1ENR
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description: APB1 peripheral clock enable register
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byte_offset: 64
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fieldset: APB1ENR
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- name: APB2ENR
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description: APB2 peripheral clock enable register
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byte_offset: 68
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fieldset: APB2ENR
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- name: AHB1LPENR
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description: AHB1 peripheral clock enable in low power mode register
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byte_offset: 80
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fieldset: AHB1LPENR
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- name: APB1LPENR
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description: APB1 peripheral clock enable in low power mode register
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byte_offset: 96
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fieldset: APB1LPENR
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- name: APB2LPENR
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description: APB2 peripheral clock enabled in low power mode register
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byte_offset: 100
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fieldset: APB2LPENR
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- name: BDCR
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description: Backup domain control register
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byte_offset: 112
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fieldset: BDCR
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- name: CSR
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description: clock control & status register
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byte_offset: 116
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fieldset: CSR
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- name: SSCGR
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description: spread spectrum clock generation register
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byte_offset: 128
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fieldset: SSCGR
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- name: DCKCFGR
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description: DCKCFGR register
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byte_offset: 140
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fieldset: DCKCFGR
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- name: DCKCFGR2
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description: DCKCFGR2 register
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byte_offset: 148
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fieldset: DCKCFGR2
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fieldset/AHB1ENR:
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description: AHB1 peripheral clock register
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fields:
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- name: GPIOAEN
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description: IO port A clock enable
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bit_offset: 0
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bit_size: 1
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- name: GPIOBEN
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description: IO port B clock enable
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bit_offset: 1
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bit_size: 1
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- name: GPIOCEN
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description: IO port C clock enable
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bit_offset: 2
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bit_size: 1
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- name: GPIOHEN
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description: IO port H clock enable
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bit_offset: 7
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bit_size: 1
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- name: CRCEN
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description: CRC clock enable
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bit_offset: 12
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bit_size: 1
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- name: DMA1EN
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description: DMA1 clock enable
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bit_offset: 21
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bit_size: 1
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- name: DMA2EN
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description: DMA2 clock enable
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bit_offset: 22
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bit_size: 1
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- name: RNGEN
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description: RNG clock enable
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bit_offset: 31
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bit_size: 1
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fieldset/AHB1LPENR:
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description: AHB1 peripheral clock enable in low power mode register
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fields:
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- name: GPIOALPEN
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description: IO port A clock enable during sleep mode
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bit_offset: 0
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bit_size: 1
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- name: GPIOBLPEN
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description: IO port B clock enable during Sleep mode
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bit_offset: 1
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bit_size: 1
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- name: GPIOCLPEN
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description: IO port C clock enable during Sleep mode
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bit_offset: 2
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bit_size: 1
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- name: GPIOHLPEN
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description: IO port H clock enable during Sleep mode
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bit_offset: 7
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bit_size: 1
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- name: CRCLPEN
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description: CRC clock enable during Sleep mode
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bit_offset: 12
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bit_size: 1
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- name: FLASHLPEN
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description: Flash interface clock enable during Sleep mode
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bit_offset: 15
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bit_size: 1
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- name: SRAM1LPEN
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description: SRAM 1interface clock enable during Sleep mode
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bit_offset: 16
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bit_size: 1
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- name: DMA1LPEN
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description: DMA1 clock enable during Sleep mode
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bit_offset: 21
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bit_size: 1
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- name: DMA2LPEN
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description: DMA2 clock enable during Sleep mode
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bit_offset: 22
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bit_size: 1
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- name: RNGLPEN
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description: RNG clock enable during sleep mode
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bit_offset: 31
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bit_size: 1
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fieldset/AHB1RSTR:
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description: AHB1 peripheral reset register
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fields:
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- name: GPIOARST
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description: IO port A reset
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bit_offset: 0
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bit_size: 1
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- name: GPIOBRST
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description: IO port B reset
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bit_offset: 1
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bit_size: 1
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- name: GPIOCRST
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description: IO port C reset
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bit_offset: 2
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bit_size: 1
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- name: GPIOHRST
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description: IO port H reset
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bit_offset: 7
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bit_size: 1
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- name: CRCRST
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description: CRC reset
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bit_offset: 12
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bit_size: 1
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- name: DMA1RST
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description: DMA2 reset
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bit_offset: 21
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bit_size: 1
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- name: DMA2RST
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description: DMA2 reset
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bit_offset: 22
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bit_size: 1
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- name: RNGRST
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description: RNGRST
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bit_offset: 31
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bit_size: 1
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fieldset/APB1ENR:
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description: APB1 peripheral clock enable register
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fields:
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- name: TIM5EN
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description: TIM5 clock enable
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bit_offset: 3
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bit_size: 1
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- name: TIM6EN
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description: TIM6 clock enable
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bit_offset: 4
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bit_size: 1
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- name: LPTIM1EN
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description: LPTIM1 clock enable
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bit_offset: 9
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bit_size: 1
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- name: RTCAPBEN
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description: RTC APB clock enable
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bit_offset: 10
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bit_size: 1
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- name: WWDGEN
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description: Window watchdog clock enable
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bit_offset: 11
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bit_size: 1
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- name: SPI2EN
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description: SPI2 clock enable
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bit_offset: 14
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bit_size: 1
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- name: USART2EN
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description: USART 2 clock enable
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bit_offset: 17
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bit_size: 1
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- name: I2C1EN
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description: I2C1 clock enable
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bit_offset: 21
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bit_size: 1
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- name: I2C2EN
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description: I2C2 clock enable
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bit_offset: 22
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bit_size: 1
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- name: FMPI2C1EN
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description: FMPI2C1 clock enable
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bit_offset: 24
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bit_size: 1
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- name: PWREN
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description: Power interface clock enable
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bit_offset: 28
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bit_size: 1
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- name: DACEN
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description: DAC interface clock enable
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bit_offset: 29
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bit_size: 1
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fieldset/APB1LPENR:
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description: APB1 peripheral clock enable in low power mode register
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fields:
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- name: TIM5LPEN
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description: TIM5 clock enable during Sleep mode
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bit_offset: 3
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bit_size: 1
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- name: TIM6LPEN
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description: TIM6 clock enable during Sleep mode
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bit_offset: 4
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bit_size: 1
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- name: LPTIM1LPEN
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description: LPTIM1 clock enable during sleep mode
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bit_offset: 9
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bit_size: 1
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- name: RTCAPBLPEN
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description: RTC APB clock enable during sleep mode
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bit_offset: 10
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bit_size: 1
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- name: WWDGLPEN
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description: Window watchdog clock enable during Sleep mode
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bit_offset: 11
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bit_size: 1
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- name: SPI2LPEN
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description: SPI2 clock enable during Sleep mode
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bit_offset: 14
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bit_size: 1
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- name: USART2LPEN
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description: USART2 clock enable during Sleep mode
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bit_offset: 17
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bit_size: 1
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- name: I2C1LPEN
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description: I2C1 clock enable during Sleep mode
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bit_offset: 21
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bit_size: 1
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- name: I2C2LPEN
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description: I2C2 clock enable during Sleep mode
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bit_offset: 22
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bit_size: 1
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- name: FMPI2C1LPEN
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description: FMPI2C1 clock enable during Sleep
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bit_offset: 24
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bit_size: 1
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- name: PWRLPEN
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description: Power interface clock enable during Sleep mode
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bit_offset: 28
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bit_size: 1
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- name: DACLPEN
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description: DAC interface clock enable during sleep mode
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bit_offset: 29
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bit_size: 1
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fieldset/APB1RSTR:
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description: APB1 peripheral reset register
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fields:
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- name: TIM5RST
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description: TIM5 reset
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bit_offset: 3
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bit_size: 1
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- name: TIM6RST
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description: TIM6 reset
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bit_offset: 4
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bit_size: 1
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- name: LPTIM1RST
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description: LPTIM1 reset
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bit_offset: 9
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bit_size: 1
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- name: WWDGRST
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description: Window watchdog reset
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bit_offset: 11
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bit_size: 1
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- name: SPI2RST
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description: SPI 2 reset
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bit_offset: 14
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bit_size: 1
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- name: USART2RST
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description: USART 2 reset
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bit_offset: 17
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bit_size: 1
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- name: I2C1RST
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description: I2C 1 reset
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bit_offset: 21
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bit_size: 1
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- name: I2C2RST
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description: I2C 2 reset
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bit_offset: 22
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bit_size: 1
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- name: FMPI2C1RST
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description: FMPI2C1 reset
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bit_offset: 24
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bit_size: 1
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- name: PWRRST
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description: Power interface reset
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bit_offset: 28
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bit_size: 1
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- name: DACRST
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description: DAC reset
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bit_offset: 29
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bit_size: 1
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fieldset/APB2ENR:
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description: APB2 peripheral clock enable register
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fields:
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- name: TIM1EN
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description: TIM1 clock enable
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bit_offset: 0
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bit_size: 1
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- name: USART1EN
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description: USART1 clock enable
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bit_offset: 4
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bit_size: 1
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- name: USART6EN
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description: USART6 clock enable
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bit_offset: 5
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bit_size: 1
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- name: ADC1EN
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description: ADC1 clock enable
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bit_offset: 8
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bit_size: 1
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- name: SPI1EN
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description: SPI1 clock enable
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bit_offset: 12
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bit_size: 1
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- name: SYSCFGEN
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description: System configuration controller clock enable
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bit_offset: 14
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bit_size: 1
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- name: EXTITEN
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description: EXTI ans external IT clock enable
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bit_offset: 15
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bit_size: 1
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- name: TIM9EN
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description: TIM9 clock enable
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bit_offset: 16
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bit_size: 1
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- name: TIM11EN
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description: TIM11 clock enable
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bit_offset: 18
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bit_size: 1
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- name: SPI5EN
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description: SPI5 clock enable
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bit_offset: 20
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bit_size: 1
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fieldset/APB2LPENR:
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description: APB2 peripheral clock enabled in low power mode register
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fields:
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- name: TIM1LPEN
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description: TIM1 clock enable during Sleep mode
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bit_offset: 0
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bit_size: 1
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- name: USART1LPEN
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description: USART1 clock enable during Sleep mode
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bit_offset: 4
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bit_size: 1
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- name: USART6LPEN
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description: USART6 clock enable during Sleep mode
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bit_offset: 5
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bit_size: 1
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- name: ADC1LPEN
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description: ADC1 clock enable during Sleep mode
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bit_offset: 8
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bit_size: 1
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- name: SDIOLPEN
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description: SDIO clock enable during Sleep mode
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bit_offset: 11
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bit_size: 1
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- name: SPI1LPEN
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description: SPI 1 clock enable during Sleep mode
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bit_offset: 12
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bit_size: 1
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- name: SYSCFGLPEN
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description: System configuration controller clock enable during Sleep mode
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bit_offset: 14
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bit_size: 1
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- name: EXTITLPEN
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description: EXTI and External IT clock enable during sleep mode
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bit_offset: 15
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bit_size: 1
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- name: TIM9LPEN
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description: TIM9 clock enable during sleep mode
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bit_offset: 16
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bit_size: 1
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- name: TIM11LPEN
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description: TIM11 clock enable during Sleep mode
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bit_offset: 18
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bit_size: 1
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- name: SPI5LPEN
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description: SPI5 clock enable during Sleep mode
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bit_offset: 20
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bit_size: 1
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fieldset/APB2RSTR:
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description: APB2 peripheral reset register
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fields:
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- name: TIM1RST
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description: TIM1 reset
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bit_offset: 0
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bit_size: 1
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- name: USART1RST
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description: USART1 reset
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bit_offset: 4
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bit_size: 1
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- name: USART6RST
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description: USART6 reset
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bit_offset: 5
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bit_size: 1
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- name: ADCRST
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description: ADC interface reset (common to all ADCs)
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bit_offset: 8
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bit_size: 1
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- name: SPI1RST
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description: SPI 1 reset
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bit_offset: 12
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bit_size: 1
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- name: SYSCFGRST
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description: System configuration controller reset
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bit_offset: 14
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bit_size: 1
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- name: TIM9RST
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description: TIM9 reset
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bit_offset: 16
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bit_size: 1
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- name: TIM11RST
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description: TIM11 reset
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bit_offset: 18
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bit_size: 1
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- name: SPI5RST
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description: SPI5 reset
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bit_offset: 20
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bit_size: 1
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fieldset/BDCR:
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description: Backup domain control register
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fields:
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- name: LSEON
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description: External low-speed oscillator enable
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bit_offset: 0
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bit_size: 1
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- name: LSERDY
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description: External low-speed oscillator ready
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bit_offset: 1
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bit_size: 1
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- name: LSEBYP
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description: External low-speed oscillator bypass
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bit_offset: 2
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bit_size: 1
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- name: RTCSEL
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description: RTC clock source selection
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bit_offset: 8
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bit_size: 2
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enum: RTCSEL
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- name: RTCEN
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description: RTC clock enable
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bit_offset: 15
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bit_size: 1
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- name: BDRST
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description: Backup domain software reset
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bit_offset: 16
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bit_size: 1
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fieldset/CFGR:
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description: clock configuration register
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fields:
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- name: SW
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description: System clock switch
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bit_offset: 0
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bit_size: 2
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enum: SW
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- name: SWS
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description: System clock switch status
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bit_offset: 2
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bit_size: 2
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enum: SW
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- name: HPRE
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description: AHB prescaler
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bit_offset: 4
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bit_size: 4
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enum: HPRE
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- name: MCO1EN
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description: MCO output enable
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bit_offset: 8
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bit_size: 1
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- name: MCO2EN
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description: MCO output enable
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bit_offset: 9
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bit_size: 1
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- name: PPRE1
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description: APB Low speed prescaler (APB1)
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bit_offset: 10
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bit_size: 3
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enum: PPRE
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- name: PPRE2
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description: APB high-speed prescaler (APB2)
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bit_offset: 13
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bit_size: 3
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enum: PPRE
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- name: RTCPRE
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description: HSE division factor for RTC clock
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bit_offset: 16
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bit_size: 5
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- name: MCO1SEL
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description: Microcontroller clock output 1
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bit_offset: 21
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bit_size: 2
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enum: MCO1SEL
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- name: MCO1PRE
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description: MCO1 prescaler
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bit_offset: 24
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bit_size: 3
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enum: MCOPRE
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- name: MCO2PRE
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description: MCO2 prescaler
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bit_offset: 27
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bit_size: 3
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enum: MCOPRE
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- name: MCO2SEL
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description: Microcontroller clock output 2
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bit_offset: 30
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bit_size: 2
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enum: MCO2SEL
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fieldset/CIR:
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description: clock interrupt register
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fields:
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- name: LSIRDYF
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description: LSI ready interrupt flag
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bit_offset: 0
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bit_size: 1
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- name: LSERDYF
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description: LSE ready interrupt flag
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bit_offset: 1
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bit_size: 1
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- name: HSIRDYF
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description: HSI ready interrupt flag
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bit_offset: 2
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bit_size: 1
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- name: HSERDYF
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description: HSE ready interrupt flag
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bit_offset: 3
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bit_size: 1
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- name: PLLRDYF
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description: Main PLL (PLL) ready interrupt flag
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: CSSF
|
|
description: Clock security system interrupt flag
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: LSIRDYIE
|
|
description: LSI ready interrupt enable
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LSERDYIE
|
|
description: LSE ready interrupt enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HSIRDYIE
|
|
description: HSI ready interrupt enable
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: HSERDYIE
|
|
description: HSE ready interrupt enable
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: PLLRDYIE
|
|
description: Main PLL (PLL) ready interrupt enable
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: LSIRDYC
|
|
description: LSI ready interrupt clear
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: LSERDYC
|
|
description: LSE ready interrupt clear
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: HSIRDYC
|
|
description: HSI ready interrupt clear
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: HSERDYC
|
|
description: HSE ready interrupt clear
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: PLLRDYC
|
|
description: Main PLL(PLL) ready interrupt clear
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: PLLI2SRDYC
|
|
description: PLLI2S ready interrupt clear
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: CSSC
|
|
description: Clock security system interrupt clear
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
fieldset/CR:
|
|
description: clock control register
|
|
fields:
|
|
- name: HSION
|
|
description: Internal high-speed clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: HSIRDY
|
|
description: Internal high-speed clock ready flag
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: HSITRIM
|
|
description: Internal high-speed clock trimming
|
|
bit_offset: 3
|
|
bit_size: 5
|
|
- name: HSICAL
|
|
description: Internal high-speed clock calibration
|
|
bit_offset: 8
|
|
bit_size: 8
|
|
- name: HSEON
|
|
description: HSE clock enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: HSERDY
|
|
description: HSE clock ready flag
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: HSEBYP
|
|
description: HSE clock bypass
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: CSSON
|
|
description: Clock security system enable
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: PLLON
|
|
description: Main PLL (PLL) enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: PLLRDY
|
|
description: Main PLL (PLL) clock ready flag
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
fieldset/CSR:
|
|
description: clock control & status register
|
|
fields:
|
|
- name: LSION
|
|
description: Internal low-speed oscillator enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSIRDY
|
|
description: Internal low-speed oscillator ready
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: RMVF
|
|
description: Remove reset flag
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: BORRSTF
|
|
description: BOR reset flag
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: PADRSTF
|
|
description: PIN reset flag
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: PORRSTF
|
|
description: POR/PDR reset flag
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: SFTRSTF
|
|
description: Software reset flag
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: WDGRSTF
|
|
description: Independent watchdog reset flag
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: WWDGRSTF
|
|
description: Window watchdog reset flag
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: LPWRRSTF
|
|
description: Low-power reset flag
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/DCKCFGR:
|
|
description: DCKCFGR register
|
|
fields:
|
|
- name: TIMPRE
|
|
description: TIMPRE
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: TIMPRE
|
|
- name: I2SSRC
|
|
description: I2SSRC
|
|
bit_offset: 25
|
|
bit_size: 2
|
|
enum: ISSRC
|
|
fieldset/DCKCFGR2:
|
|
description: DCKCFGR2 register
|
|
fields:
|
|
- name: FMPI2C1SEL
|
|
description: FMPI2C1 kernel clock source selection
|
|
bit_offset: 22
|
|
bit_size: 2
|
|
enum: FMPICSEL
|
|
- name: LPTIM1SEL
|
|
description: LPTIM1SEL
|
|
bit_offset: 30
|
|
bit_size: 2
|
|
enum: LPTIMSEL
|
|
fieldset/PLLCFGR:
|
|
description: PLL configuration register
|
|
fields:
|
|
- name: PLLM
|
|
description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
|
|
bit_offset: 0
|
|
bit_size: 6
|
|
- name: PLLN
|
|
description: Main PLL (PLL) multiplication factor for VCO
|
|
bit_offset: 6
|
|
bit_size: 9
|
|
- name: PLLP
|
|
description: Main PLL (PLL) division factor for main system clock
|
|
bit_offset: 16
|
|
bit_size: 2
|
|
enum: PLLP
|
|
- name: PLLSRC
|
|
description: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: PLLSRC
|
|
- name: PLLQ
|
|
description: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
|
|
bit_offset: 24
|
|
bit_size: 4
|
|
- name: PLLR
|
|
description: PLL division factor for I2S and System clocks
|
|
bit_offset: 28
|
|
bit_size: 3
|
|
fieldset/SSCGR:
|
|
description: spread spectrum clock generation register
|
|
fields:
|
|
- name: MODPER
|
|
description: Modulation period
|
|
bit_offset: 0
|
|
bit_size: 13
|
|
- name: INCSTEP
|
|
description: Incrementation step
|
|
bit_offset: 13
|
|
bit_size: 15
|
|
- name: SPREADSEL
|
|
description: Spread Select
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: SPREADSEL
|
|
- name: SSCGEN
|
|
description: Spread spectrum modulation enable
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum/FMPICSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: APB
|
|
description: APB clock selected as I2C clock
|
|
value: 0
|
|
- name: SYSCLK
|
|
description: System clock selected as I2C clock
|
|
value: 1
|
|
- name: HSI
|
|
description: HSI clock selected as I2C clock
|
|
value: 2
|
|
enum/HPRE:
|
|
bit_size: 4
|
|
variants:
|
|
- name: Div1
|
|
description: SYSCLK not divided
|
|
value: 0
|
|
- name: Div2
|
|
description: SYSCLK divided by 2
|
|
value: 8
|
|
- name: Div4
|
|
description: SYSCLK divided by 4
|
|
value: 9
|
|
- name: Div8
|
|
description: SYSCLK divided by 8
|
|
value: 10
|
|
- name: Div16
|
|
description: SYSCLK divided by 16
|
|
value: 11
|
|
- name: Div64
|
|
description: SYSCLK divided by 64
|
|
value: 12
|
|
- name: Div128
|
|
description: SYSCLK divided by 128
|
|
value: 13
|
|
- name: Div256
|
|
description: SYSCLK divided by 256
|
|
value: 14
|
|
- name: Div512
|
|
description: SYSCLK divided by 512
|
|
value: 15
|
|
enum/ISSRC:
|
|
bit_size: 2
|
|
variants:
|
|
- name: PLLCLKR
|
|
description: I2Sx clock frequency = f(PLLCLK_R)
|
|
value: 0
|
|
- name: I2S_CKIN
|
|
description: I2Sx clock frequency = I2S_CKIN Alternate function input frequency
|
|
value: 1
|
|
- name: HSI_HSE
|
|
description: I2Sx clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22])
|
|
value: 3
|
|
enum/LPTIMSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: APB1
|
|
description: APB1 clock (PCLK1) selected as LPTILM1 clock
|
|
value: 0
|
|
- name: LSI
|
|
description: LSI clock is selected as LPTILM1 clock
|
|
value: 1
|
|
- name: HSI
|
|
description: HSI clock is selected as LPTILM1 clock
|
|
value: 2
|
|
- name: LSE
|
|
description: LSE clock is selected as LPTILM1 clock
|
|
value: 3
|
|
enum/MCO1SEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: HSI
|
|
description: HSI clock selected
|
|
value: 0
|
|
- name: LSE
|
|
description: LSE oscillator selected
|
|
value: 1
|
|
- name: HSE
|
|
description: HSE oscillator clock selected
|
|
value: 2
|
|
- name: PLL
|
|
description: PLL clock selected
|
|
value: 3
|
|
enum/MCO2SEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: SYSCLK
|
|
description: System clock (SYSCLK) selected
|
|
value: 0
|
|
- name: PLLI2S
|
|
description: PLLI2S clock selected
|
|
value: 1
|
|
- name: HSE
|
|
description: HSE oscillator clock selected
|
|
value: 2
|
|
- name: PLL
|
|
description: PLL clock selected
|
|
value: 3
|
|
enum/MCOPRE:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Div1
|
|
description: No division
|
|
value: 0
|
|
- name: Div2
|
|
description: Division by 2
|
|
value: 4
|
|
- name: Div3
|
|
description: Division by 3
|
|
value: 5
|
|
- name: Div4
|
|
description: Division by 4
|
|
value: 6
|
|
- name: Div5
|
|
description: Division by 5
|
|
value: 7
|
|
enum/PLLP:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Div2
|
|
description: PLLP=2
|
|
value: 0
|
|
- name: Div4
|
|
description: PLLP=4
|
|
value: 1
|
|
- name: Div6
|
|
description: PLLP=6
|
|
value: 2
|
|
- name: Div8
|
|
description: PLLP=8
|
|
value: 3
|
|
enum/PLLSRC:
|
|
bit_size: 1
|
|
variants:
|
|
- name: HSI
|
|
description: HSI clock selected as PLL and PLLI2S clock entry
|
|
value: 0
|
|
- name: HSE
|
|
description: HSE oscillator clock selected as PLL and PLLI2S clock entry
|
|
value: 1
|
|
enum/PPRE:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Div1
|
|
description: HCLK not divided
|
|
value: 0
|
|
- name: Div2
|
|
description: HCLK divided by 2
|
|
value: 4
|
|
- name: Div4
|
|
description: HCLK divided by 4
|
|
value: 5
|
|
- name: Div8
|
|
description: HCLK divided by 8
|
|
value: 6
|
|
- name: Div16
|
|
description: HCLK divided by 16
|
|
value: 7
|
|
enum/RTCSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: NoClock
|
|
description: No clock
|
|
value: 0
|
|
- name: LSE
|
|
description: LSE oscillator clock used as RTC clock
|
|
value: 1
|
|
- name: LSI
|
|
description: LSI oscillator clock used as RTC clock
|
|
value: 2
|
|
- name: HSE
|
|
description: HSE oscillator clock divided by a prescaler used as RTC clock
|
|
value: 3
|
|
enum/SPREADSEL:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Center
|
|
description: Center spread
|
|
value: 0
|
|
- name: Down
|
|
description: Down spread
|
|
value: 1
|
|
enum/SW:
|
|
bit_size: 2
|
|
variants:
|
|
- name: HSI
|
|
description: HSI oscillator used as system clock
|
|
value: 0
|
|
- name: HSE
|
|
description: HSE oscillator used as system clock
|
|
value: 1
|
|
- name: PLL
|
|
description: PLL used as system clock
|
|
value: 2
|
|
enum/TIMPRE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Mul2
|
|
description: If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx
|
|
value: 0
|
|
- name: Mul4
|
|
description: If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx
|
|
value: 1
|