451 lines
10 KiB
YAML
451 lines
10 KiB
YAML
---
|
|
block/LPUART1:
|
|
description: Universal synchronous asynchronous receiver transmitter
|
|
items:
|
|
- name: CR1
|
|
description: Control register 1
|
|
byte_offset: 0
|
|
fieldset: CR1
|
|
- name: CR2
|
|
description: Control register 2
|
|
byte_offset: 4
|
|
fieldset: CR2
|
|
- name: CR3
|
|
description: Control register 3
|
|
byte_offset: 8
|
|
fieldset: CR3
|
|
- name: BRR
|
|
description: Baud rate register
|
|
byte_offset: 12
|
|
fieldset: BRR
|
|
- name: RQR
|
|
description: Request register
|
|
byte_offset: 24
|
|
access: Write
|
|
fieldset: RQR
|
|
- name: ISR
|
|
description: Interrupt & status register
|
|
byte_offset: 28
|
|
access: Read
|
|
fieldset: ISR
|
|
- name: ICR
|
|
description: Interrupt flag clear register
|
|
byte_offset: 32
|
|
access: Write
|
|
fieldset: ICR
|
|
- name: RDR
|
|
description: Receive data register
|
|
byte_offset: 36
|
|
access: Read
|
|
fieldset: RDR
|
|
- name: TDR
|
|
description: Transmit data register
|
|
byte_offset: 40
|
|
fieldset: TDR
|
|
- name: PRESC
|
|
description: Prescaler register
|
|
byte_offset: 44
|
|
fieldset: PRESC
|
|
fieldset/BRR:
|
|
description: Baud rate register
|
|
fields:
|
|
- name: BRR
|
|
description: BRR
|
|
bit_offset: 0
|
|
bit_size: 20
|
|
fieldset/CR1:
|
|
description: Control register 1
|
|
fields:
|
|
- name: UE
|
|
description: USART enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: UESM
|
|
description: USART enable in Stop mode
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: RE
|
|
description: Receiver enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: TE
|
|
description: Transmitter enable
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: IDLEIE
|
|
description: IDLE interrupt enable
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: RXNEIE
|
|
description: RXNE interrupt enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: TCIE
|
|
description: Transmission complete interrupt enable
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: TXEIE
|
|
description: interrupt enable
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: PEIE
|
|
description: PE interrupt enable
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: PS
|
|
description: Parity selection
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: PCE
|
|
description: Parity control enable
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: WAKE
|
|
description: Receiver wakeup method
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: M0
|
|
description: Word length
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: MME
|
|
description: Mute mode enable
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: CMIE
|
|
description: Character match interrupt enable
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: DEDT0
|
|
description: DEDT0
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: DEDT1
|
|
description: DEDT1
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: DEDT2
|
|
description: DEDT2
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: DEDT3
|
|
description: DEDT3
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: DEDT4
|
|
description: Driver Enable de-assertion time
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: DEAT0
|
|
description: DEAT0
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: DEAT1
|
|
description: DEAT1
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: DEAT2
|
|
description: DEAT2
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: DEAT3
|
|
description: DEAT3
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: DEAT4
|
|
description: Driver Enable assertion time
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: M1
|
|
description: Word length
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: FIFOEN
|
|
description: FIFOEN
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: TXFEIE
|
|
description: TXFEIE
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: RXFFIE
|
|
description: RXFFIE
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/CR2:
|
|
description: Control register 2
|
|
fields:
|
|
- name: ADDM7
|
|
description: 7-bit Address Detection/4-bit Address Detection
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: STOP
|
|
description: STOP bits
|
|
bit_offset: 12
|
|
bit_size: 2
|
|
- name: SWAP
|
|
description: Swap TX/RX pins
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: RXINV
|
|
description: RX pin active level inversion
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: TXINV
|
|
description: TX pin active level inversion
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TAINV
|
|
description: Binary data inversion
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: MSBFIRST
|
|
description: Most significant bit first
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: ADD0_3
|
|
description: Address of the USART node
|
|
bit_offset: 24
|
|
bit_size: 4
|
|
- name: ADD4_7
|
|
description: Address of the USART node
|
|
bit_offset: 28
|
|
bit_size: 4
|
|
fieldset/CR3:
|
|
description: Control register 3
|
|
fields:
|
|
- name: EIE
|
|
description: Error interrupt enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: HDSEL
|
|
description: Half-duplex selection
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: DMAR
|
|
description: DMA enable receiver
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: DMAT
|
|
description: DMA enable transmitter
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: RTSE
|
|
description: RTS enable
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: CTSE
|
|
description: CTS enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: CTSIE
|
|
description: CTS interrupt enable
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: OVRDIS
|
|
description: Overrun Disable
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: DDRE
|
|
description: DMA Disable on Reception Error
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: DEM
|
|
description: Driver enable mode
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: DEP
|
|
description: Driver enable polarity selection
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: WUS
|
|
description: Wakeup from Stop mode interrupt flag selection
|
|
bit_offset: 20
|
|
bit_size: 2
|
|
- name: WUFIE
|
|
description: Wakeup from Stop mode interrupt enable
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: TXFTIE
|
|
description: TXFTIE
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: RXFTCFG
|
|
description: RXFTCFG
|
|
bit_offset: 25
|
|
bit_size: 3
|
|
- name: RXFTIE
|
|
description: RXFTIE
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: TXFTCFG
|
|
description: TXFTCFG
|
|
bit_offset: 29
|
|
bit_size: 3
|
|
fieldset/ICR:
|
|
description: Interrupt flag clear register
|
|
fields:
|
|
- name: PECF
|
|
description: Parity error clear flag
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: FECF
|
|
description: Framing error clear flag
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: NCF
|
|
description: Noise detected clear flag
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: ORECF
|
|
description: Overrun error clear flag
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: IDLECF
|
|
description: Idle line detected clear flag
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: TCCF
|
|
description: Transmission complete clear flag
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: CTSCF
|
|
description: CTS clear flag
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: CMCF
|
|
description: Character match clear flag
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: WUCF
|
|
description: Wakeup from Stop mode clear flag
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
fieldset/ISR:
|
|
description: Interrupt & status register
|
|
fields:
|
|
- name: PE
|
|
description: PE
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: FE
|
|
description: FE
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: NF
|
|
description: NF
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: ORE
|
|
description: ORE
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: IDLE
|
|
description: IDLE
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: RXNE
|
|
description: RXNE
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: TC
|
|
description: TC
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: TXE
|
|
description: TXE
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: CTSIF
|
|
description: CTSIF
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: CTS
|
|
description: CTS
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: BUSY
|
|
description: BUSY
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: CMF
|
|
description: CMF
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: SBKF
|
|
description: SBKF
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: RWU
|
|
description: RWU
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: WUF
|
|
description: WUF
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: TEACK
|
|
description: TEACK
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: REACK
|
|
description: REACK
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: TXFE
|
|
description: TXFE
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: RXFF
|
|
description: RXFF
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: RXFT
|
|
description: RXFT
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: TXFT
|
|
description: TXFT
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
fieldset/PRESC:
|
|
description: Prescaler register
|
|
fields:
|
|
- name: PRESCALER
|
|
description: PRESCALER
|
|
bit_offset: 0
|
|
bit_size: 4
|
|
fieldset/RDR:
|
|
description: Receive data register
|
|
fields:
|
|
- name: RDR
|
|
description: Receive data value
|
|
bit_offset: 0
|
|
bit_size: 9
|
|
fieldset/RQR:
|
|
description: Request register
|
|
fields:
|
|
- name: SBKRQ
|
|
description: Send break request
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: MMRQ
|
|
description: Mute mode request
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: RXFRQ
|
|
description: Receive data flush request
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: TXFRQ
|
|
description: TXFRQ
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
fieldset/TDR:
|
|
description: Transmit data register
|
|
fields:
|
|
- name: TDR
|
|
description: Transmit data value
|
|
bit_offset: 0
|
|
bit_size: 9
|