1618 lines
42 KiB
YAML
1618 lines
42 KiB
YAML
block/OTG:
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description: OTG_HS.
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items:
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- name: GOTGCTL
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description: Control and status register
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byte_offset: 0
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fieldset: GOTGCTL
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- name: GOTGINT
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description: Interrupt register
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byte_offset: 4
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fieldset: GOTGINT
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- name: GAHBCFG
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description: AHB configuration register
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byte_offset: 8
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fieldset: GAHBCFG
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- name: GUSBCFG
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description: USB configuration register
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byte_offset: 12
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fieldset: GUSBCFG
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- name: GRSTCTL
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description: Reset register
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byte_offset: 16
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fieldset: GRSTCTL
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- name: GINTSTS
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description: Core interrupt register
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byte_offset: 20
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fieldset: GINTSTS
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- name: GINTMSK
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description: Interrupt mask register
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byte_offset: 24
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fieldset: GINTMSK
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- name: GRXSTSR
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description: Receive status debug read register
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byte_offset: 28
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access: Read
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fieldset: GRXSTS
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- name: GRXSTSP
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description: Status read and pop register
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byte_offset: 32
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access: Read
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fieldset: GRXSTS
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- name: GRXFSIZ
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description: Receive FIFO size register
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byte_offset: 36
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fieldset: GRXFSIZ
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- name: DIEPTXF0
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description: Endpoint 0 transmit FIFO size register (device mode)
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byte_offset: 40
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fieldset: FSIZ
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- name: GCCFG_V1
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description: General core configuration register, for core_id 0x0000_1xxx
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byte_offset: 56
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fieldset: GCCFG_V1
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- name: GCCFG_V2
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description: General core configuration register, for core_id 0x0000_[23]xxx
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byte_offset: 56
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fieldset: GCCFG_V2
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- name: CID
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description: Core ID register
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byte_offset: 60
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fieldset: CID
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- name: GLPMCFG
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description: OTG core LPM configuration register
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byte_offset: 84
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fieldset: GLPMCFG
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- name: DIEPTXF
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description: Device IN endpoint transmit FIFO size register
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array:
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len: 7
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stride: 4
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byte_offset: 260
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fieldset: FSIZ
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- name: HCFG
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description: Host configuration register
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byte_offset: 1024
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fieldset: HCFG
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- name: HFIR
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description: Host frame interval register
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byte_offset: 1028
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fieldset: HFIR
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- name: HFNUM
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description: Host frame number/frame time remaining register
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byte_offset: 1032
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access: Read
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fieldset: HFNUM
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- name: HPTXSTS
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description: Periodic transmit FIFO/queue status register
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byte_offset: 1040
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access: Read
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- name: HAINT
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description: Host all channels interrupt register
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byte_offset: 1044
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access: Read
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fieldset: HAINT
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- name: HAINTMSK
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description: Host all channels interrupt mask register
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byte_offset: 1048
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fieldset: HAINTMSK
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- name: HPRT
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description: Host port control and status register
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byte_offset: 1088
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fieldset: HPRT
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- name: DCFG
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description: Device configuration register
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byte_offset: 2048
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fieldset: DCFG
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- name: DCTL
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description: Device control register
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byte_offset: 2052
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fieldset: DCTL
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- name: DSTS
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description: Device status register
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byte_offset: 2056
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access: Read
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fieldset: DSTS
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- name: DIEPMSK
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description: Device IN endpoint common interrupt mask register
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byte_offset: 2064
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fieldset: DIEPMSK
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- name: DOEPMSK
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description: Device OUT endpoint common interrupt mask register
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byte_offset: 2068
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fieldset: DOEPMSK
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- name: DAINT
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description: Device all endpoints interrupt register
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byte_offset: 2072
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access: Read
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fieldset: DAINT
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- name: DAINTMSK
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description: All endpoints interrupt mask register
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byte_offset: 2076
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fieldset: DAINTMSK
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- name: DVBUSDIS
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description: Device VBUS discharge time register
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byte_offset: 2088
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fieldset: DVBUSDIS
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- name: DVBUSPULSE
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description: Device VBUS pulsing time register
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byte_offset: 2092
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fieldset: DVBUSPULSE
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- name: DTHRCTL
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description: OTG device threshold control register.
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byte_offset: 2096
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fieldset: DTHRCTL
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- name: DIEPEMPMSK
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description: Device IN endpoint FIFO empty interrupt mask register
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byte_offset: 2100
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fieldset: DIEPEMPMSK
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- name: HS_DOEPEACHMSK1
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description: OTG device each OUT endpoint-1 interrupt mask register.
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byte_offset: 2180
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fieldset: HS_DOEPEACHMSK1
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- name: DIEPCTL
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description: Device IN endpoint control register
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array:
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len: 16
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stride: 32
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byte_offset: 2304
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fieldset: DIEPCTL
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- name: DIEPINT
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description: Device IN endpoint interrupt register
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array:
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len: 16
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stride: 32
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byte_offset: 2312
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fieldset: DIEPINT
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- name: DIEPTSIZ
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description: Device IN endpoint transfer size register
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array:
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len: 16
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stride: 32
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byte_offset: 2320
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fieldset: DIEPTSIZ
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- name: DIEPDMA
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description: Device IN endpoint DMA address register
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array:
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len: 16
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stride: 32
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byte_offset: 2324
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fieldset: DIEPDMA
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- name: DTXFSTS
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description: Device IN endpoint transmit FIFO status register
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array:
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len: 16
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stride: 32
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byte_offset: 2328
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access: Read
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fieldset: DTXFSTS
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- name: DOEPCTL
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description: Device OUT endpoint control register
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array:
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len: 16
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stride: 32
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byte_offset: 2816
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fieldset: DOEPCTL
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- name: DOEPINT
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description: Device OUT endpoint interrupt register
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array:
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len: 16
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stride: 32
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byte_offset: 2824
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fieldset: DOEPINT
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- name: DOEPTSIZ
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description: Device OUT endpoint transfer size register
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array:
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len: 16
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stride: 32
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byte_offset: 2832
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fieldset: DOEPTSIZ
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- name: DOEPDMA
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description: OTG device OUT endpoint 0 DMA address register.
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byte_offset: 2836
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array:
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len: 16
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stride: 32
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fieldset: DOEPDMA
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- name: PCGCCTL
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description: Power and clock gating control register
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byte_offset: 3584
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fieldset: PCGCCTL
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- name: FIFO
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description: Device endpoint / host channel FIFO register
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array:
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len: 16
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stride: 4096
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byte_offset: 4096
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fieldset: FIFO
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fieldset/CID:
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description: Core ID register
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fields:
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- name: PRODUCT_ID
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description: Product ID field
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bit_offset: 0
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bit_size: 32
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fieldset/DAINT:
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description: Device all endpoints interrupt register
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fields:
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- name: IEPINT
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description: IN endpoint interrupt bits
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bit_offset: 0
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bit_size: 16
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- name: OEPINT
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description: OUT endpoint interrupt bits
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bit_offset: 16
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bit_size: 16
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fieldset/DAINTMSK:
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description: All endpoints interrupt mask register
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fields:
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- name: IEPM
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description: IN EP interrupt mask bits
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bit_offset: 0
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bit_size: 16
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- name: OEPM
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description: OUT EP interrupt mask bits
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bit_offset: 16
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bit_size: 16
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fieldset/DCFG:
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description: Device configuration register
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fields:
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- name: DSPD
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description: Device speed
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bit_offset: 0
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bit_size: 2
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enum: DSPD
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- name: NZLSOHSK
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description: Non-zero-length status OUT handshake
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bit_offset: 2
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bit_size: 1
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- name: DAD
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description: Device address
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bit_offset: 4
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bit_size: 7
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- name: PFIVL
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description: PFIVL.
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bit_offset: 11
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bit_size: 2
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enum: PFIVL
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- name: ERRATIM
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description: ERRATIM.
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bit_offset: 15
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bit_size: 1
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fieldset/DCTL:
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description: Device control register
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fields:
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- name: RWUSIG
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description: Remote wakeup signaling
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bit_offset: 0
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bit_size: 1
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- name: SDIS
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description: Soft disconnect
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bit_offset: 1
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bit_size: 1
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- name: GINSTS
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description: Global IN NAK status
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bit_offset: 2
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bit_size: 1
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- name: GONSTS
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description: Global OUT NAK status
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bit_offset: 3
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bit_size: 1
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- name: TCTL
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description: Test control
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bit_offset: 4
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bit_size: 3
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- name: SGINAK
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description: SGINAK.
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bit_offset: 7
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bit_size: 1
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- name: CGINAK
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description: CGINAK.
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bit_offset: 8
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bit_size: 1
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- name: SGONAK
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description: SGONAK.
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bit_offset: 9
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bit_size: 1
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- name: CGONAK
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description: CGONAK.
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bit_offset: 10
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bit_size: 1
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- name: POPRGDNE
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description: POPRGDNE.
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bit_offset: 11
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bit_size: 1
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- name: DSBESLRJCT
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description: DSBESLRJCT.
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bit_offset: 18
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bit_size: 1
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fieldset/DIEPCTL:
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description: Device endpoint control register
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fields:
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- name: MPSIZ
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description: MPSIZ
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bit_offset: 0
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bit_size: 11
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- name: MPSIZ0
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description: MPSIZ for endpoint 0
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bit_offset: 0
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bit_size: 2
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- name: USBAEP
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description: USBAEP
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bit_offset: 15
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bit_size: 1
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- name: EONUM_DPID
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description: EONUM/DPID
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bit_offset: 16
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bit_size: 1
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- name: NAKSTS
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description: NAKSTS
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bit_offset: 17
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bit_size: 1
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- name: EPTYP
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description: EPTYP
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bit_offset: 18
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bit_size: 2
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enum: EPTYP
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- name: SNPM
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description: SNPM
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bit_offset: 20
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bit_size: 1
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- name: STALL
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description: STALL
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bit_offset: 21
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bit_size: 1
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- name: TXFNUM
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description: TXFNUM
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bit_offset: 22
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bit_size: 4
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- name: CNAK
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description: CNAK
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bit_offset: 26
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bit_size: 1
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- name: SNAK
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description: SNAK
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bit_offset: 27
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bit_size: 1
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- name: SD0PID_SEVNFRM
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description: SD0PID/SEVNFRM
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bit_offset: 28
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bit_size: 1
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- name: SODDFRM_SD1PID
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description: SODDFRM/SD1PID
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bit_offset: 29
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bit_size: 1
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- name: EPDIS
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description: EPDIS
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bit_offset: 30
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bit_size: 1
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- name: EPENA
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description: EPENA
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bit_offset: 31
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bit_size: 1
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fieldset/DIEPEMPMSK:
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description: This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_DIEPINTx).
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fields:
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- name: INEPTXFEM
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description: INEPTXFEM.
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bit_offset: 0
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bit_size: 16
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fieldset/DIEPINT:
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description: Device endpoint interrupt register
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fields:
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- name: XFRC
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description: XFRC
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bit_offset: 0
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bit_size: 1
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- name: EPDISD
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description: EPDISD
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bit_offset: 1
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bit_size: 1
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- name: TOC
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description: TOC
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bit_offset: 3
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bit_size: 1
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- name: ITTXFE
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description: ITTXFE
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bit_offset: 4
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bit_size: 1
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- name: INEPNM
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description: INEPNM.
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bit_offset: 5
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bit_size: 1
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- name: INEPNE
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description: INEPNE
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bit_offset: 6
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bit_size: 1
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- name: TXFE
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description: TXFE
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bit_offset: 7
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bit_size: 1
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- name: PKTDRPSTS
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description: PKTDRPSTS.
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bit_offset: 11
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bit_size: 1
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- name: NAK
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description: NAK.
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bit_offset: 13
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bit_size: 1
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fieldset/DIEPMSK:
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description: This register works with each of the DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTx register can be masked by writing to the corresponding bit in this register. Status bits are masked by default.
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fields:
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- name: XFRCM
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description: XFRCM.
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bit_offset: 0
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bit_size: 1
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- name: EPDM
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description: EPDM.
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bit_offset: 1
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bit_size: 1
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- name: AHBERRM
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description: AHBERRM.
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bit_offset: 2
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bit_size: 1
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- name: TOM
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description: TOM.
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bit_offset: 3
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bit_size: 1
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- name: ITTXFEMSK
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description: ITTXFEMSK.
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bit_offset: 4
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bit_size: 1
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- name: INEPNMM
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description: INEPNMM.
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bit_offset: 5
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bit_size: 1
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- name: INEPNEM
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description: INEPNEM.
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bit_offset: 6
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bit_size: 1
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- name: TXFURM
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description: TXFURM.
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bit_offset: 8
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bit_size: 1
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- name: NAKM
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description: NAKM.
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bit_offset: 13
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bit_size: 1
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fieldset/DIEPTSIZ:
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description: The application must modify this register before enabling endpoint 0.
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fields:
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- name: XFRSIZ
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description: XFRSIZ.
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bit_offset: 0
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bit_size: 19
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- name: PKTCNT
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description: PKTCNT.
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bit_offset: 19
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bit_size: 10
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- name: MCNT
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description: Multi count
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bit_offset: 29
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bit_size: 2
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fieldset/DOEPCTL:
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description: Device endpoint control register
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fields:
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- name: MPSIZ
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description: MPSIZ
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bit_offset: 0
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bit_size: 11
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- name: MPSIZ0
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description: MPSIZ for endpoint 0
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bit_offset: 0
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bit_size: 2
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access: Read
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- name: USBAEP
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description: USBAEP
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bit_offset: 15
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bit_size: 1
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- name: EONUM_DPID
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description: EONUM/DPID
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bit_offset: 16
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bit_size: 1
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- name: NAKSTS
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description: NAKSTS
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bit_offset: 17
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bit_size: 1
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- name: EPTYP
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description: EPTYP
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bit_offset: 18
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bit_size: 2
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enum: EPTYP
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- name: SNPM
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description: SNPM
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bit_offset: 20
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bit_size: 1
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- name: STALL
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description: STALL
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bit_offset: 21
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bit_size: 1
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- name: CNAK
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description: CNAK
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bit_offset: 26
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bit_size: 1
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- name: SNAK
|
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description: SNAK
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bit_offset: 27
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bit_size: 1
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- name: SD0PID_SEVNFRM
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description: SD0PID/SEVNFRM
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bit_offset: 28
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bit_size: 1
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- name: SODDFRM
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description: SODDFRM
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bit_offset: 29
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bit_size: 1
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- name: EPDIS
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description: EPDIS
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bit_offset: 30
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bit_size: 1
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- name: EPENA
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description: EPENA
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bit_offset: 31
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bit_size: 1
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fieldset/DOEPDMA:
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description: OTG device OUT endpoint 0 DMA address register.
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fields:
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- name: DMAADDR
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description: DMAADDR.
|
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bit_offset: 0
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bit_size: 32
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|
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fieldset/DIEPDMA:
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description: OTG device OUT endpoint 0 DMA address register.
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fields:
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- name: DMAADDR
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description: DMAADDR.
|
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bit_offset: 0
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bit_size: 32
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|
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fieldset/DOEPINT:
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description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
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fields:
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- name: XFRC
|
|
description: XFRC.
|
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bit_offset: 0
|
|
bit_size: 1
|
|
- name: EPDISD
|
|
description: EPDISD.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: AHBERR
|
|
description: AHBERR.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: STUP
|
|
description: STUP.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: OTEPDIS
|
|
description: OTEPDIS.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: STSPHSRX
|
|
description: STSPHSRX.
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: B2BSTUP
|
|
description: B2BSTUP.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: OUTPKTERR
|
|
description: OUTPKTERR.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: BNA
|
|
description: BNA.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: BERR
|
|
description: BERR.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: NAK
|
|
description: NAK.
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: NYET
|
|
description: NYET.
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: STPKTRX
|
|
description: STPKTRX.
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
|
|
fieldset/DOEPMSK:
|
|
description: This register works with each of the DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the DOEPINTx register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.
|
|
fields:
|
|
- name: XFRCM
|
|
description: XFRCM.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: EPDM
|
|
description: EPDM.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: AHBERRM
|
|
description: AHBERRM.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: STUPM
|
|
description: STUPM.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: OTEPDM
|
|
description: OTEPDM.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: STSPHSRXM
|
|
description: STSPHSRXM.
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: B2BSTUPM
|
|
description: B2BSTUPM.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: OUTPKTERRM
|
|
description: OUTPKTERRM.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: BERRM
|
|
description: BERRM.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: NAKMSK
|
|
description: NAKMSK.
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: NYETMSK
|
|
description: NYETMSK.
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
fieldset/DOEPTSIZ:
|
|
description: The application must modify this register before enabling endpoint 0.
|
|
fields:
|
|
- name: XFRSIZ
|
|
description: XFRSIZ.
|
|
bit_offset: 0
|
|
bit_size: 19
|
|
- name: PKTCNT
|
|
description: PKTCNT.
|
|
bit_offset: 19
|
|
bit_size: 10
|
|
- name: STUPCNT
|
|
description: STUPCNT.
|
|
bit_offset: 29
|
|
bit_size: 2
|
|
- name: RXDPID
|
|
description: RXDPID.
|
|
bit_offset: 29
|
|
bit_size: 2
|
|
|
|
fieldset/DSTS:
|
|
description: This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (DAINT) register.
|
|
fields:
|
|
- name: SUSPSTS
|
|
description: SUSPSTS.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: ENUMSPD
|
|
description: ENUMSPD.
|
|
bit_offset: 1
|
|
bit_size: 2
|
|
enum: DSPD
|
|
- name: EERR
|
|
description: EERR.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: FNSOF
|
|
description: FNSOF.
|
|
bit_offset: 8
|
|
bit_size: 14
|
|
- name: DEVLNSTS
|
|
description: DEVLNSTS.
|
|
bit_offset: 22
|
|
bit_size: 2
|
|
fieldset/DTHRCTL:
|
|
description: OTG device threshold control register.
|
|
fields:
|
|
- name: NONISOTHREN
|
|
description: Nonisochronous IN endpoints threshold enable. When this bit is set, the core enables thresholding for nonisochronous IN endpoints.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: ISOTHREN
|
|
description: ISO IN endpoint threshold enable. When this bit is set, the core enables thresholding for isochronous IN endpoints.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: TXTHRLEN
|
|
description: Transmit threshold length. This field specifies the transmit thresholding size in 32-bit words. This field specifies the amount of data in bytes to be in the corresponding endpoint transmit FIFO, before the core can start transmitting on the USB. The threshold length has to be at least eight 32-bit words. This field controls both isochronous and nonisochronous IN endpoint thresholds. The recommended value for TXTHRLEN is to be the same as the programmed AHB burst length (HBSTLEN bit in OTG_GAHBCFG).
|
|
bit_offset: 2
|
|
bit_size: 9
|
|
- name: RXTHREN
|
|
description: Receive threshold enable. When this bit is set, the core enables thresholding in the receive direction.
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: RXTHRLEN
|
|
description: Receive threshold length. This field specifies the receive thresholding size in 32-bit words. This field also specifies the amount of data received on the USB before the core can start transmitting on the AHB. The threshold length has to be at least eight 32-bit words. The recommended value for RXTHRLEN is to be the same as the programmed AHB burst length (HBSTLEN bit in OTG_GAHBCFG).
|
|
bit_offset: 17
|
|
bit_size: 9
|
|
- name: ARPEN
|
|
description: Arbiter parking enable. This bit controls internal DMA arbiter parking for IN endpoints. When thresholding is enabled and this bit is set to one, then the arbiter parks on the IN endpoint for which there is a token received on the USB. This is done to avoid getting into underrun conditions. By default parking is enabled.
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
fieldset/DTXFSTS:
|
|
description: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
|
|
fields:
|
|
- name: INEPTFSAV
|
|
description: INEPTFSAV.
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
|
|
fieldset/DVBUSDIS:
|
|
description: This register specifies the VBUS discharge time after VBUS pulsing during SRP.
|
|
fields:
|
|
- name: VBUSDT
|
|
description: VBUSDT.
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/DVBUSPULSE:
|
|
description: This register specifies the VBUS pulsing time during SRP.
|
|
fields:
|
|
- name: DVBUSP
|
|
description: DVBUSP.
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/FSIZ:
|
|
description: FIFO size register
|
|
fields:
|
|
- name: SA
|
|
description: RAM start address
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
- name: FD
|
|
description: FIFO depth
|
|
bit_offset: 16
|
|
bit_size: 16
|
|
fieldset/FIFO:
|
|
description: FIFO register
|
|
fields:
|
|
- name: DATA
|
|
description: Data
|
|
bit_offset: 0
|
|
bit_size: 32
|
|
fieldset/GAHBCFG:
|
|
description: This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB.
|
|
fields:
|
|
- name: GINTMSK
|
|
description: GINTMSK.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: TXFELVL
|
|
description: TXFELVL.
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: PTXFELVL
|
|
description: PTXFELVL.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
fieldset/GCCFG_V1:
|
|
description: General core configuration register
|
|
fields:
|
|
- name: PWRDWN
|
|
description: Power down
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: VBUSASEN
|
|
description: Enable the VBUS "A" sensing device
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: VBUSBSEN
|
|
description: Enable the VBUS "B" sensing device
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: SOFOUTEN
|
|
description: SOF output enable
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: NOVBUSSENS
|
|
description: VBUS sensing disable
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
fieldset/GCCFG_V2:
|
|
description: General core configuration register
|
|
fields:
|
|
- name: DCDET
|
|
description: Data contact detection (DCD) status
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: PDET
|
|
description: Primary detection (PD) status
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: SDET
|
|
description: Secondary detection (SD) status
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: PS2DET
|
|
description: DM pull-up detection status
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: PWRDWN
|
|
description: Power down
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: BCDEN
|
|
description: Battery charging detector (BCD) enable
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: DCDEN
|
|
description: Data contact detection (DCD) mode enable
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: PDEN
|
|
description: Primary detection (PD) mode enable
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: SDEN
|
|
description: Secondary detection (SD) mode enable
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: VBDEN
|
|
description: USB VBUS detection enable
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: PHYHSEN
|
|
description: Internal high-speed PHY enable.
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
fieldset/GINTMSK:
|
|
description: This register works with the core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the core interrupt (GINTSTS) register bit corresponding to that interrupt is still set.
|
|
fields:
|
|
- name: MMISM
|
|
description: MMISM.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: OTGINT
|
|
description: OTGINT.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: SOFM
|
|
description: SOFM.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: RXFLVLM
|
|
description: RXFLVLM.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: NPTXFEM
|
|
description: NPTXFEM.
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: GINAKEFFM
|
|
description: GINAKEFFM.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: GONAKEFFM
|
|
description: GONAKEFFM.
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: ESUSPM
|
|
description: ESUSPM.
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: USBSUSPM
|
|
description: USBSUSPM.
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: USBRST
|
|
description: USBRST.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: ENUMDNEM
|
|
description: ENUMDNEM.
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: ISOODRPM
|
|
description: ISOODRPM.
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: EOPFM
|
|
description: EOPFM.
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: IEPINT
|
|
description: IEPINT.
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: OEPINT
|
|
description: OEPINT.
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: IISOIXFRM
|
|
description: IISOIXFRM.
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: IPXFRM
|
|
description: IPXFRM.
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: FSUSPM
|
|
description: FSUSPM.
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: RSTDETM
|
|
description: RSTDETM.
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: PRTIM
|
|
description: PRTIM.
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: HCIM
|
|
description: HCIM.
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: PTXFEM
|
|
description: PTXFEM.
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: LPMINTM
|
|
description: LPMINTM.
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: CIDSCHGM
|
|
description: CIDSCHGM.
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: DISCINT
|
|
description: DISCINT.
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: SRQIM
|
|
description: SRQIM.
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: WUIM
|
|
description: WUIM.
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/GINTSTS:
|
|
description: This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode, while others are valid in device mode only. This register also indicates the current mode. To clear the interrupt status bits of the rc_w1 type, the application must write 1 into the bit. The FIFO status interrupts are read-only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically. The application must clear the GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization.
|
|
fields:
|
|
- name: CMOD
|
|
description: CMOD.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: MMIS
|
|
description: MMIS.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: OTGINT
|
|
description: OTGINT.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: SOF
|
|
description: SOF.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: RXFLVL
|
|
description: RXFLVL.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: NPTXFE
|
|
description: NPTXFE.
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: GINAKEFF
|
|
description: GINAKEFF.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: GONAKEFF
|
|
description: GONAKEFF.
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: ESUSP
|
|
description: ESUSP.
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: USBSUSP
|
|
description: USBSUSP.
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: USBRST
|
|
description: USBRST.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: ENUMDNE
|
|
description: ENUMDNE.
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: ISOODRP
|
|
description: ISOODRP.
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: EOPF
|
|
description: EOPF.
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: IEPINT
|
|
description: IEPINT.
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: OEPINT
|
|
description: OEPINT.
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: IISOIXFR
|
|
description: IISOIXFR.
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: IPXFR
|
|
description: IPXFR.
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: DATAFSUSP
|
|
description: DATAFSUSP.
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: RSTDET
|
|
description: RSTDET.
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: HPRTINT
|
|
description: HPRTINT.
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: HCINT
|
|
description: HCINT.
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: PTXFE
|
|
description: PTXFE.
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: LPMINT
|
|
description: LPMINT.
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: CIDSCHG
|
|
description: CIDSCHG.
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: DISCINT
|
|
description: DISCINT.
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: SRQINT
|
|
description: SRQINT.
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: WKUPINT
|
|
description: WKUPINT.
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/GLPMCFG:
|
|
description: OTG core LPM configuration register.
|
|
fields:
|
|
- name: LPMEN
|
|
description: LPMEN.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LPMACK
|
|
description: LPMACK.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: BESL
|
|
description: BESL.
|
|
bit_offset: 2
|
|
bit_size: 4
|
|
- name: REMWAKE
|
|
description: REMWAKE.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: L1SSEN
|
|
description: L1SSEN.
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: BESLTHRS
|
|
description: BESLTHRS.
|
|
bit_offset: 8
|
|
bit_size: 4
|
|
- name: L1DSEN
|
|
description: L1DSEN.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: LPMRSP
|
|
description: LPMRSP.
|
|
bit_offset: 13
|
|
bit_size: 2
|
|
- name: SLPSTS
|
|
description: SLPSTS.
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: L1RSMOK
|
|
description: L1RSMOK.
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: LPMCHIDX
|
|
description: LPMCHIDX.
|
|
bit_offset: 17
|
|
bit_size: 4
|
|
- name: LPMRCNT
|
|
description: LPMRCNT.
|
|
bit_offset: 21
|
|
bit_size: 3
|
|
- name: SNDLPM
|
|
description: SNDLPM.
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: LPMRCNTSTS
|
|
description: LPMRCNTSTS.
|
|
bit_offset: 25
|
|
bit_size: 3
|
|
- name: ENBESL
|
|
description: ENBESL.
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
fieldset/GOTGCTL:
|
|
description: The GOTGCTL register controls the behavior and reflects the status of the OTG function of the core.
|
|
fields:
|
|
- name: SRQSCS
|
|
description: SRQSCS.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: SRQ
|
|
description: SRQ.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: VBVALOEN
|
|
description: VBVALOEN.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: VBVALOVAL
|
|
description: VBVALOVAL.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: AVALOEN
|
|
description: AVALOEN.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: AVALOVAL
|
|
description: AVALOVAL.
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: BVALOEN
|
|
description: BVALOEN.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: BVALOVAL
|
|
description: BVALOVAL.
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: HNGSCS
|
|
description: HNGSCS.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: HNPRQ
|
|
description: HNPRQ.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HSHNPEN
|
|
description: HSHNPEN.
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: DHNPEN
|
|
description: DHNPEN.
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: EHEN
|
|
description: EHEN.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: CIDSTS
|
|
description: CIDSTS.
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: DBCT
|
|
description: DBCT.
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: ASVLD
|
|
description: ASVLD.
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: BSVLD
|
|
description: BSVLD.
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: OTGVER
|
|
description: OTGVER.
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: CURMOD
|
|
description: CURMOD.
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
fieldset/GOTGINT:
|
|
description: The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt.
|
|
fields:
|
|
- name: SEDET
|
|
description: SEDET.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: SRSSCHG
|
|
description: SRSSCHG.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: HNSSCHG
|
|
description: HNSSCHG.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HNGDET
|
|
description: HNGDET.
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: ADTOCHG
|
|
description: ADTOCHG.
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: DBCDNE
|
|
description: DBCDNE.
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
fieldset/GRSTCTL:
|
|
description: The application uses this register to reset various hardware features inside the core.
|
|
fields:
|
|
- name: CSRST
|
|
description: CSRST.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: PSRST
|
|
description: PSRST.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: FSRST
|
|
description: FSRST.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: RXFFLSH
|
|
description: RXFFLSH.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: TXFFLSH
|
|
description: TXFFLSH.
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: TXFNUM
|
|
description: TXFNUM.
|
|
bit_offset: 6
|
|
bit_size: 5
|
|
- name: DMAREQ
|
|
description: DMAREQ.
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: AHBIDL
|
|
description: AHBIDL.
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/GRXFSIZ:
|
|
description: The application can program the RAM size that must be allocated to the Rx FIFO.
|
|
fields:
|
|
- name: RXFD
|
|
description: RXFD.
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/GRXSTS:
|
|
description: Status read and pop register
|
|
fields:
|
|
- name: EPNUM
|
|
description: Endpoint number (device mode) / Channel number (host mode)
|
|
bit_offset: 0
|
|
bit_size: 4
|
|
- name: BCNT
|
|
description: Byte count
|
|
bit_offset: 4
|
|
bit_size: 11
|
|
- name: DPID
|
|
description: Data PID
|
|
bit_offset: 15
|
|
bit_size: 2
|
|
- name: PKTSTSD
|
|
description: Packet status (device mode)
|
|
bit_offset: 17
|
|
bit_size: 4
|
|
enum: PKTSTSD
|
|
- name: FRMNUM
|
|
description: Frame number (device mode)
|
|
bit_offset: 21
|
|
bit_size: 4
|
|
- name: STSPHST
|
|
description: STSPHST.
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
|
|
fieldset/GUSBCFG:
|
|
description: This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming.
|
|
fields:
|
|
- name: TOCAL
|
|
description: TOCAL.
|
|
bit_offset: 0
|
|
bit_size: 3
|
|
- name: PHYSEL
|
|
description: PHYSEL.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: SRPCAP
|
|
description: SRPCAP.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: HNPCAP
|
|
description: HNPCAP.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: TRDT
|
|
description: TRDT.
|
|
bit_offset: 10
|
|
bit_size: 4
|
|
- name: PHYLPC
|
|
description: PHYLPC.
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: TSDPS
|
|
description: TSDPS.
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: FHMOD
|
|
description: FHMOD.
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: FDMOD
|
|
description: FDMOD.
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
fieldset/HAINT:
|
|
description: When a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in GINTSTS). This is shown in Figure724. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding host channel-x interrupt register.
|
|
fields:
|
|
- name: HAINT
|
|
description: HAINT.
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/HAINTMSK:
|
|
description: The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits.
|
|
fields:
|
|
- name: HAINTM
|
|
description: HAINTM.
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/HCFG:
|
|
description: This register configures the core after power-on. Do not make changes to this register after initializing the host.
|
|
fields:
|
|
- name: FSLSPCS
|
|
description: FSLSPCS.
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: FSLSS
|
|
description: FSLSS.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
fieldset/HFIR:
|
|
description: This register stores the frame interval information for the current speed to which the OTG controller has enumerated.
|
|
fields:
|
|
- name: FRIVL
|
|
description: FRIVL.
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
- name: RLDCTRL
|
|
description: RLDCTRL.
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
fieldset/HFNUM:
|
|
description: This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame.
|
|
fields:
|
|
- name: FRNUM
|
|
description: FRNUM.
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
- name: FTREM
|
|
description: FTREM.
|
|
bit_offset: 16
|
|
bit_size: 16
|
|
fieldset/HPRT:
|
|
description: This register is available only in host mode. Currently, the OTG host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure724. The rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (HPRTINT bit in GINTSTS). On a port interrupt, the application must read this register and clear the bit that caused the interrupt. For the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt.
|
|
fields:
|
|
- name: PCSTS
|
|
description: PCSTS.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: PCDET
|
|
description: PCDET.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: PENA
|
|
description: PENA.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: PENCHNG
|
|
description: PENCHNG.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: POCA
|
|
description: POCA.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: POCCHNG
|
|
description: POCCHNG.
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: PRES
|
|
description: PRES.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: PSUSP
|
|
description: PSUSP.
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: PRST
|
|
description: PRST.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: PLSTS
|
|
description: PLSTS.
|
|
bit_offset: 10
|
|
bit_size: 2
|
|
- name: PPWR
|
|
description: PPWR.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: PTCTL
|
|
description: PTCTL.
|
|
bit_offset: 13
|
|
bit_size: 4
|
|
- name: PSPD
|
|
description: PSPD.
|
|
bit_offset: 17
|
|
bit_size: 2
|
|
fieldset/HS_DOEPEACHMSK1:
|
|
description: OTG device each OUT endpoint-1 interrupt mask register.
|
|
fields:
|
|
- name: XFRCM
|
|
description: XFRCM.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: EPDM
|
|
description: EPDM.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: AHBERRM
|
|
description: AHBERRM.
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: STUPM
|
|
description: STUPM.
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: OTEPDM
|
|
description: OTEPDM.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: B2BSTUPM
|
|
description: B2BSTUPM.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: OUTPKTERRM
|
|
description: OUTPKTERRM.
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: BNAM
|
|
description: BNAM.
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: BERRM
|
|
description: BERRM.
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: NAKMSK
|
|
description: NAKMSK.
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: NYETMSK
|
|
description: NYETMSK.
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
fieldset/PCGCCTL:
|
|
description: This register is available in host and device modes.
|
|
fields:
|
|
- name: STPPCLK
|
|
description: STPPCLK.
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: GATEHCLK
|
|
description: GATEHCLK.
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: PHYSUSP
|
|
description: PHYSUSP.
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: ENL1GTG
|
|
description: ENL1GTG.
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: PHYSLEEP
|
|
description: PHYSLEEP.
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: SUSP
|
|
description: SUSP.
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum/DSPD:
|
|
bit_size: 2
|
|
variants:
|
|
- name: HIGH_SPEED
|
|
description: High speed
|
|
value: 0
|
|
- name: FULL_SPEED_EXTERNAL
|
|
description: Full speed using external ULPI PHY
|
|
value: 1
|
|
- name: FULL_SPEED_INTERNAL
|
|
description: Full speed using internal embedded PHY
|
|
value: 3
|
|
enum/EPTYP:
|
|
bit_size: 2
|
|
variants:
|
|
- name: CONTROL
|
|
value: 0
|
|
- name: ISOCHRONOUS
|
|
value: 1
|
|
- name: BULK
|
|
value: 2
|
|
- name: INTERRUPT
|
|
value: 3
|
|
|
|
enum/PKTSTSD:
|
|
bit_size: 4
|
|
variants:
|
|
- name: OUT_NAK
|
|
description: Global OUT NAK (triggers an interrupt)
|
|
value: 1
|
|
- name: OUT_DATA_RX
|
|
description: OUT data packet received
|
|
value: 2
|
|
- name: OUT_DATA_DONE
|
|
description: OUT transfer completed (triggers an interrupt)
|
|
value: 3
|
|
- name: SETUP_DATA_DONE
|
|
description: SETUP transaction completed (triggers an interrupt)
|
|
value: 4
|
|
- name: SETUP_DATA_RX
|
|
description: SETUP data packet received
|
|
value: 6
|
|
|
|
enum/PFIVL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: FRAME_INTERVAL_80
|
|
description: 80% of the frame interval
|
|
value: 0
|
|
- name: FRAME_INTERVAL_85
|
|
description: 85% of the frame interval
|
|
value: 1
|
|
- name: FRAME_INTERVAL_90
|
|
description: 90% of the frame interval
|
|
value: 2
|
|
- name: FRAME_INTERVAL_95
|
|
description: 95% of the frame interval
|
|
value: 3
|