1156 lines
30 KiB
YAML
1156 lines
30 KiB
YAML
---
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block/RCC:
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description: Reset and clock control
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items:
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- name: CR
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description: Clock control register
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byte_offset: 0
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fieldset: CR
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- name: ICSCR
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description: Internal clock sources calibration register
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byte_offset: 4
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fieldset: ICSCR
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- name: CFGR
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description: Clock configuration register
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byte_offset: 8
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fieldset: CFGR
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- name: PLLSYSCFGR
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description: PLL configuration register
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byte_offset: 12
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fieldset: PLLSYSCFGR
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- name: CRRCR
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description: RCC clock recovery RC register
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byte_offset: 20
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access: Read
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fieldset: CRRCR
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- name: CIER
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description: Clock interrupt enable register
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byte_offset: 24
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fieldset: CIER
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- name: CIFR
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description: Clock interrupt flag register
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byte_offset: 28
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access: Read
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fieldset: CIFR
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- name: CICR
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description: Clock interrupt clear register
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byte_offset: 32
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access: Write
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fieldset: CICR
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- name: GPIORSTR
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description: GPIO reset register
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byte_offset: 36
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fieldset: GPIORSTR
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- name: AHBRSTR
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description: AHB peripheral reset register
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byte_offset: 40
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fieldset: AHBRSTR
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- name: APBRSTR1
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description: APB peripheral reset register 1
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byte_offset: 44
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fieldset: APBRSTR1
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- name: APBRSTR2
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description: APB peripheral reset register 2
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byte_offset: 48
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fieldset: APBRSTR2
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- name: GPIOENR
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description: GPIO clock enable register
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byte_offset: 52
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fieldset: GPIOENR
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- name: AHBENR
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description: AHB peripheral clock enable register
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byte_offset: 56
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fieldset: AHBENR
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- name: APBENR1
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description: APB peripheral clock enable register 1
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byte_offset: 60
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fieldset: APBENR1
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- name: APBENR2
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description: APB peripheral clock enable register 2
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byte_offset: 64
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fieldset: APBENR2
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- name: GPIOSMENR
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description: GPIO in Sleep mode clock enable register
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byte_offset: 68
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fieldset: GPIOSMENR
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- name: AHBSMENR
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description: AHB peripheral clock enable in Sleep mode register
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byte_offset: 72
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fieldset: AHBSMENR
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- name: APBSMENR1
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description: APB peripheral clock enable in Sleep mode register 1
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byte_offset: 76
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fieldset: APBSMENR1
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- name: APBSMENR2
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description: APB peripheral clock enable in Sleep mode register 2
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byte_offset: 80
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fieldset: APBSMENR2
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- name: CCIPR
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description: Peripherals independent clock configuration register
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byte_offset: 84
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fieldset: CCIPR
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- name: CCIPR2
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description: Peripherals independent clock configuration register 2
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byte_offset: 88
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fieldset: CCIPR2
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- name: BDCR
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description: RTC domain control register
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byte_offset: 92
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fieldset: BDCR
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- name: CSR
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description: Control/status register
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byte_offset: 96
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fieldset: CSR
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fieldset/AHBENR:
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description: AHB peripheral clock enable register
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fields:
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- name: DMA1EN
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description: DMA1 clock enable
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bit_offset: 0
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bit_size: 1
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- name: DMAEN
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description: DMA clock enable
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bit_offset: 0
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bit_size: 1
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- name: DMA2EN
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description: DMA2 clock enable
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bit_offset: 1
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bit_size: 1
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- name: FLASHEN
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description: Flash memory interface clock enable
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bit_offset: 8
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bit_size: 1
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- name: CRCEN
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description: CRC clock enable
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bit_offset: 12
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bit_size: 1
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- name: AESEN
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description: AES hardware accelerator
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bit_offset: 16
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bit_size: 1
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- name: RNGEN
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description: Random number generator clock enable
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bit_offset: 18
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bit_size: 1
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fieldset/AHBRSTR:
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description: AHB peripheral reset register
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fields:
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- name: DMA1RST
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description: DMA1 reset
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bit_offset: 0
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bit_size: 1
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- name: DMARST
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description: DMA1 reset
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bit_offset: 0
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bit_size: 1
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- name: DMA2RST
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description: DMA1 reset
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bit_offset: 1
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bit_size: 1
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- name: FLASHRST
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description: FLITF reset
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bit_offset: 8
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bit_size: 1
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- name: CRCRST
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description: CRC reset
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bit_offset: 12
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bit_size: 1
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- name: AESRST
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description: AES hardware accelerator reset
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bit_offset: 16
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bit_size: 1
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- name: RNGRST
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description: Random number generator reset
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bit_offset: 18
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bit_size: 1
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fieldset/AHBSMENR:
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description: AHB peripheral clock enable in Sleep mode register
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fields:
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- name: DMA1SMEN
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description: DMA1 clock enable during Sleep mode
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bit_offset: 0
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bit_size: 1
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- name: DMASMEN
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description: DMA clock enable during Sleep mode
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bit_offset: 0
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bit_size: 1
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- name: DMA2SMEN
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description: DMA2 clock enable during Sleep mode
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bit_offset: 1
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bit_size: 1
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- name: FLASHSMEN
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description: Flash memory interface clock enable during Sleep mode
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bit_offset: 8
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bit_size: 1
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- name: SRAMSMEN
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description: SRAM clock enable during Sleep mode
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bit_offset: 9
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bit_size: 1
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- name: CRCSMEN
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description: CRC clock enable during Sleep mode
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bit_offset: 12
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bit_size: 1
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- name: AESSMEN
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description: AES hardware accelerator clock enable during Sleep mode
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bit_offset: 16
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bit_size: 1
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- name: RNGSMEN
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description: Random number generator clock enable during Sleep mode
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bit_offset: 18
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bit_size: 1
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fieldset/APBENR1:
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description: APB peripheral clock enable register 1
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fields:
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- name: TIM2EN
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description: TIM2 timer clock enable
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bit_offset: 0
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bit_size: 1
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- name: TIM3EN
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description: TIM3 timer clock enable
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bit_offset: 1
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bit_size: 1
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- name: TIM4EN
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description: TIM4 timer clock enable
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bit_offset: 2
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bit_size: 1
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- name: TIM6EN
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description: TIM6 timer clock enable
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bit_offset: 4
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bit_size: 1
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- name: TIM7EN
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description: TIM7 timer clock enable
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bit_offset: 5
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bit_size: 1
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- name: LPUART2EN
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description: LPUART2 clock enable
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bit_offset: 7
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bit_size: 1
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- name: USART5EN
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description: USART5EN
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bit_offset: 8
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bit_size: 1
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- name: USART6EN
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description: USART6EN
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bit_offset: 9
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bit_size: 1
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- name: RTCAPBEN
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description: RTC APB clock enable
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bit_offset: 10
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bit_size: 1
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- name: WWDGEN
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description: WWDG clock enable
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bit_offset: 11
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bit_size: 1
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- name: FDCANEN
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description: USBEN
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bit_offset: 12
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bit_size: 1
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- name: USBEN
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description: USBEN
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bit_offset: 13
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bit_size: 1
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- name: SPI2EN
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description: SPI2 clock enable
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bit_offset: 14
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bit_size: 1
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- name: SPI3EN
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description: SPI3 clock enable
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bit_offset: 15
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bit_size: 1
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- name: CRSEN
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description: CRSEN
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bit_offset: 16
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bit_size: 1
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- name: USART2EN
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description: USART2 clock enable
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bit_offset: 17
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bit_size: 1
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- name: USART3EN
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description: USART3 clock enable
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bit_offset: 18
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bit_size: 1
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- name: USART4EN
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description: USART4 clock enable
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bit_offset: 19
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bit_size: 1
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- name: LPUART1EN
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description: LPUART1 clock enable
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bit_offset: 20
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bit_size: 1
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- name: I2C1EN
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description: I2C1 clock enable
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bit_offset: 21
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bit_size: 1
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- name: I2C2EN
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description: I2C2 clock enable
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bit_offset: 22
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bit_size: 1
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- name: I2C3EN
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description: I2C3 clock enable
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bit_offset: 23
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bit_size: 1
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- name: CECEN
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description: HDMI CEC clock enable
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bit_offset: 24
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bit_size: 1
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- name: UCPD1EN
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description: UCPD1 clock enable
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bit_offset: 25
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bit_size: 1
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- name: UCPD2EN
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description: UCPD2 clock enable
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bit_offset: 26
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bit_size: 1
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- name: DBGEN
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description: Debug support clock enable
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bit_offset: 27
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bit_size: 1
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- name: PWREN
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description: Power interface clock enable
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bit_offset: 28
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bit_size: 1
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- name: DAC1EN
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description: DAC1 interface clock enable
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bit_offset: 29
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bit_size: 1
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- name: LPTIM2EN
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description: LPTIM2 clock enable
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bit_offset: 30
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bit_size: 1
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- name: LPTIM1EN
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description: LPTIM1 clock enable
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bit_offset: 31
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bit_size: 1
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fieldset/APBENR2:
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description: APB peripheral clock enable register 2
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fields:
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- name: SYSCFGEN
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description: "SYSCFG, COMP and VREFBUF clock enable"
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bit_offset: 0
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bit_size: 1
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- name: TIM1EN
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description: TIM1 timer clock enable
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bit_offset: 11
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bit_size: 1
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- name: SPI1EN
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description: SPI1 clock enable
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bit_offset: 12
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bit_size: 1
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- name: USART1EN
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description: USART1 clock enable
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bit_offset: 14
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bit_size: 1
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- name: TIM14EN
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description: TIM14 timer clock enable
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bit_offset: 15
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bit_size: 1
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- name: TIM15EN
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description: TIM15 timer clock enable
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bit_offset: 16
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bit_size: 1
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- name: TIM16EN
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description: TIM16 timer clock enable
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bit_offset: 17
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bit_size: 1
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- name: TIM17EN
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description: TIM16 timer clock enable
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bit_offset: 18
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bit_size: 1
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- name: ADCEN
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description: ADC clock enable
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bit_offset: 20
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bit_size: 1
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fieldset/APBRSTR1:
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description: APB peripheral reset register 1
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fields:
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- name: TIM2RST
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description: TIM2 timer reset
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bit_offset: 0
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bit_size: 1
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- name: TIM3RST
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description: TIM3 timer reset
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bit_offset: 1
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bit_size: 1
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- name: TIM4RST
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description: TIM4 timer reset
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bit_offset: 2
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bit_size: 1
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- name: TIM6RST
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description: TIM6 timer reset
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bit_offset: 4
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bit_size: 1
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- name: TIM7RST
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description: TIM7 timer reset
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bit_offset: 5
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bit_size: 1
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- name: LPUART2RST
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description: LPUART2RST
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bit_offset: 7
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bit_size: 1
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- name: USART5RST
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description: USART5RST
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bit_offset: 8
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bit_size: 1
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- name: USART6RST
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description: USART6RST
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bit_offset: 9
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bit_size: 1
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- name: FDCANRST
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description: FDCANRST
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bit_offset: 12
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bit_size: 1
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- name: USBRST
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description: USBRST
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bit_offset: 13
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bit_size: 1
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- name: SPI2RST
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description: SPI2 reset
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bit_offset: 14
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bit_size: 1
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- name: SPI3RST
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description: SPI3 reset
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bit_offset: 15
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bit_size: 1
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- name: CRSRST
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description: CRSRST
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bit_offset: 16
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bit_size: 1
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- name: USART2RST
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description: USART2 reset
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bit_offset: 17
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bit_size: 1
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- name: USART3RST
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description: USART3 reset
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bit_offset: 18
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bit_size: 1
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- name: USART4RST
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description: USART4 reset
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bit_offset: 19
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bit_size: 1
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- name: LPUART1RST
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description: LPUART1 reset
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bit_offset: 20
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bit_size: 1
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- name: I2C1RST
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description: I2C1 reset
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bit_offset: 21
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bit_size: 1
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- name: I2C2RST
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description: I2C2 reset
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bit_offset: 22
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bit_size: 1
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- name: I2C3RST
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description: I2C3RST reset
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bit_offset: 23
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bit_size: 1
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- name: CECRST
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description: HDMI CEC reset
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bit_offset: 24
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bit_size: 1
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- name: UCPD1RST
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description: UCPD1 reset
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bit_offset: 25
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bit_size: 1
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- name: UCPD2RST
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description: UCPD2 reset
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bit_offset: 26
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bit_size: 1
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- name: DBGRST
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description: Debug support reset
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bit_offset: 27
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bit_size: 1
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- name: PWRRST
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description: Power interface reset
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bit_offset: 28
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bit_size: 1
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- name: DAC1RST
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description: DAC1 interface reset
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bit_offset: 29
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bit_size: 1
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- name: LPTIM2RST
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description: Low Power Timer 2 reset
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bit_offset: 30
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bit_size: 1
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- name: LPTIM1RST
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description: Low Power Timer 1 reset
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bit_offset: 31
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bit_size: 1
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fieldset/APBRSTR2:
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description: APB peripheral reset register 2
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fields:
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- name: SYSCFGRST
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description: "SYSCFG, COMP and VREFBUF reset"
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bit_offset: 0
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bit_size: 1
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- name: TIM1RST
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description: TIM1 timer reset
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bit_offset: 11
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bit_size: 1
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- name: SPI1RST
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description: SPI1 reset
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bit_offset: 12
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bit_size: 1
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- name: USART1RST
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description: USART1 reset
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bit_offset: 14
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bit_size: 1
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- name: TIM14RST
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description: TIM14 timer reset
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bit_offset: 15
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bit_size: 1
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- name: TIM15RST
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description: TIM15 timer reset
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bit_offset: 16
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bit_size: 1
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- name: TIM16RST
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description: TIM16 timer reset
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bit_offset: 17
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bit_size: 1
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- name: TIM17RST
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description: TIM17 timer reset
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bit_offset: 18
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bit_size: 1
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- name: ADCRST
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description: ADC reset
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bit_offset: 20
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bit_size: 1
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fieldset/APBSMENR1:
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description: APB peripheral clock enable in Sleep mode register 1
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fields:
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- name: TIM2SMEN
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description: TIM2 timer clock enable during Sleep mode
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bit_offset: 0
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bit_size: 1
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- name: TIM3SMEN
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description: TIM3 timer clock enable during Sleep mode
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bit_offset: 1
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bit_size: 1
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- name: TIM4SMEN
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description: TIM4 timer clock enable during Sleep mode
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bit_offset: 2
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bit_size: 1
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- name: TIM6SMEN
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description: TIM6 timer clock enable during Sleep mode
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bit_offset: 4
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bit_size: 1
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- name: TIM7SMEN
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description: TIM7 timer clock enable during Sleep mode
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bit_offset: 5
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bit_size: 1
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- name: LPUART2SMEN
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description: LPUART2 clock enable
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bit_offset: 7
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bit_size: 1
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- name: USART5SMEN
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description: USART5 clock enable
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bit_offset: 8
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bit_size: 1
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- name: USART6SMEN
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description: USART6 clock enable
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bit_offset: 9
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bit_size: 1
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- name: RTCAPBSMEN
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description: RTC APB clock enable during Sleep mode
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bit_offset: 10
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bit_size: 1
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- name: WWDGSMEN
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description: WWDG clock enable during Sleep mode
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bit_offset: 11
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bit_size: 1
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- name: FDCANSMEN
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description: FDCAN clock enable during Sleep mode
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bit_offset: 12
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bit_size: 1
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- name: USBSMEN
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description: USB clock enable during Sleep mode
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bit_offset: 13
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bit_size: 1
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- name: SPI2SMEN
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description: SPI2 clock enable during Sleep mode
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bit_offset: 14
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bit_size: 1
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- name: SPI3SMEN
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description: SPI3 clock enable during Sleep mode
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bit_offset: 15
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bit_size: 1
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- name: CRSSSMEN
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description: CRSS clock enable during Sleep mode
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bit_offset: 16
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bit_size: 1
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- name: USART2SMEN
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|
description: USART2 clock enable during Sleep mode
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: USART3SMEN
|
|
description: USART3 clock enable during Sleep mode
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: USART4SMEN
|
|
description: USART4 clock enable during Sleep mode
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: LPUART1SMEN
|
|
description: LPUART1 clock enable during Sleep mode
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: I2C1SMEN
|
|
description: I2C1 clock enable during Sleep mode
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: I2C2SMEN
|
|
description: I2C2 clock enable during Sleep mode
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: I2C3SMEN
|
|
description: I2C3 clock enable during Sleep mode
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: CECSMEN
|
|
description: HDMI CEC clock enable during Sleep mode
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: UCPD1SMEN
|
|
description: UCPD1 clock enable during Sleep mode
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: UCPD2SMEN
|
|
description: UCPD2 clock enable during Sleep mode
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: DBGSMEN
|
|
description: Debug support clock enable during Sleep mode
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: PWRSMEN
|
|
description: Power interface clock enable during Sleep mode
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: DAC1SMEN
|
|
description: DAC1 interface clock enable during Sleep mode
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: LPTIM2SMEN
|
|
description: Low Power Timer 2 clock enable during Sleep mode
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: LPTIM1SMEN
|
|
description: Low Power Timer 1 clock enable during Sleep mode
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/APBSMENR2:
|
|
description: APB peripheral clock enable in Sleep mode register 2
|
|
fields:
|
|
- name: SYSCFGSMEN
|
|
description: "SYSCFG, COMP and VREFBUF clock enable during Sleep mode"
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: TIM1SMEN
|
|
description: TIM1 timer clock enable during Sleep mode
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI1SMEN
|
|
description: SPI1 clock enable during Sleep mode
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: USART1SMEN
|
|
description: USART1 clock enable during Sleep mode
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TIM14SMEN
|
|
description: TIM14 timer clock enable during Sleep mode
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: TIM15SMEN
|
|
description: TIM15 timer clock enable during Sleep mode
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: TIM16SMEN
|
|
description: TIM16 timer clock enable during Sleep mode
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM17SMEN
|
|
description: TIM16 timer clock enable during Sleep mode
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: ADCSMEN
|
|
description: ADC clock enable during Sleep mode
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
fieldset/BDCR:
|
|
description: RTC domain control register
|
|
fields:
|
|
- name: LSEON
|
|
description: LSE oscillator enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDY
|
|
description: LSE oscillator ready
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: LSEBYP
|
|
description: LSE oscillator bypass
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: LSEDRV
|
|
description: LSE oscillator drive capability
|
|
bit_offset: 3
|
|
bit_size: 2
|
|
- name: LSECSSON
|
|
description: CSS on LSE enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: LSECSSD
|
|
description: CSS on LSE failure Detection
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: RTCSEL
|
|
description: RTC clock source selection
|
|
bit_offset: 8
|
|
bit_size: 2
|
|
- name: RTCEN
|
|
description: RTC clock enable
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: BDRST
|
|
description: RTC domain software reset
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: LSCOEN
|
|
description: Low-speed clock output (LSCO) enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: LSCOSEL
|
|
description: Low-speed clock output selection
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
fieldset/CCIPR:
|
|
description: Peripherals independent clock configuration register
|
|
fields:
|
|
- name: USART1SEL
|
|
description: USART1 clock source selection
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: USART2SEL
|
|
description: USART2 clock source selection
|
|
bit_offset: 2
|
|
bit_size: 2
|
|
- name: USART3SEL
|
|
description: USART3 clock source selection
|
|
bit_offset: 4
|
|
bit_size: 2
|
|
- name: CECSEL
|
|
description: HDMI CEC clock source selection
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: LPUART2SEL
|
|
description: LPUART2 clock source selection
|
|
bit_offset: 8
|
|
bit_size: 2
|
|
- name: LPUART1SEL
|
|
description: LPUART1 clock source selection
|
|
bit_offset: 10
|
|
bit_size: 2
|
|
- name: I2C1SEL
|
|
description: I2C1 clock source selection
|
|
bit_offset: 12
|
|
bit_size: 2
|
|
- name: I2S2SEL
|
|
description: I2S1 clock source selection
|
|
bit_offset: 14
|
|
bit_size: 2
|
|
- name: LPTIM1SEL
|
|
description: LPTIM1 clock source selection
|
|
bit_offset: 18
|
|
bit_size: 2
|
|
- name: LPTIM2SEL
|
|
description: LPTIM2 clock source selection
|
|
bit_offset: 20
|
|
bit_size: 2
|
|
- name: TIM1SEL
|
|
description: TIM1 clock source selection
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: TIM15SEL
|
|
description: TIM15 clock source selection
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: RNGSEL
|
|
description: RNG clock source selection
|
|
bit_offset: 26
|
|
bit_size: 2
|
|
- name: RNGDIV
|
|
description: Division factor of RNG clock divider
|
|
bit_offset: 28
|
|
bit_size: 2
|
|
- name: ADCSEL
|
|
description: ADCs clock source selection
|
|
bit_offset: 30
|
|
bit_size: 2
|
|
fieldset/CCIPR2:
|
|
description: Peripherals independent clock configuration register 2
|
|
fields:
|
|
- name: I2S1SEL
|
|
description: 2S1SEL
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: I2S2SEL
|
|
description: I2S2SEL
|
|
bit_offset: 2
|
|
bit_size: 2
|
|
- name: FDCANSEL
|
|
description: FDCANSEL
|
|
bit_offset: 8
|
|
bit_size: 2
|
|
- name: USBSEL
|
|
description: USBSEL
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
fieldset/CFGR:
|
|
description: Clock configuration register
|
|
fields:
|
|
- name: SW
|
|
description: System clock switch
|
|
bit_offset: 0
|
|
bit_size: 3
|
|
- name: SWS
|
|
description: System clock switch status
|
|
bit_offset: 3
|
|
bit_size: 3
|
|
- name: HPRE
|
|
description: AHB prescaler
|
|
bit_offset: 8
|
|
bit_size: 4
|
|
- name: PPRE
|
|
description: APB prescaler
|
|
bit_offset: 12
|
|
bit_size: 3
|
|
- name: MCO2SEL
|
|
description: MCO2SEL
|
|
bit_offset: 16
|
|
bit_size: 4
|
|
- name: MCO2PRE
|
|
description: MCO2PRE
|
|
bit_offset: 20
|
|
bit_size: 4
|
|
- name: MCOSEL
|
|
description: Microcontroller clock output
|
|
bit_offset: 24
|
|
bit_size: 3
|
|
- name: MCOPRE
|
|
description: Microcontroller clock output prescaler
|
|
bit_offset: 28
|
|
bit_size: 3
|
|
fieldset/CICR:
|
|
description: Clock interrupt clear register
|
|
fields:
|
|
- name: LSIRDYC
|
|
description: LSI ready interrupt clear
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYC
|
|
description: LSE ready interrupt clear
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: HSI48RDYC
|
|
description: HSI48RDYC
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSIRDYC
|
|
description: HSI ready interrupt clear
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: HSERDYC
|
|
description: HSE ready interrupt clear
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: PLLSYSRDYC
|
|
description: PLL ready interrupt clear
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: CSSC
|
|
description: Clock security system interrupt clear
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LSECSSC
|
|
description: LSE Clock security system interrupt clear
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
fieldset/CIER:
|
|
description: Clock interrupt enable register
|
|
fields:
|
|
- name: LSIRDYIE
|
|
description: LSI ready interrupt enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYIE
|
|
description: LSE ready interrupt enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: HSIRDYIE
|
|
description: HSI ready interrupt enable
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: HSERDYIE
|
|
description: HSE ready interrupt enable
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: PLLSYSRDYIE
|
|
description: PLL ready interrupt enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
fieldset/CIFR:
|
|
description: Clock interrupt flag register
|
|
fields:
|
|
- name: LSIRDYF
|
|
description: LSI ready interrupt flag
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYF
|
|
description: LSE ready interrupt flag
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: HSI48RDYF
|
|
description: HSI48RDYF
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSIRDYF
|
|
description: HSI ready interrupt flag
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: HSERDYF
|
|
description: HSE ready interrupt flag
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: PLLSYSRDYF
|
|
description: PLL ready interrupt flag
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: CSSF
|
|
description: Clock security system interrupt flag
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LSECSSF
|
|
description: LSE Clock security system interrupt flag
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
fieldset/CR:
|
|
description: Clock control register
|
|
fields:
|
|
- name: HSION
|
|
description: HSI16 clock enable
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: HSIKERON
|
|
description: HSI16 always enable for peripheral kernels
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HSIRDY
|
|
description: HSI16 clock ready flag
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: HSIDIV
|
|
description: HSI16 clock division factor
|
|
bit_offset: 11
|
|
bit_size: 3
|
|
- name: HSEON
|
|
description: HSE clock enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: HSERDY
|
|
description: HSE clock ready flag
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: HSEBYP
|
|
description: HSE crystal oscillator bypass
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: CSSON
|
|
description: Clock security system enable
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: HSI48ON
|
|
description: HSI48ON
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: HSI48RDY
|
|
description: HSI48RDY
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: PLLON
|
|
description: PLL enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: PLLRDY
|
|
description: PLL clock ready flag
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
fieldset/CRRCR:
|
|
description: RCC clock recovery RC register
|
|
fields:
|
|
- name: HSI48CAL
|
|
description: HSI48 clock calibration
|
|
bit_offset: 0
|
|
bit_size: 9
|
|
fieldset/CSR:
|
|
description: Control/status register
|
|
fields:
|
|
- name: LSION
|
|
description: LSI oscillator enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSIRDY
|
|
description: LSI oscillator ready
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: RMVF
|
|
description: Remove reset flags
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: OBLRSTF
|
|
description: Option byte loader reset flag
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: PINRSTF
|
|
description: Pin reset flag
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: PWRRSTF
|
|
description: BOR or POR/PDR flag
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: SFTRSTF
|
|
description: Software reset flag
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: IWDGRSTF
|
|
description: Independent window watchdog reset flag
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: WWDGRSTF
|
|
description: Window watchdog reset flag
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: LPWRRSTF
|
|
description: Low-power reset flag
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/ICSCR:
|
|
description: Internal clock sources calibration register
|
|
fields:
|
|
- name: HSICAL
|
|
description: HSI16 clock calibration
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
- name: HSITRIM
|
|
description: HSI16 clock trimming
|
|
bit_offset: 8
|
|
bit_size: 7
|
|
fieldset/GPIOENR:
|
|
description: GPIO clock enable register
|
|
fields:
|
|
- name: GPIOAEN
|
|
description: I/O port A clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: GPIOBEN
|
|
description: I/O port B clock enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: GPIOCEN
|
|
description: I/O port C clock enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: GPIODEN
|
|
description: I/O port D clock enable
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: GPIOFEN
|
|
description: I/O port F clock enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
fieldset/GPIORSTR:
|
|
description: GPIO reset register
|
|
fields:
|
|
- name: GPIOARST
|
|
description: I/O port A reset
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: GPIOBRST
|
|
description: I/O port B reset
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: GPIOCRST
|
|
description: I/O port C reset
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: GPIODRST
|
|
description: I/O port D reset
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: GPIOFRST
|
|
description: I/O port F reset
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
fieldset/GPIOSMENR:
|
|
description: GPIO in Sleep mode clock enable register
|
|
fields:
|
|
- name: GPIOASMEN
|
|
description: I/O port A clock enable during Sleep mode
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: GPIOBSMEN
|
|
description: I/O port B clock enable during Sleep mode
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: GPIOCSMEN
|
|
description: I/O port C clock enable during Sleep mode
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: GPIODSMEN
|
|
description: I/O port D clock enable during Sleep mode
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: GPIOFSMEN
|
|
description: I/O port F clock enable during Sleep mode
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
fieldset/PLLSYSCFGR:
|
|
description: PLL configuration register
|
|
fields:
|
|
- name: PLLSRC
|
|
description: PLL input clock source
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: PLLM
|
|
description: Division factor M of the PLL input clock divider
|
|
bit_offset: 4
|
|
bit_size: 3
|
|
- name: PLLN
|
|
description: PLL frequency multiplication factor N
|
|
bit_offset: 8
|
|
bit_size: 7
|
|
- name: PLLPEN
|
|
description: PLLPCLK clock output enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: PLLP
|
|
description: PLL VCO division factor P for PLLPCLK clock output
|
|
bit_offset: 17
|
|
bit_size: 5
|
|
- name: PLLQEN
|
|
description: PLLQCLK clock output enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: PLLQ
|
|
description: PLL VCO division factor Q for PLLQCLK clock output
|
|
bit_offset: 25
|
|
bit_size: 3
|
|
- name: PLLREN
|
|
description: PLLRCLK clock output enable
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: PLLR
|
|
description: PLL VCO division factor R for PLLRCLK clock output
|
|
bit_offset: 29
|
|
bit_size: 3
|