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stm32-data/data/registers/rcc_l4.yaml
Matt Ickstadt 60d034f9fa RCC: unify LSEDRV enum variant names and descriptions 
Now the only differences are the series which have swapped medium low/high bits: F0, F3v2, F3, F7, and H7_RM0433.
2023-10-05 10:56:02 -05:00

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block/RCC:
description: Reset and clock control
items:
- name: CR
description: Clock control register
byte_offset: 0
fieldset: CR
- name: ICSCR
description: Internal clock sources calibration register
byte_offset: 4
fieldset: ICSCR
- name: CFGR
description: Clock configuration register
byte_offset: 8
fieldset: CFGR
- name: PLLCFGR
description: PLL configuration register
byte_offset: 12
fieldset: PLLCFGR
- name: PLLSAI1CFGR
description: PLLSAI1 configuration register
byte_offset: 16
fieldset: PLLSAI1CFGR
- name: PLLSAI2CFGR
description: PLLSAI2 configuration register
byte_offset: 20
fieldset: PLLSAI2CFGR
- name: CIER
description: Clock interrupt enable register
byte_offset: 24
fieldset: CIER
- name: CIFR
description: Clock interrupt flag register
byte_offset: 28
access: Read
fieldset: CIFR
- name: CICR
description: Clock interrupt clear register
byte_offset: 32
access: Write
fieldset: CICR
- name: AHB1RSTR
description: AHB1 peripheral reset register
byte_offset: 40
fieldset: AHB1RSTR
- name: AHB2RSTR
description: AHB2 peripheral reset register
byte_offset: 44
fieldset: AHB2RSTR
- name: AHB3RSTR
description: AHB3 peripheral reset register
byte_offset: 48
fieldset: AHB3RSTR
- name: APB1RSTR1
description: APB1 peripheral reset register 1
byte_offset: 56
fieldset: APB1RSTR1
- name: APB1RSTR2
description: APB1 peripheral reset register 2
byte_offset: 60
fieldset: APB1RSTR2
- name: APB2RSTR
description: APB2 peripheral reset register
byte_offset: 64
fieldset: APB2RSTR
- name: AHB1ENR
description: AHB1 peripheral clock enable register
byte_offset: 72
fieldset: AHB1ENR
- name: AHB2ENR
description: AHB2 peripheral clock enable register
byte_offset: 76
fieldset: AHB2ENR
- name: AHB3ENR
description: AHB3 peripheral clock enable register
byte_offset: 80
fieldset: AHB3ENR
- name: APB1ENR1
description: APB1ENR1
byte_offset: 88
fieldset: APB1ENR1
- name: APB1ENR2
description: APB1 peripheral clock enable register 2
byte_offset: 92
fieldset: APB1ENR2
- name: APB2ENR
description: APB2ENR
byte_offset: 96
fieldset: APB2ENR
- name: AHB1SMENR
description: AHB1 peripheral clocks enable in Sleep and Stop modes register
byte_offset: 104
fieldset: AHB1SMENR
- name: AHB2SMENR
description: AHB2 peripheral clocks enable in Sleep and Stop modes register
byte_offset: 108
fieldset: AHB2SMENR
- name: AHB3SMENR
description: AHB3 peripheral clocks enable in Sleep and Stop modes register
byte_offset: 112
fieldset: AHB3SMENR
- name: APB1SMENR1
description: APB1SMENR1
byte_offset: 120
fieldset: APB1SMENR1
- name: APB1SMENR2
description: APB1 peripheral clocks enable in Sleep and Stop modes register 2
byte_offset: 124
fieldset: APB1SMENR2
- name: APB2SMENR
description: APB2SMENR
byte_offset: 128
fieldset: APB2SMENR
- name: CCIPR
description: CCIPR
byte_offset: 136
fieldset: CCIPR
- name: BDCR
description: BDCR
byte_offset: 144
fieldset: BDCR
- name: CSR
description: CSR
byte_offset: 148
fieldset: CSR
- name: CRRCR
description: Clock recovery RC register
byte_offset: 152
fieldset: CRRCR
- name: CCIPR2
description: Peripherals independent clock configuration register
byte_offset: 156
fieldset: CCIPR2
fieldset/AHB1ENR:
description: AHB1 peripheral clock enable register
fields:
- name: DMA1EN
description: DMA1 clock enable
bit_offset: 0
bit_size: 1
- name: DMA2EN
description: DMA2 clock enable
bit_offset: 1
bit_size: 1
- name: DMAMUX1EN
description: DMAMUX clock enable
bit_offset: 2
bit_size: 1
- name: FLASHEN
description: Flash memory interface clock enable
bit_offset: 8
bit_size: 1
- name: CRCEN
description: CRC clock enable
bit_offset: 12
bit_size: 1
- name: TSCEN
description: Touch Sensing Controller clock enable
bit_offset: 16
bit_size: 1
- name: DMA2DEN
description: DMA2D clock enable
bit_offset: 17
bit_size: 1
- name: GFXMMUEN
description: Graphic MMU clock enable
bit_offset: 18
bit_size: 1
fieldset/AHB1RSTR:
description: AHB1 peripheral reset register
fields:
- name: DMA1RST
description: DMA1 reset
bit_offset: 0
bit_size: 1
- name: DMA2RST
description: DMA2 reset
bit_offset: 1
bit_size: 1
- name: DMAMUX1RST
description: DMAMUX1RST
bit_offset: 2
bit_size: 1
- name: FLASHRST
description: Flash memory interface reset
bit_offset: 8
bit_size: 1
- name: CRCRST
description: CRC reset
bit_offset: 12
bit_size: 1
- name: TSCRST
description: Touch Sensing Controller reset
bit_offset: 16
bit_size: 1
- name: DMA2DRST
description: DMA2D reset
bit_offset: 17
bit_size: 1
- name: GFXMMURST
description: GFXMMU reset
bit_offset: 18
bit_size: 1
fieldset/AHB1SMENR:
description: AHB1 peripheral clocks enable in Sleep and Stop modes register
fields:
- name: DMA1SMEN
description: DMA1 clocks enable during Sleep and Stop modes
bit_offset: 0
bit_size: 1
- name: DMA2SMEN
description: DMA2 clocks enable during Sleep and Stop modes
bit_offset: 1
bit_size: 1
- name: DMAMUX1SMEN
description: DMAMUX clock enable during Sleep and Stop modes
bit_offset: 2
bit_size: 1
- name: FLASHSMEN
description: Flash memory interface clocks enable during Sleep and Stop modes
bit_offset: 8
bit_size: 1
- name: SRAM1SMEN
description: SRAM1 interface clocks enable during Sleep and Stop modes
bit_offset: 9
bit_size: 1
- name: CRCSMEN
description: CRCSMEN
bit_offset: 12
bit_size: 1
- name: TSCSMEN
description: Touch Sensing Controller clocks enable during Sleep and Stop modes
bit_offset: 16
bit_size: 1
- name: DMA2DSMEN
description: DMA2D clock enable during Sleep and Stop modes
bit_offset: 17
bit_size: 1
- name: GFXMMUSMEN
description: GFXMMU clock enable during Sleep and Stop modes
bit_offset: 18
bit_size: 1
fieldset/AHB2ENR:
description: AHB2 peripheral clock enable register
fields:
- name: GPIOAEN
description: IO port A clock enable
bit_offset: 0
bit_size: 1
- name: GPIOBEN
description: IO port B clock enable
bit_offset: 1
bit_size: 1
- name: GPIOCEN
description: IO port C clock enable
bit_offset: 2
bit_size: 1
- name: GPIODEN
description: IO port D clock enable
bit_offset: 3
bit_size: 1
- name: GPIOEEN
description: IO port E clock enable
bit_offset: 4
bit_size: 1
- name: GPIOFEN
description: IO port F clock enable
bit_offset: 5
bit_size: 1
- name: GPIOGEN
description: IO port G clock enable
bit_offset: 6
bit_size: 1
- name: GPIOHEN
description: IO port H clock enable
bit_offset: 7
bit_size: 1
- name: GPIOIEN
description: IO port I clock enable
bit_offset: 8
bit_size: 1
- name: USB_OTG_FSEN
description: OTG full speed clock enable
bit_offset: 12
bit_size: 1
- name: ADCEN
description: ADC clock enable
bit_offset: 13
bit_size: 1
- name: DCMIEN
description: DCMI clock enable
bit_offset: 14
bit_size: 1
- name: AESEN
description: AES accelerator clock enable
bit_offset: 16
bit_size: 1
- name: HASHEN
description: HASH clock enable
bit_offset: 17
bit_size: 1
- name: RNGEN
description: Random Number Generator clock enable
bit_offset: 18
bit_size: 1
- name: OSPIMEN
description: OctoSPI IO manager clock enable
bit_offset: 20
bit_size: 1
- name: SDMMC1EN
description: SDMMC1 clock enable
bit_offset: 22
bit_size: 1
fieldset/AHB2RSTR:
description: AHB2 peripheral reset register
fields:
- name: GPIOARST
description: IO port A reset
bit_offset: 0
bit_size: 1
- name: GPIOBRST
description: IO port B reset
bit_offset: 1
bit_size: 1
- name: GPIOCRST
description: IO port C reset
bit_offset: 2
bit_size: 1
- name: GPIODRST
description: IO port D reset
bit_offset: 3
bit_size: 1
- name: GPIOERST
description: IO port E reset
bit_offset: 4
bit_size: 1
- name: GPIOFRST
description: IO port F reset
bit_offset: 5
bit_size: 1
- name: GPIOGRST
description: IO port G reset
bit_offset: 6
bit_size: 1
- name: GPIOHRST
description: IO port H reset
bit_offset: 7
bit_size: 1
- name: GPIOIRST
description: IO port I reset
bit_offset: 8
bit_size: 1
- name: USB_OTG_FSRST
description: USB OTG FS reset
bit_offset: 12
bit_size: 1
- name: ADCRST
description: ADC reset
bit_offset: 13
bit_size: 1
- name: DCMIRST
description: Digital Camera Interface reset
bit_offset: 14
bit_size: 1
- name: AESRST
description: AES hardware accelerator reset
bit_offset: 16
bit_size: 1
- name: HASHRST
description: Hash reset
bit_offset: 17
bit_size: 1
- name: RNGRST
description: Random number generator reset
bit_offset: 18
bit_size: 1
- name: OSPIMRST
description: OCTOSPI IO manager reset
bit_offset: 20
bit_size: 1
- name: SDMMC1RST
description: SDMMC1 reset
bit_offset: 22
bit_size: 1
fieldset/AHB2SMENR:
description: AHB2 peripheral clocks enable in Sleep and Stop modes register
fields:
- name: GPIOASMEN
description: IO port A clocks enable during Sleep and Stop modes
bit_offset: 0
bit_size: 1
- name: GPIOBSMEN
description: IO port B clocks enable during Sleep and Stop modes
bit_offset: 1
bit_size: 1
- name: GPIOCSMEN
description: IO port C clocks enable during Sleep and Stop modes
bit_offset: 2
bit_size: 1
- name: GPIODSMEN
description: IO port D clocks enable during Sleep and Stop modes
bit_offset: 3
bit_size: 1
- name: GPIOESMEN
description: IO port E clocks enable during Sleep and Stop modes
bit_offset: 4
bit_size: 1
- name: GPIOFSMEN
description: IO port F clocks enable during Sleep and Stop modes
bit_offset: 5
bit_size: 1
- name: GPIOGSMEN
description: IO port G clocks enable during Sleep and Stop modes
bit_offset: 6
bit_size: 1
- name: GPIOHSMEN
description: IO port H clocks enable during Sleep and Stop modes
bit_offset: 7
bit_size: 1
- name: GPIOISMEN
description: IO port I clocks enable during Sleep and Stop modes
bit_offset: 8
bit_size: 1
- name: SRAM2SMEN
description: SRAM2 interface clocks enable during Sleep and Stop modes
bit_offset: 9
bit_size: 1
- name: SRAM3SMEN
description: SRAM2 interface clocks enable during Sleep and Stop modes
bit_offset: 10
bit_size: 1
- name: USB_OTG_FSSMEN
description: OTG full speed clocks enable during Sleep and Stop modes
bit_offset: 12
bit_size: 1
- name: ADCFSSMEN
description: ADC clocks enable during Sleep and Stop modes
bit_offset: 13
bit_size: 1
- name: DCMISMEN
description: DCMI clock enable during Sleep and Stop modes
bit_offset: 14
bit_size: 1
- name: AESSMEN
description: AES accelerator clocks enable during Sleep and Stop modes
bit_offset: 16
bit_size: 1
- name: HASH1SMEN
description: HASH clock enable during Sleep and Stop modes
bit_offset: 17
bit_size: 1
- name: HASHSMEN
description: HASH clock enable during Sleep and Stop modes
bit_offset: 17
bit_size: 1
- name: RNGSMEN
description: Random Number Generator clocks enable during Sleep and Stop modes
bit_offset: 18
bit_size: 1
- name: OSPIMSMEN
description: OctoSPI IO manager clocks enable during Sleep and Stop modes
bit_offset: 20
bit_size: 1
- name: SDMMC1SMEN
description: SDMMC1 clocks enable during Sleep and Stop modes
bit_offset: 22
bit_size: 1
fieldset/AHB3ENR:
description: AHB3 peripheral clock enable register
fields:
- name: FMCEN
description: Flexible memory controller clock enable
bit_offset: 0
bit_size: 1
- name: QUADSPIEN
description: QUADSPIEN
bit_offset: 8
bit_size: 1
- name: OSPI2EN
description: OSPI2EN memory interface clock enable
bit_offset: 9
bit_size: 1
fieldset/AHB3RSTR:
description: AHB3 peripheral reset register
fields:
- name: FMCRST
description: Flexible memory controller reset
bit_offset: 0
bit_size: 1
- name: QSPIRST
description: Quad SPI memory interface reset
bit_offset: 8
bit_size: 1
- name: OSPI2RST
description: OctOSPI2 memory interface reset
bit_offset: 9
bit_size: 1
fieldset/AHB3SMENR:
description: AHB3 peripheral clocks enable in Sleep and Stop modes register
fields:
- name: FMCSMEN
description: Flexible memory controller clocks enable during Sleep and Stop modes
bit_offset: 0
bit_size: 1
- name: QSPISMEN
description: QSPISMEN
bit_offset: 8
bit_size: 1
- name: OCTOSPI2
description: OctoSPI2 memory interface clocks enable during Sleep and Stop modes
bit_offset: 9
bit_size: 1
fieldset/APB1ENR1:
description: APB1ENR1
fields:
- name: TIM2EN
description: TIM2 timer clock enable
bit_offset: 0
bit_size: 1
- name: TIM3EN
description: TIM3 timer clock enable
bit_offset: 1
bit_size: 1
- name: TIM4EN
description: TIM4 timer clock enable
bit_offset: 2
bit_size: 1
- name: TIM5EN
description: TIM5 timer clock enable
bit_offset: 3
bit_size: 1
- name: TIM6EN
description: TIM6 timer clock enable
bit_offset: 4
bit_size: 1
- name: TIM7EN
description: TIM7 timer clock enable
bit_offset: 5
bit_size: 1
- name: LCDEN
description: LCD clock enable
bit_offset: 9
bit_size: 1
- name: RTCAPBEN
description: RTC APB clock enable
bit_offset: 10
bit_size: 1
- name: WWDGEN
description: Window watchdog clock enable
bit_offset: 11
bit_size: 1
- name: SPI2EN
description: SPI2 clock enable
bit_offset: 14
bit_size: 1
- name: SPI3EN
description: SPI3 clock enable
bit_offset: 15
bit_size: 1
- name: USART2EN
description: USART2 clock enable
bit_offset: 17
bit_size: 1
- name: USART3EN
description: USART3 clock enable
bit_offset: 18
bit_size: 1
- name: UART4EN
description: UART4 clock enable
bit_offset: 19
bit_size: 1
- name: UART5EN
description: UART5 clock enable
bit_offset: 20
bit_size: 1
- name: I2C1EN
description: I2C1 clock enable
bit_offset: 21
bit_size: 1
- name: I2C2EN
description: I2C2 clock enable
bit_offset: 22
bit_size: 1
- name: I2C3EN
description: I2C3 clock enable
bit_offset: 23
bit_size: 1
- name: CRSEN
description: Clock Recovery System clock enable
bit_offset: 24
bit_size: 1
- name: CAN1EN
description: CAN1 clock enable
bit_offset: 25
bit_size: 1
- name: CAN2EN
description: CAN2 clock enable
bit_offset: 26
bit_size: 1
- name: USBEN
description: USB FS clock enable
bit_offset: 26
bit_size: 1
- name: PWREN
description: Power interface clock enable
bit_offset: 28
bit_size: 1
- name: DAC1EN
description: DAC1 interface clock enable
bit_offset: 29
bit_size: 1
- name: OPAMPEN
description: OPAMP interface clock enable
bit_offset: 30
bit_size: 1
- name: LPTIM1EN
description: Low power timer 1 clock enable
bit_offset: 31
bit_size: 1
fieldset/APB1ENR2:
description: APB1 peripheral clock enable register 2
fields:
- name: LPUART1EN
description: Low power UART 1 clock enable
bit_offset: 0
bit_size: 1
- name: I2C4EN
description: I2C4 clock enable
bit_offset: 1
bit_size: 1
- name: SWPMI1EN
description: Single wire protocol clock enable
bit_offset: 2
bit_size: 1
- name: LPTIM2EN
description: LPTIM2EN
bit_offset: 5
bit_size: 1
- name: DFSDMEN
description: DFSDMEN enable
bit_offset: 24
bit_size: 1
fieldset/APB1RSTR1:
description: APB1 peripheral reset register 1
fields:
- name: TIM2RST
description: TIM2 timer reset
bit_offset: 0
bit_size: 1
- name: TIM3RST
description: TIM3 timer reset
bit_offset: 1
bit_size: 1
- name: TIM4RST
description: TIM3 timer reset
bit_offset: 2
bit_size: 1
- name: TIM5RST
description: TIM5 timer reset
bit_offset: 3
bit_size: 1
- name: TIM6RST
description: TIM6 timer reset
bit_offset: 4
bit_size: 1
- name: TIM7RST
description: TIM7 timer reset
bit_offset: 5
bit_size: 1
- name: LCDRST
description: LCD interface reset
bit_offset: 9
bit_size: 1
- name: SPI2RST
description: SPI2 reset
bit_offset: 14
bit_size: 1
- name: SPI3RST
description: SPI3 reset
bit_offset: 15
bit_size: 1
- name: USART2RST
description: USART2 reset
bit_offset: 17
bit_size: 1
- name: USART3RST
description: USART3 reset
bit_offset: 18
bit_size: 1
- name: UART4RST
description: UART4 reset
bit_offset: 19
bit_size: 1
- name: UART5RST
description: UART5 reset
bit_offset: 20
bit_size: 1
- name: I2C1RST
description: I2C1 reset
bit_offset: 21
bit_size: 1
- name: I2C2RST
description: I2C2 reset
bit_offset: 22
bit_size: 1
- name: I2C3RST
description: I2C3 reset
bit_offset: 23
bit_size: 1
- name: CRSRST
description: CRS reset
bit_offset: 24
bit_size: 1
- name: CAN1RST
description: CAN1 reset
bit_offset: 25
bit_size: 1
- name: CAN2RST
description: CAN2 reset
bit_offset: 26
bit_size: 1
- name: USBRST
description: USB FS reset
bit_offset: 26
bit_size: 1
- name: PWRRST
description: Power interface reset
bit_offset: 28
bit_size: 1
- name: DAC1RST
description: DAC1 interface reset
bit_offset: 29
bit_size: 1
- name: OPAMPRST
description: OPAMP interface reset
bit_offset: 30
bit_size: 1
- name: LPTIM1RST
description: Low Power Timer 1 reset
bit_offset: 31
bit_size: 1
fieldset/APB1RSTR2:
description: APB1 peripheral reset register 2
fields:
- name: LPUART1RST
description: Low-power UART 1 reset
bit_offset: 0
bit_size: 1
- name: I2C4RST
description: I2C4 reset
bit_offset: 1
bit_size: 1
- name: SWPMI1RST
description: Single wire protocol reset
bit_offset: 2
bit_size: 1
- name: LPTIM2RST
description: Low-power timer 2 reset
bit_offset: 5
bit_size: 1
fieldset/APB1SMENR1:
description: APB1SMENR1
fields:
- name: TIM2SMEN
description: TIM2 timer clocks enable during Sleep and Stop modes
bit_offset: 0
bit_size: 1
- name: TIM3SMEN
description: TIM3 timer clocks enable during Sleep and Stop modes
bit_offset: 1
bit_size: 1
- name: TIM4SMEN
description: TIM4 timer clocks enable during Sleep and Stop modes
bit_offset: 2
bit_size: 1
- name: TIM5SMEN
description: TIM5 timer clocks enable during Sleep and Stop modes
bit_offset: 3
bit_size: 1
- name: TIM6SMEN
description: TIM6 timer clocks enable during Sleep and Stop modes
bit_offset: 4
bit_size: 1
- name: TIM7SMEN
description: TIM7 timer clocks enable during Sleep and Stop modes
bit_offset: 5
bit_size: 1
- name: LCDSMEN
description: LCD clocks enable during Sleep and Stop modes
bit_offset: 9
bit_size: 1
- name: RTCAPBSMEN
description: RTC APB clock enable during Sleep and Stop modes
bit_offset: 10
bit_size: 1
- name: WWDGSMEN
description: Window watchdog clocks enable during Sleep and Stop modes
bit_offset: 11
bit_size: 1
- name: SPI2SMEN
description: SPI2 clocks enable during Sleep and Stop modes
bit_offset: 14
bit_size: 1
- name: SP3SMEN
description: SPI3 clocks enable during Sleep and Stop modes
bit_offset: 15
bit_size: 1
- name: USART2SMEN
description: USART2 clocks enable during Sleep and Stop modes
bit_offset: 17
bit_size: 1
- name: USART3SMEN
description: USART3 clocks enable during Sleep and Stop modes
bit_offset: 18
bit_size: 1
- name: UART4SMEN
description: UART4 clocks enable during Sleep and Stop modes
bit_offset: 19
bit_size: 1
- name: UART5SMEN
description: UART5 clocks enable during Sleep and Stop modes
bit_offset: 20
bit_size: 1
- name: I2C1SMEN
description: I2C1 clocks enable during Sleep and Stop modes
bit_offset: 21
bit_size: 1
- name: I2C2SMEN
description: I2C2 clocks enable during Sleep and Stop modes
bit_offset: 22
bit_size: 1
- name: I2C3SMEN
description: I2C3 clocks enable during Sleep and Stop modes
bit_offset: 23
bit_size: 1
- name: CRSSMEN
description: CRS clock enable during Sleep and Stop modes
bit_offset: 24
bit_size: 1
- name: CAN1SMEN
description: CAN1 clocks enable during Sleep and Stop modes
bit_offset: 25
bit_size: 1
- name: CAN2SMEN
description: CAN2 clocks enable during Sleep and Stop modes
bit_offset: 26
bit_size: 1
- name: USBSMEN
description: USB FS clock enable during Sleep and Stop modes
bit_offset: 26
bit_size: 1
- name: PWRSMEN
description: Power interface clocks enable during Sleep and Stop modes
bit_offset: 28
bit_size: 1
- name: DAC1SMEN
description: DAC1 interface clocks enable during Sleep and Stop modes
bit_offset: 29
bit_size: 1
- name: OPAMPSMEN
description: OPAMP interface clocks enable during Sleep and Stop modes
bit_offset: 30
bit_size: 1
- name: LPTIM1SMEN
description: Low power timer 1 clocks enable during Sleep and Stop modes
bit_offset: 31
bit_size: 1
fieldset/APB1SMENR2:
description: APB1 peripheral clocks enable in Sleep and Stop modes register 2
fields:
- name: LPUART1SMEN
description: Low power UART 1 clocks enable during Sleep and Stop modes
bit_offset: 0
bit_size: 1
- name: I2C4SMEN
description: I2C4 clocks enable during Sleep and Stop modes
bit_offset: 1
bit_size: 1
- name: SWPMI1SMEN
description: Single wire protocol clocks enable during Sleep and Stop modes
bit_offset: 2
bit_size: 1
- name: LPTIM2SMEN
description: LPTIM2SMEN
bit_offset: 5
bit_size: 1
fieldset/APB2ENR:
description: APB2ENR
fields:
- name: SYSCFGEN
description: SYSCFG clock enable
bit_offset: 0
bit_size: 1
- name: FWEN
description: Firewall clock enable
bit_offset: 7
bit_size: 1
- name: SDMMCEN
description: SDMMC clock enable
bit_offset: 10
bit_size: 1
- name: TIM1EN
description: TIM1 timer clock enable
bit_offset: 11
bit_size: 1
- name: SPI1EN
description: SPI1 clock enable
bit_offset: 12
bit_size: 1
- name: TIM8EN
description: TIM8 timer clock enable
bit_offset: 13
bit_size: 1
- name: USART1EN
description: USART1clock enable
bit_offset: 14
bit_size: 1
- name: TIM15EN
description: TIM15 timer clock enable
bit_offset: 16
bit_size: 1
- name: TIM16EN
description: TIM16 timer clock enable
bit_offset: 17
bit_size: 1
- name: TIM17EN
description: TIM17 timer clock enable
bit_offset: 18
bit_size: 1
- name: SAI1EN
description: SAI1 clock enable
bit_offset: 21
bit_size: 1
- name: SAI2EN
description: SAI2 clock enable
bit_offset: 22
bit_size: 1
- name: DFSDM1EN
description: DFSDM timer clock enable
bit_offset: 24
bit_size: 1
- name: DFSDMEN
description: DFSDM timer clock enable
bit_offset: 24
bit_size: 1
- name: LTDCEN
description: LCD-TFT clock enable
bit_offset: 26
bit_size: 1
- name: DSIEN
description: DSI clock enable
bit_offset: 27
bit_size: 1
fieldset/APB2RSTR:
description: APB2 peripheral reset register
fields:
- name: SYSCFGRST
description: System configuration (SYSCFG) reset
bit_offset: 0
bit_size: 1
- name: SDMMCRST
description: SDMMC reset
bit_offset: 10
bit_size: 1
- name: TIM1RST
description: TIM1 timer reset
bit_offset: 11
bit_size: 1
- name: SPI1RST
description: SPI1 reset
bit_offset: 12
bit_size: 1
- name: TIM8RST
description: TIM8 timer reset
bit_offset: 13
bit_size: 1
- name: USART1RST
description: USART1 reset
bit_offset: 14
bit_size: 1
- name: TIM15RST
description: TIM15 timer reset
bit_offset: 16
bit_size: 1
- name: TIM16RST
description: TIM16 timer reset
bit_offset: 17
bit_size: 1
- name: TIM17RST
description: TIM17 timer reset
bit_offset: 18
bit_size: 1
- name: SAI1RST
description: Serial audio interface 1 (SAI1) reset
bit_offset: 21
bit_size: 1
- name: SAI2RST
description: Serial audio interface 2 (SAI2) reset
bit_offset: 22
bit_size: 1
- name: DFSDM1RST
description: Digital filters for sigma-delata modulators (DFSDM) reset
bit_offset: 24
bit_size: 1
- name: DFSDMRST
description: DFSDM filter reset
bit_offset: 24
bit_size: 1
- name: LTDCRST
description: LCD-TFT reset
bit_offset: 26
bit_size: 1
- name: DSIRST
description: DSI reset
bit_offset: 27
bit_size: 1
fieldset/APB2SMENR:
description: APB2SMENR
fields:
- name: SYSCFGSMEN
description: SYSCFG clocks enable during Sleep and Stop modes
bit_offset: 0
bit_size: 1
- name: SDMMCSMEN
description: SDMMC clocks enable during Sleep and Stop modes
bit_offset: 10
bit_size: 1
- name: TIM1SMEN
description: TIM1 timer clocks enable during Sleep and Stop modes
bit_offset: 11
bit_size: 1
- name: SPI1SMEN
description: SPI1 clocks enable during Sleep and Stop modes
bit_offset: 12
bit_size: 1
- name: TIM8SMEN
description: TIM8 timer clocks enable during Sleep and Stop modes
bit_offset: 13
bit_size: 1
- name: USART1SMEN
description: USART1clocks enable during Sleep and Stop modes
bit_offset: 14
bit_size: 1
- name: TIM15SMEN
description: TIM15 timer clocks enable during Sleep and Stop modes
bit_offset: 16
bit_size: 1
- name: TIM16SMEN
description: TIM16 timer clocks enable during Sleep and Stop modes
bit_offset: 17
bit_size: 1
- name: TIM17SMEN
description: TIM17 timer clocks enable during Sleep and Stop modes
bit_offset: 18
bit_size: 1
- name: SAI1SMEN
description: SAI1 clocks enable during Sleep and Stop modes
bit_offset: 21
bit_size: 1
- name: SAI2SMEN
description: SAI2 clocks enable during Sleep and Stop modes
bit_offset: 22
bit_size: 1
- name: DFSDM1SMEN
description: DFSDM timer clocks enable during Sleep and Stop modes
bit_offset: 24
bit_size: 1
- name: DFSDMSMEN
description: DFSDM timer clocks enable during Sleep and Stop modes
bit_offset: 24
bit_size: 1
- name: LTDCSMEN
description: LCD-TFT timer clocks enable during Sleep and Stop modes
bit_offset: 26
bit_size: 1
- name: DSISMEN
description: DSI clocks enable during Sleep and Stop modes
bit_offset: 27
bit_size: 1
fieldset/BDCR:
description: BDCR
fields:
- name: LSEON
description: LSE oscillator enable
bit_offset: 0
bit_size: 1
- name: LSERDY
description: LSE oscillator ready
bit_offset: 1
bit_size: 1
- name: LSEBYP
description: LSE oscillator bypass
bit_offset: 2
bit_size: 1
- name: LSEDRV
description: SE oscillator drive capability
bit_offset: 3
bit_size: 2
enum: LSEDRV
- name: LSECSSON
description: LSECSSON
bit_offset: 5
bit_size: 1
- name: LSECSSD
description: LSECSSD
bit_offset: 6
bit_size: 1
- name: RTCSEL
description: RTC clock source selection
bit_offset: 8
bit_size: 2
enum: RTCSEL
- name: RTCEN
description: RTC clock enable
bit_offset: 15
bit_size: 1
- name: BDRST
description: Backup domain software reset
bit_offset: 16
bit_size: 1
- name: LSCOEN
description: Low speed clock output enable
bit_offset: 24
bit_size: 1
- name: LSCOSEL
description: Low speed clock output selection
bit_offset: 25
bit_size: 1
fieldset/CCIPR:
description: CCIPR
fields:
- name: USART1SEL
description: USART1 clock source selection
bit_offset: 0
bit_size: 2
- name: USART2SEL
description: USART2 clock source selection
bit_offset: 2
bit_size: 2
- name: USART3SEL
description: USART3 clock source selection
bit_offset: 4
bit_size: 2
- name: UART4SEL
description: UART4 clock source selection
bit_offset: 6
bit_size: 2
- name: UART5SEL
description: UART5 clock source selection
bit_offset: 8
bit_size: 2
- name: LPUART1SEL
description: LPUART1 clock source selection
bit_offset: 10
bit_size: 2
- name: I2C1SEL
description: I2C1 clock source selection
bit_offset: 12
bit_size: 2
- name: I2C2SEL
description: I2C2 clock source selection
bit_offset: 14
bit_size: 2
- name: I2C3SEL
description: I2C3 clock source selection
bit_offset: 16
bit_size: 2
- name: LPTIM1SEL
description: Low power timer 1 clock source selection
bit_offset: 18
bit_size: 2
- name: LPTIM2SEL
description: Low power timer 2 clock source selection
bit_offset: 20
bit_size: 2
- name: SAI1SEL
description: SAI1 clock source selection
bit_offset: 22
bit_size: 2
- name: SAI2SEL
description: SAI2 clock source selection
bit_offset: 24
bit_size: 2
- name: CLK48SEL
description: 48 MHz clock source selection
bit_offset: 26
bit_size: 2
- name: ADCSEL
description: ADCs clock source selection
bit_offset: 28
bit_size: 2
- name: SWPMI1SEL
description: SWPMI1 clock source selection
bit_offset: 30
bit_size: 1
- name: DFSDMSEL
description: DFSDM clock source selection
bit_offset: 31
bit_size: 1
fieldset/CCIPR2:
description: Peripherals independent clock configuration register
fields:
- name: I2C4SEL
description: I2C4 clock source selection
bit_offset: 0
bit_size: 2
- name: DFSDMSEL
description: Digital filter for sigma delta modulator kernel clock source selection
bit_offset: 2
bit_size: 1
- name: ADFSDMSEL
description: Digital filter for sigma delta modulator audio clock source selection
bit_offset: 3
bit_size: 2
- name: SAI1SEL
description: SAI1 clock source selection
bit_offset: 5
bit_size: 3
- name: SAI2SEL
description: SAI2 clock source selection
bit_offset: 8
bit_size: 3
- name: DSISEL
description: clock selection
bit_offset: 12
bit_size: 1
- name: SDMMCSEL
description: SDMMC clock selection
bit_offset: 14
bit_size: 1
- name: PLLSAI2DIVR
description: division factor for LTDC clock
bit_offset: 16
bit_size: 2
- name: OSPISEL
description: Octospi clock source selection
bit_offset: 20
bit_size: 2
fieldset/CFGR:
description: Clock configuration register
fields:
- name: SW
description: System clock switch
bit_offset: 0
bit_size: 2
enum: SW
- name: SWS
description: System clock switch status
bit_offset: 2
bit_size: 2
enum: SW
- name: HPRE
description: AHB prescaler
bit_offset: 4
bit_size: 4
enum: HPRE
- name: PPRE1
description: APB low-speed prescaler (APB1)
bit_offset: 8
bit_size: 3
enum: PPRE
- name: PPRE2
description: APB high-speed prescaler (APB2)
bit_offset: 11
bit_size: 3
enum: PPRE
- name: STOPWUCK
description: Wakeup from Stop and CSS backup clock selection
bit_offset: 15
bit_size: 1
enum: STOPWUCK
- name: MCOSEL
description: Microcontroller clock output selection
bit_offset: 24
bit_size: 4
enum: MCOSEL
- name: MCOPRE
description: Microcontroller clock output prescaler
bit_offset: 28
bit_size: 3
enum: MCOPRE
fieldset/CICR:
description: Clock interrupt clear register
fields:
- name: LSIRDYC
description: LSI ready interrupt clear
bit_offset: 0
bit_size: 1
- name: LSERDYC
description: LSE ready interrupt clear
bit_offset: 1
bit_size: 1
- name: MSIRDYC
description: MSI ready interrupt clear
bit_offset: 2
bit_size: 1
- name: HSIRDYC
description: HSI ready interrupt clear
bit_offset: 3
bit_size: 1
- name: HSERDYC
description: HSE ready interrupt clear
bit_offset: 4
bit_size: 1
- name: PLLRDYC
description: PLL ready interrupt clear
bit_offset: 5
bit_size: 1
- name: PLLSAI1RDYC
description: PLLSAI1 ready interrupt clear
bit_offset: 6
bit_size: 1
- name: PLLSAI2RDYC
description: PLLSAI2 ready interrupt clear
bit_offset: 7
bit_size: 1
- name: CSSC
description: Clock security system interrupt clear
bit_offset: 8
bit_size: 1
- name: LSECSSC
description: LSE Clock security system interrupt clear
bit_offset: 9
bit_size: 1
- name: HSI48RDYC
description: HSI48 oscillator ready interrupt clear
bit_offset: 10
bit_size: 1
fieldset/CIER:
description: Clock interrupt enable register
fields:
- name: LSIRDYIE
description: LSI ready interrupt enable
bit_offset: 0
bit_size: 1
- name: LSERDYIE
description: LSE ready interrupt enable
bit_offset: 1
bit_size: 1
- name: MSIRDYIE
description: MSI ready interrupt enable
bit_offset: 2
bit_size: 1
- name: HSIRDYIE
description: HSI ready interrupt enable
bit_offset: 3
bit_size: 1
- name: HSERDYIE
description: HSE ready interrupt enable
bit_offset: 4
bit_size: 1
- name: PLLRDYIE
description: PLL ready interrupt enable
bit_offset: 5
bit_size: 1
- name: PLLSAI1RDYIE
description: PLLSAI1 ready interrupt enable
bit_offset: 6
bit_size: 1
- name: PLLSAI2RDYIE
description: PLLSAI2 ready interrupt enable
bit_offset: 7
bit_size: 1
- name: LSECSSIE
description: LSE clock security system interrupt enable
bit_offset: 9
bit_size: 1
- name: HSI48RDYIE
description: HSI48 ready interrupt enable
bit_offset: 10
bit_size: 1
fieldset/CIFR:
description: Clock interrupt flag register
fields:
- name: LSIRDYF
description: LSI ready interrupt flag
bit_offset: 0
bit_size: 1
- name: LSERDYF
description: LSE ready interrupt flag
bit_offset: 1
bit_size: 1
- name: MSIRDYF
description: MSI ready interrupt flag
bit_offset: 2
bit_size: 1
- name: HSIRDYF
description: HSI ready interrupt flag
bit_offset: 3
bit_size: 1
- name: HSERDYF
description: HSE ready interrupt flag
bit_offset: 4
bit_size: 1
- name: PLLRDYF
description: PLL ready interrupt flag
bit_offset: 5
bit_size: 1
- name: PLLSAI1RDYF
description: PLLSAI1 ready interrupt flag
bit_offset: 6
bit_size: 1
- name: PLLSAI2RDYF
description: PLLSAI2 ready interrupt flag
bit_offset: 7
bit_size: 1
- name: CSSF
description: Clock security system interrupt flag
bit_offset: 8
bit_size: 1
- name: LSECSSF
description: LSE Clock security system interrupt flag
bit_offset: 9
bit_size: 1
- name: HSI48RDYF
description: HSI48 ready interrupt flag
bit_offset: 10
bit_size: 1
fieldset/CR:
description: Clock control register
fields:
- name: MSION
description: MSI clock enable
bit_offset: 0
bit_size: 1
- name: MSIRDY
description: MSI clock ready flag
bit_offset: 1
bit_size: 1
- name: MSIPLLEN
description: MSI clock PLL enable
bit_offset: 2
bit_size: 1
- name: MSIRGSEL
description: MSI clock range selection
bit_offset: 3
bit_size: 1
- name: MSIRANGE
description: MSI clock ranges
bit_offset: 4
bit_size: 4
enum: MSIRANGE
- name: HSION
description: HSI clock enable
bit_offset: 8
bit_size: 1
- name: HSIKERON
description: HSI always enable for peripheral kernels
bit_offset: 9
bit_size: 1
- name: HSIRDY
description: HSI clock ready flag
bit_offset: 10
bit_size: 1
- name: HSIASFS
description: HSI automatic start from Stop
bit_offset: 11
bit_size: 1
- name: HSEON
description: HSE clock enable
bit_offset: 16
bit_size: 1
- name: HSERDY
description: HSE clock ready flag
bit_offset: 17
bit_size: 1
- name: HSEBYP
description: HSE crystal oscillator bypass
bit_offset: 18
bit_size: 1
- name: CSSON
description: Clock security system enable
bit_offset: 19
bit_size: 1
- name: PLLON
description: Main PLL enable
bit_offset: 24
bit_size: 1
- name: PLLRDY
description: Main PLL clock ready flag
bit_offset: 25
bit_size: 1
- name: PLLSAI1ON
description: SAI1 PLL enable
bit_offset: 26
bit_size: 1
- name: PLLSAI1RDY
description: SAI1 PLL clock ready flag
bit_offset: 27
bit_size: 1
- name: PLLSAI2ON
description: SAI2 PLL enable
bit_offset: 28
bit_size: 1
- name: PLLSAI2RDY
description: SAI2 PLL clock ready flag
bit_offset: 29
bit_size: 1
fieldset/CRRCR:
description: Clock recovery RC register
fields:
- name: HSI48ON
description: HSI48 clock enable
bit_offset: 0
bit_size: 1
- name: HSI48RDY
description: HSI48 clock ready flag
bit_offset: 1
bit_size: 1
- name: HSI48CAL
description: HSI48 clock calibration
bit_offset: 7
bit_size: 9
fieldset/CSR:
description: CSR
fields:
- name: LSION
description: LSI oscillator enable
bit_offset: 0
bit_size: 1
- name: LSIRDY
description: LSI oscillator ready
bit_offset: 1
bit_size: 1
- name: MSISRANGE
description: SI range after Standby mode
bit_offset: 8
bit_size: 4
- name: RMVF
description: Remove reset flag
bit_offset: 23
bit_size: 1
- name: FWRSTF
description: Firewall reset flag
bit_offset: 24
bit_size: 1
- name: OBLRSTF
description: Option byte loader reset flag
bit_offset: 25
bit_size: 1
- name: PINRSTF
description: Pin reset flag
bit_offset: 26
bit_size: 1
- name: BORRSTF
description: BOR flag
bit_offset: 27
bit_size: 1
- name: SFTRSTF
description: Software reset flag
bit_offset: 28
bit_size: 1
- name: IWDGRSTF
description: Independent window watchdog reset flag
bit_offset: 29
bit_size: 1
- name: WWDGRSTF
description: Window watchdog reset flag
bit_offset: 30
bit_size: 1
- name: LPWRRSTF
description: Low-power reset flag
bit_offset: 31
bit_size: 1
fieldset/ICSCR:
description: Internal clock sources calibration register
fields:
- name: MSICAL
description: MSI clock calibration
bit_offset: 0
bit_size: 8
- name: MSITRIM
description: MSI clock trimming
bit_offset: 8
bit_size: 8
- name: HSICAL
description: HSI clock calibration
bit_offset: 16
bit_size: 8
- name: HSITRIM
description: HSI clock trimming
bit_offset: 24
bit_size: 7
fieldset/PLLCFGR:
description: PLL configuration register
fields:
- name: PLLSRC
description: Main PLL, PLLSAI1 and PLLSAI2 entry clock source
bit_offset: 0
bit_size: 2
enum: PLLSRC
- name: PLLM
description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
bit_offset: 4
bit_size: 4
- name: PLLN
description: Main PLL multiplication factor for VCO
bit_offset: 8
bit_size: 7
- name: PLLPEN
description: Main PLL PLLSAI3CLK output enable
bit_offset: 16
bit_size: 1
- name: PLLP
description: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)
bit_offset: 17
bit_size: 1
- name: PLLQEN
description: Main PLL PLLUSB1CLK output enable
bit_offset: 20
bit_size: 1
- name: PLLQ
description: Main PLL division factor for PLLUSB1CLK(48 MHz clock)
bit_offset: 21
bit_size: 2
- name: PLLREN
description: Main PLL PLLCLK output enable
bit_offset: 24
bit_size: 1
- name: PLLR
description: Main PLL division factor for PLLCLK (system clock)
bit_offset: 25
bit_size: 2
- name: PLLPDIV
description: Main PLL division factor for PLLSAI2CLK
bit_offset: 27
bit_size: 5
fieldset/PLLSAI1CFGR:
description: PLLSAI1 configuration register
fields:
- name: PLLSAI1M
description: Division factor for PLLSAI1 input clock
bit_offset: 4
bit_size: 4
- name: PLLSAI1N
description: SAI1PLL multiplication factor for VCO
bit_offset: 8
bit_size: 7
- name: PLLSAI1PEN
description: SAI1PLL PLLSAI1CLK output enable
bit_offset: 16
bit_size: 1
- name: PLLSAI1P
description: SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock)
bit_offset: 17
bit_size: 1
- name: PLLSAI1QEN
description: SAI1PLL PLLUSB2CLK output enable
bit_offset: 20
bit_size: 1
- name: PLLSAI1Q
description: SAI1PLL division factor for PLLUSB2CLK (48 MHz clock)
bit_offset: 21
bit_size: 2
- name: PLLSAI1REN
description: PLLSAI1 PLLADC1CLK output enable
bit_offset: 24
bit_size: 1
- name: PLLSAI1R
description: PLLSAI1 division factor for PLLADC1CLK (ADC clock)
bit_offset: 25
bit_size: 2
- name: PLLSAI1PDIV
description: PLLSAI1 division factor for PLLSAI1CLK
bit_offset: 27
bit_size: 5
fieldset/PLLSAI2CFGR:
description: PLLSAI2 configuration register
fields:
- name: PLLSAI2M
description: Division factor for PLLSAI2 input clock
bit_offset: 4
bit_size: 4
- name: PLLSAI2N
description: SAI2PLL multiplication factor for VCO
bit_offset: 8
bit_size: 7
- name: PLLSAI2PEN
description: SAI2PLL PLLSAI2CLK output enable
bit_offset: 16
bit_size: 1
- name: PLLSAI2P
description: SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock)
bit_offset: 17
bit_size: 1
- name: PLLSAI2QEN
description: PLLSAI2 division factor for PLLDISCLK
bit_offset: 20
bit_size: 1
- name: PLLSAI2Q
description: SAI2PLL PLLSAI2CLK output enable
bit_offset: 21
bit_size: 2
- name: PLLSAI2REN
description: PLLSAI2 PLLADC2CLK output enable
bit_offset: 24
bit_size: 1
- name: PLLSAI2R
description: PLLSAI2 division factor for PLLADC2CLK (ADC clock)
bit_offset: 25
bit_size: 2
- name: PLLSAI2PDIV
description: PLLSAI2 division factor for PLLSAI2CLK
bit_offset: 27
bit_size: 5
enum/HPRE:
bit_size: 4
variants:
- name: Div1
description: system clock not divided
value: 0
- name: Div2
description: system clock divided by 2
value: 8
- name: Div4
description: system clock divided by 4
value: 9
- name: Div8
description: system clock divided by 8
value: 10
- name: Div16
description: system clock divided by 16
value: 11
- name: Div64
description: system clock divided by 64
value: 12
- name: Div128
description: system clock divided by 128
value: 13
- name: Div256
description: system clock divided by 256
value: 14
- name: Div512
description: system clock divided by 512
value: 15
enum/LSEDRV:
bit_size: 2
variants:
- name: Low
description: Low driving capability
value: 0
- name: MediumLow
description: Medium low driving capability
value: 1
- name: MediumHigh
description: Medium high driving capability
value: 2
- name: High
description: High driving capability
value: 3
enum/MCOPRE:
bit_size: 3
variants:
- name: Div1
description: No division
value: 0
- name: Div2
description: Division by 2
value: 1
- name: Div4
description: Division by 4
value: 2
- name: Div8
description: Division by 8
value: 3
- name: Div16
description: Division by 16
value: 4
enum/MCOSEL:
bit_size: 4
variants:
- name: NoClock
description: No clock
value: 0
- name: SYSCLK
description: SYSCLK clock selected
value: 1
- name: MSI
description: MSI oscillator clock selected
value: 2
- name: HSI16
description: HSI oscillator clock selected
value: 3
- name: HSE
description: HSE oscillator clock selected
value: 4
- name: PLL
description: PLL clock selected
value: 5
- name: LSI
description: LSI oscillator clock selected
value: 6
- name: LSE
description: LSE oscillator clock selected
value: 7
- name: HSI48
description: HSI48 oscillator clock selected
value: 8
enum/MSIRANGE:
bit_size: 4
variants:
- name: Range100K
description: range 0 around 100 kHz
value: 0
- name: Range200K
description: range 1 around 200 kHz
value: 1
- name: Range400K
description: range 2 around 400 kHz
value: 2
- name: Range800K
description: range 3 around 800 kHz
value: 3
- name: Range1M
description: range 4 around 1 MHz
value: 4
- name: Range2M
description: range 5 around 2 MHz
value: 5
- name: Range4M
description: range 6 around 4 MHz
value: 6
- name: Range8M
description: range 7 around 8 MHz
value: 7
- name: Range16M
description: range 8 around 16 MHz
value: 8
- name: Range24M
description: range 9 around 24 MHz
value: 9
- name: Range32M
description: range 10 around 32 MHz
value: 10
- name: Range48M
description: range 11 around 48 MHz
value: 11
enum/PLLSRC:
bit_size: 2
variants:
- name: None
description: No clock sent to PLL
value: 0
- name: MSI
description: MSI selected as PLL input clock
value: 1
- name: HSI16
description: HSI selected as PLL input clock
value: 2
- name: HSE
description: HSE selected as PLL input clock
value: 3
enum/PPRE:
bit_size: 3
variants:
- name: Div1
description: HCLK not divided
value: 0
- name: Div2
description: HCLK divided by 2
value: 4
- name: Div4
description: HCLK divided by 4
value: 5
- name: Div8
description: HCLK divided by 8
value: 6
- name: Div16
description: HCLK divided by 16
value: 7
enum/RTCSEL:
bit_size: 2
variants:
- name: NoClock
description: No clock
value: 0
- name: LSE
description: LSE oscillator clock used as RTC clock
value: 1
- name: LSI
description: LSI oscillator clock used as RTC clock
value: 2
- name: HSE
description: HSE oscillator clock divided by 32 used as the RTC clock
value: 3
enum/STOPWUCK:
bit_size: 1
variants:
- name: MSI
description: MSI oscillator selected as wake-up from Stop clock
value: 0
- name: HSI16
description: HSI oscillator selected as wake-up from Stop clock
value: 1
enum/SW:
bit_size: 2
variants:
- name: MSI
description: MSI selected as system clock
value: 0
- name: HSI16
description: HSI selected as system clock
value: 1
- name: HSE
description: HSE selected as system clock
value: 2
- name: PLL
description: PLL selected as system clock
value: 3
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