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stm32-data/data/registers/rtc_h7.yaml
chemicstry 5ec0ad4387 Add RTC registers for all chips
2022-06-05 22:52:14 +02:00

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---
block/RTC:
description: RTC
items:
- name: TR
description: "The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page9 and Reading the calendar on page10.This register is write protected. The write access procedure is described in RTC register write protection on page9."
byte_offset: 0
fieldset: TR
- name: DR
description: "The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page9 and Reading the calendar on page10.This register is write protected. The write access procedure is described in RTC register write protection on page9."
byte_offset: 4
fieldset: DR
- name: CR
description: RTC control register
byte_offset: 8
fieldset: CR
- name: ISR
description: "This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure is described in RTC register write protection on page9."
byte_offset: 12
fieldset: ISR
- name: PRER
description: "This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page9.This register is write protected. The write access procedure is described in RTC register write protection on page9."
byte_offset: 16
fieldset: PRER
- name: WUTR
description: "This register can be written only when WUTWF is set to 1 in RTC_ISR.This register is write protected. The write access procedure is described in RTC register write protection on page9."
byte_offset: 20
fieldset: WUTR
- name: ALRMAR
description: "This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9."
byte_offset: 28
fieldset: ALRMAR
- name: ALRMBR
description: "This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9."
byte_offset: 32
fieldset: ALRMBR
- name: WPR
description: RTC write protection register
byte_offset: 36
access: Write
fieldset: WPR
- name: SSR
description: RTC sub second register
byte_offset: 40
access: Read
fieldset: SSR
- name: SHIFTR
description: "This register is write protected. The write access procedure is described in RTC register write protection on page9."
byte_offset: 44
access: Write
fieldset: SHIFTR
- name: TSTR
description: "The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset."
byte_offset: 48
access: Read
fieldset: TSTR
- name: TSDR
description: "The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset."
byte_offset: 52
access: Read
fieldset: TSDR
- name: TSSSR
description: "The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the RTC_ISR/TSF bit is reset."
byte_offset: 56
access: Read
fieldset: TSSSR
- name: CALR
description: "This register is write protected. The write access procedure is described in RTC register write protection on page9."
byte_offset: 60
fieldset: CALR
- name: TAMPCR
description: "RTC tamper and alternate function configuration register"
byte_offset: 64
fieldset: TAMPCR
- name: ALRMASSR
description: "This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9"
byte_offset: 68
fieldset: ALRMASSR
- name: ALRMBSSR
description: "This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode.This register is write protected.The write access procedure is described in Section: RTC register write protection."
byte_offset: 72
fieldset: ALRMBSSR
- name: OR
description: RTC option register
byte_offset: 76
fieldset: OR
- name: BKPR
description: RTC backup registers
array:
len: 32
stride: 4
byte_offset: 80
fieldset: BKPR
fieldset/ALRMAR:
description: "This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9."
fields:
- name: SU
description: "Second units in BCD format."
bit_offset: 0
bit_size: 4
- name: ST
description: Second tens in BCD format.
bit_offset: 4
bit_size: 3
- name: MSK1
description: Alarm A seconds mask
bit_offset: 7
bit_size: 1
enum: ALRMAR_MSK1
- name: MNU
description: "Minute units in BCD format."
bit_offset: 8
bit_size: 4
- name: MNT
description: Minute tens in BCD format.
bit_offset: 12
bit_size: 3
- name: MSK2
description: Alarm A minutes mask
bit_offset: 15
bit_size: 1
enum: ALRMAR_MSK1
- name: HU
description: Hour units in BCD format.
bit_offset: 16
bit_size: 4
- name: HT
description: Hour tens in BCD format.
bit_offset: 20
bit_size: 2
- name: PM
description: AM/PM notation
bit_offset: 22
bit_size: 1
enum: ALRMAR_PM
- name: MSK3
description: Alarm A hours mask
bit_offset: 23
bit_size: 1
enum: ALRMAR_MSK1
- name: DU
description: "Date units or day in BCD format."
bit_offset: 24
bit_size: 4
- name: DT
description: Date tens in BCD format.
bit_offset: 28
bit_size: 2
- name: WDSEL
description: Week day selection
bit_offset: 30
bit_size: 1
enum: ALRMAR_WDSEL
- name: MSK4
description: Alarm A date mask
bit_offset: 31
bit_size: 1
enum: ALRMAR_MSK1
fieldset/ALRMASSR:
description: "This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9"
fields:
- name: SS
description: "Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared."
bit_offset: 0
bit_size: 15
- name: MASKSS
description: "Mask the most-significant bits starting at this bit ... The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation."
bit_offset: 24
bit_size: 4
fieldset/ALRMBR:
description: "This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9."
fields:
- name: SU
description: Second units in BCD format
bit_offset: 0
bit_size: 4
- name: ST
description: Second tens in BCD format
bit_offset: 4
bit_size: 3
- name: MSK1
description: Alarm B seconds mask
bit_offset: 7
bit_size: 1
enum: ALRMBR_MSK1
- name: MNU
description: Minute units in BCD format
bit_offset: 8
bit_size: 4
- name: MNT
description: Minute tens in BCD format
bit_offset: 12
bit_size: 3
- name: MSK2
description: Alarm B minutes mask
bit_offset: 15
bit_size: 1
enum: ALRMBR_MSK1
- name: HU
description: Hour units in BCD format
bit_offset: 16
bit_size: 4
- name: HT
description: Hour tens in BCD format
bit_offset: 20
bit_size: 2
- name: PM
description: AM/PM notation
bit_offset: 22
bit_size: 1
enum: ALRMBR_PM
- name: MSK3
description: Alarm B hours mask
bit_offset: 23
bit_size: 1
enum: ALRMBR_MSK1
- name: DU
description: "Date units or day in BCD format"
bit_offset: 24
bit_size: 4
- name: DT
description: Date tens in BCD format
bit_offset: 28
bit_size: 2
- name: WDSEL
description: Week day selection
bit_offset: 30
bit_size: 1
enum: ALRMBR_WDSEL
- name: MSK4
description: Alarm B date mask
bit_offset: 31
bit_size: 1
enum: ALRMBR_MSK1
fieldset/ALRMBSSR:
description: "This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode.This register is write protected.The write access procedure is described in Section: RTC register write protection."
fields:
- name: SS
description: "Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if Alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared."
bit_offset: 0
bit_size: 15
- name: MASKSS
description: "Mask the most-significant bits starting at this bit ... The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation."
bit_offset: 24
bit_size: 4
fieldset/BKPR:
description: RTC backup registers
fields:
- name: BKP
description: "The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled."
bit_offset: 0
bit_size: 32
fieldset/CALR:
description: "This register is write protected. The write access procedure is described in RTC register write protection on page9."
fields:
- name: CALM
description: "Calibration minus The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See Section24.3.12: RTC smooth digital calibration on page13."
bit_offset: 0
bit_size: 9
- name: CALW16
description: "Use a 16-second calibration cycle period When CALW16 is set to 1, the 16-second calibration cycle period is selected.This bit must not be set to 1 if CALW8=1. Note: CALM[0] is stuck at 0 when CALW16= 1. Refer to Section24.3.12: RTC smooth digital calibration."
bit_offset: 13
bit_size: 1
enum: CALW16
- name: CALW8
description: "Use an 8-second calibration cycle period When CALW8 is set to 1, the 8-second calibration cycle period is selected. Note: CALM[1:0] are stuck at 00; when CALW8= 1. Refer to Section24.3.12: RTC smooth digital calibration."
bit_offset: 14
bit_size: 1
enum: CALW8
- name: CALP
description: "Increase frequency of RTC by 488.5 ppm This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 * CALP) - CALM. Refer to Section24.3.12: RTC smooth digital calibration."
bit_offset: 15
bit_size: 1
enum: CALP
fieldset/CR:
description: RTC control register
fields:
- name: WUCKSEL
description: Wakeup clock selection
bit_offset: 0
bit_size: 3
enum: WUCKSEL
- name: TSEDGE
description: "Time-stamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting."
bit_offset: 3
bit_size: 1
enum: TSEDGE
- name: REFCKON
description: "RTC_REFIN reference clock detection enable (50 or 60Hz) Note: PREDIV_S must be 0x00FF."
bit_offset: 4
bit_size: 1
enum: REFCKON
- name: BYPSHAD
description: "Bypass the shadow registers Note: If the frequency of the APB clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1."
bit_offset: 5
bit_size: 1
enum: BYPSHAD
- name: FMT
description: Hour format
bit_offset: 6
bit_size: 1
enum: FMT
- name: ALRAE
description: Alarm A enable
bit_offset: 8
bit_size: 1
enum: ALRAE
- name: ALRBE
description: Alarm B enable
bit_offset: 9
bit_size: 1
enum: ALRBE
- name: WUTE
description: Wakeup timer enable
bit_offset: 10
bit_size: 1
enum: WUTE
- name: TSE
description: timestamp enable
bit_offset: 11
bit_size: 1
enum: TSE
- name: ALRAIE
description: Alarm A interrupt enable
bit_offset: 12
bit_size: 1
enum: ALRAIE
- name: ALRBIE
description: Alarm B interrupt enable
bit_offset: 13
bit_size: 1
enum: ALRBIE
- name: WUTIE
description: "Wakeup timer interrupt enable"
bit_offset: 14
bit_size: 1
enum: WUTIE
- name: TSIE
description: "Time-stamp interrupt enable"
bit_offset: 15
bit_size: 1
enum: TSIE
- name: ADD1H
description: "Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0."
bit_offset: 16
bit_size: 1
enum_write: ADD1HW
- name: SUB1H
description: "Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0."
bit_offset: 17
bit_size: 1
enum_write: SUB1HW
- name: BKP
description: "Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not."
bit_offset: 18
bit_size: 1
enum: BKP
- name: COSEL
description: "Calibration output selection When COE=1, this bit selects which signal is output on RTC_CALIB. These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A=127 and PREDIV_S=255). Refer to Section24.3.15: Calibration clock output"
bit_offset: 19
bit_size: 1
enum: COSEL
- name: POL
description: "Output polarity This bit is used to configure the polarity of RTC_ALARM output"
bit_offset: 20
bit_size: 1
enum: POL
- name: OSEL
description: "Output selection These bits are used to select the flag to be routed to RTC_ALARM output"
bit_offset: 21
bit_size: 2
enum: OSEL
- name: COE
description: "Calibration output enable This bit enables the RTC_CALIB output"
bit_offset: 23
bit_size: 1
enum: COE
- name: ITSE
description: "timestamp on internal event enable"
bit_offset: 24
bit_size: 1
enum: ITSE
fieldset/DR:
description: "The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page9 and Reading the calendar on page10.This register is write protected. The write access procedure is described in RTC register write protection on page9."
fields:
- name: DU
description: Date units in BCD format
bit_offset: 0
bit_size: 4
- name: DT
description: Date tens in BCD format
bit_offset: 4
bit_size: 2
- name: MU
description: Month units in BCD format
bit_offset: 8
bit_size: 4
- name: MT
description: Month tens in BCD format
bit_offset: 12
bit_size: 1
- name: WDU
description: Week day units
bit_offset: 13
bit_size: 3
- name: YU
description: Year units in BCD format
bit_offset: 16
bit_size: 4
- name: YT
description: Year tens in BCD format
bit_offset: 20
bit_size: 4
fieldset/ISR:
description: "This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure is described in RTC register write protection on page9."
fields:
- name: ALRAWF
description: "Alarm A write flag This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode."
bit_offset: 0
bit_size: 1
enum_read: ALRAWFR
- name: ALRBWF
description: "Alarm B write flag This bit is set by hardware when Alarm B values can be changed, after the ALRBE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode."
bit_offset: 1
bit_size: 1
enum_read: ALRAWFR
- name: WUTWF
description: "Wakeup timer write flag This bit is set by hardware up to 2 RTCCLK cycles after the WUTE bit has been set to 0 in RTC_CR, and is cleared up to 2 RTCCLK cycles after the WUTE bit has been set to 1. The wakeup timer values can be changed when WUTE bit is cleared and WUTWF is set."
bit_offset: 2
bit_size: 1
enum_read: WUTWFR
- name: SHPF
description: "Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect."
bit_offset: 3
bit_size: 1
enum_read: SHPFR
- name: INITS
description: "Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state)."
bit_offset: 4
bit_size: 1
enum_read: INITSR
- name: RSF
description: "Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow register mode (BYPSHAD=1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode."
bit_offset: 5
bit_size: 1
enum_read: RSFR
enum_write: RSFW
- name: INITF
description: "Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated."
bit_offset: 6
bit_size: 1
enum_read: INITFR
- name: INIT
description: Initialization mode
bit_offset: 7
bit_size: 1
enum: INIT
- name: ALRAF
description: "Alarm A flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR). This flag is cleared by software by writing 0."
bit_offset: 8
bit_size: 1
enum_read: ALRAFR
enum_write: ALRAFW
- name: ALRBF
description: "Alarm B flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR). This flag is cleared by software by writing 0."
bit_offset: 9
bit_size: 1
enum_read: ALRBFR
enum_write: ALRBFW
- name: WUTF
description: "Wakeup timer flag This flag is set by hardware when the wakeup auto-reload counter reaches 0. This flag is cleared by software by writing 0. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again."
bit_offset: 10
bit_size: 1
enum_read: WUTFR
enum_write: WUTFW
- name: TSF
description: "Time-stamp flag This flag is set by hardware when a time-stamp event occurs. This flag is cleared by software by writing 0."
bit_offset: 11
bit_size: 1
enum_read: TSFR
enum_write: TSFW
- name: TSOVF
description: "Time-stamp overflow flag This flag is set by hardware when a time-stamp event occurs while TSF is already set. This flag is cleared by software by writing 0. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a time-stamp event occurs immediately before the TSF bit is cleared."
bit_offset: 12
bit_size: 1
enum_read: TSOVFR
enum_write: TSOVFW
- name: TAMP1F
description: "RTC_TAMP1 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP1 input. It is cleared by software writing 0"
bit_offset: 13
bit_size: 1
enum_read: TAMP1FR
enum_write: TAMP1FW
- name: TAMP2F
description: "RTC_TAMP2 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP2 input. It is cleared by software writing 0"
bit_offset: 14
bit_size: 1
enum_read: TAMP1FR
enum_write: TAMP1FW
- name: TAMP3F
description: "RTC_TAMP3 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP3 input. It is cleared by software writing 0"
bit_offset: 15
bit_size: 1
enum_read: TAMP1FR
enum_write: TAMP1FW
- name: RECALPF
description: "Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to Re-calibration on-the-fly."
bit_offset: 16
bit_size: 1
enum_read: RECALPFR
- name: ITSF
description: Internal tTime-stamp flag
bit_offset: 17
bit_size: 1
enum_read: ITSFR
enum_write: ITSFW
fieldset/OR:
description: RTC option register
fields:
- name: RTC_ALARM_TYPE
description: "RTC_ALARM output type on PC13"
bit_offset: 0
bit_size: 1
- name: RTC_OUT_RMP
description: RTC_OUT remap
bit_offset: 1
bit_size: 1
fieldset/PRER:
description: "This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page9.This register is write protected. The write access procedure is described in RTC register write protection on page9."
fields:
- name: PREDIV_S
description: "Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1)"
bit_offset: 0
bit_size: 15
- name: PREDIV_A
description: "Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)"
bit_offset: 16
bit_size: 7
fieldset/SHIFTR:
description: "This register is write protected. The write access procedure is described in RTC register write protection on page9."
fields:
- name: SUBFS
description: "Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF=1 to be sure that the shadow registers have been updated with the shifted time."
bit_offset: 0
bit_size: 15
- name: ADD1S
description: "Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation."
bit_offset: 31
bit_size: 1
enum_write: ADD1SW
fieldset/SSR:
description: RTC sub second register
fields:
- name: SS
description: "Sub second value SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR."
bit_offset: 0
bit_size: 16
fieldset/TAMPCR:
description: "RTC tamper and alternate function configuration register"
fields:
- name: TAMP1E
description: "RTC_TAMP1 input detection enable"
bit_offset: 0
bit_size: 1
- name: TAMP1TRG
description: "Active level for RTC_TAMP1 input If TAMPFLT != 00 if TAMPFLT = 00:"
bit_offset: 1
bit_size: 1
- name: TAMPIE
description: Tamper interrupt enable
bit_offset: 2
bit_size: 1
- name: TAMP2E
description: "RTC_TAMP2 input detection enable"
bit_offset: 3
bit_size: 1
- name: TAMP2TRG
description: "Active level for RTC_TAMP2 input if TAMPFLT != 00: if TAMPFLT = 00:"
bit_offset: 4
bit_size: 1
- name: TAMP3E
description: RTC_TAMP3 detection enable
bit_offset: 5
bit_size: 1
- name: TAMP3TRG
description: "Active level for RTC_TAMP3 input if TAMPFLT != 00: if TAMPFLT = 00:"
bit_offset: 6
bit_size: 1
- name: TAMPTS
description: "Activate timestamp on tamper detection event TAMPTS is valid even if TSE=0 in the RTC_CR register."
bit_offset: 7
bit_size: 1
- name: TAMPFREQ
description: "Tamper sampling frequency Determines the frequency at which each of the RTC_TAMPx inputs are sampled."
bit_offset: 8
bit_size: 3
- name: TAMPFLT
description: "RTC_TAMPx filter count These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a Tamper event. TAMPFLT is valid for each of the RTC_TAMPx inputs."
bit_offset: 11
bit_size: 2
- name: TAMPPRCH
description: "RTC_TAMPx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the RTC_TAMPx inputs."
bit_offset: 13
bit_size: 2
- name: TAMPPUDIS
description: "RTC_TAMPx pull-up disable This bit determines if each of the RTC_TAMPx pins are pre-charged before each sample."
bit_offset: 15
bit_size: 1
- name: TAMP1IE
description: Tamper 1 interrupt enable
bit_offset: 16
bit_size: 1
- name: TAMP1NOERASE
description: Tamper 1 no erase
bit_offset: 17
bit_size: 1
- name: TAMP1MF
description: Tamper 1 mask flag
bit_offset: 18
bit_size: 1
- name: TAMP2IE
description: Tamper 2 interrupt enable
bit_offset: 19
bit_size: 1
- name: TAMP2NOERASE
description: Tamper 2 no erase
bit_offset: 20
bit_size: 1
- name: TAMP2MF
description: Tamper 2 mask flag
bit_offset: 21
bit_size: 1
- name: TAMP3IE
description: Tamper 3 interrupt enable
bit_offset: 22
bit_size: 1
- name: TAMP3NOERASE
description: Tamper 3 no erase
bit_offset: 23
bit_size: 1
- name: TAMP3MF
description: Tamper 3 mask flag
bit_offset: 24
bit_size: 1
fieldset/TR:
description: "The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page9 and Reading the calendar on page10.This register is write protected. The write access procedure is described in RTC register write protection on page9."
fields:
- name: SU
description: Second units in BCD format
bit_offset: 0
bit_size: 4
- name: ST
description: Second tens in BCD format
bit_offset: 4
bit_size: 3
- name: MNU
description: Minute units in BCD format
bit_offset: 8
bit_size: 4
- name: MNT
description: Minute tens in BCD format
bit_offset: 12
bit_size: 3
- name: HU
description: Hour units in BCD format
bit_offset: 16
bit_size: 4
- name: HT
description: Hour tens in BCD format
bit_offset: 20
bit_size: 2
- name: PM
description: AM/PM notation
bit_offset: 22
bit_size: 1
enum: TR_PM
fieldset/TSDR:
description: "The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset."
fields:
- name: DU
description: Date units in BCD format
bit_offset: 0
bit_size: 4
- name: DT
description: Date tens in BCD format
bit_offset: 4
bit_size: 2
- name: MU
description: Month units in BCD format
bit_offset: 8
bit_size: 4
- name: MT
description: Month tens in BCD format
bit_offset: 12
bit_size: 1
- name: WDU
description: Week day units
bit_offset: 13
bit_size: 3
fieldset/TSSSR:
description: "The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the RTC_ISR/TSF bit is reset."
fields:
- name: SS
description: "Sub second value SS[15:0] is the value of the synchronous prescaler counter when the timestamp event occurred."
bit_offset: 0
bit_size: 16
fieldset/TSTR:
description: "The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset."
fields:
- name: SU
description: "Second units in BCD format."
bit_offset: 0
bit_size: 4
- name: ST
description: Second tens in BCD format.
bit_offset: 4
bit_size: 3
- name: MNU
description: "Minute units in BCD format."
bit_offset: 8
bit_size: 4
- name: MNT
description: Minute tens in BCD format.
bit_offset: 12
bit_size: 3
- name: HU
description: Hour units in BCD format.
bit_offset: 16
bit_size: 4
- name: HT
description: Hour tens in BCD format.
bit_offset: 20
bit_size: 2
- name: PM
description: AM/PM notation
bit_offset: 22
bit_size: 1
fieldset/WPR:
description: RTC write protection register
fields:
- name: KEY
description: "Write protection key This byte is written by software. Reading this byte always returns 0x00. Refer to RTC register write protection for a description of how to unlock RTC register write protection."
bit_offset: 0
bit_size: 8
fieldset/WUTR:
description: "This register can be written only when WUTWF is set to 1 in RTC_ISR.This register is write protected. The write access procedure is described in RTC register write protection on page9."
fields:
- name: WUT
description: "Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden."
bit_offset: 0
bit_size: 16
enum/ADD1HW:
bit_size: 1
variants:
- name: Add1
description: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode
value: 1
enum/ADD1SW:
bit_size: 1
variants:
- name: Add1
description: Add one second to the clock/calendar
value: 1
enum/ALRAE:
bit_size: 1
variants:
- name: Disabled
description: Alarm A disabled
value: 0
- name: Enabled
description: Alarm A enabled
value: 1
enum/ALRAFR:
bit_size: 1
variants:
- name: Match
description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)
value: 1
enum/ALRAFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/ALRAIE:
bit_size: 1
variants:
- name: Disabled
description: Alarm A interrupt disabled
value: 0
- name: Enabled
description: Alarm A interrupt enabled
value: 1
enum/ALRAWFR:
bit_size: 1
variants:
- name: UpdateNotAllowed
description: Alarm update not allowed
value: 0
- name: UpdateAllowed
description: Alarm update allowed
value: 1
enum/ALRBE:
bit_size: 1
variants:
- name: Disabled
description: Alarm B disabled
value: 0
- name: Enabled
description: Alarm B enabled
value: 1
enum/ALRBFR:
bit_size: 1
variants:
- name: Match
description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR)
value: 1
enum/ALRBFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/ALRBIE:
bit_size: 1
variants:
- name: Disabled
description: Alarm B Interrupt disabled
value: 0
- name: Enabled
description: Alarm B Interrupt enabled
value: 1
enum/ALRMAR_MSK1:
bit_size: 1
variants:
- name: Mask
description: Alarm set if the date/day match
value: 0
- name: NotMask
description: Date/day don’t care in Alarm comparison
value: 1
enum/ALRMAR_PM:
bit_size: 1
variants:
- name: AM
description: AM or 24-hour format
value: 0
- name: PM
description: PM
value: 1
enum/ALRMAR_WDSEL:
bit_size: 1
variants:
- name: DateUnits
description: "DU[3:0] represents the date units"
value: 0
- name: WeekDay
description: "DU[3:0] represents the week day. DT[1:0] is don’t care."
value: 1
enum/ALRMBR_MSK1:
bit_size: 1
variants:
- name: Mask
description: Alarm set if the date/day match
value: 0
- name: NotMask
description: Date/day don’t care in Alarm comparison
value: 1
enum/ALRMBR_PM:
bit_size: 1
variants:
- name: AM
description: AM or 24-hour format
value: 0
- name: PM
description: PM
value: 1
enum/ALRMBR_WDSEL:
bit_size: 1
variants:
- name: DateUnits
description: "DU[3:0] represents the date units"
value: 0
- name: WeekDay
description: "DU[3:0] represents the week day. DT[1:0] is don’t care."
value: 1
enum/BKP:
bit_size: 1
variants:
- name: DST_Not_Changed
description: Daylight Saving Time change has not been performed
value: 0
- name: DST_Changed
description: Daylight Saving Time change has been performed
value: 1
enum/BYPSHAD:
bit_size: 1
variants:
- name: ShadowReg
description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles"
value: 0
- name: BypassShadowReg
description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters"
value: 1
enum/CALP:
bit_size: 1
variants:
- name: NoChange
description: No RTCCLK pulses are added
value: 0
- name: IncreaseFreq
description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)
value: 1
enum/CALW16:
bit_size: 1
variants:
- name: Sixteen_Second
description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1"
value: 1
enum/CALW8:
bit_size: 1
variants:
- name: Eight_Second
description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected"
value: 1
enum/COE:
bit_size: 1
variants:
- name: Disabled
description: Calibration output disabled
value: 0
- name: Enabled
description: Calibration output enabled
value: 1
enum/COSEL:
bit_size: 1
variants:
- name: CalFreq_512Hz
description: Calibration output is 512 Hz (with default prescaler setting)
value: 0
- name: CalFreq_1Hz
description: Calibration output is 1 Hz (with default prescaler setting)
value: 1
enum/FMT:
bit_size: 1
variants:
- name: Twenty_Four_Hour
description: 24 hour/day format
value: 0
- name: AM_PM
description: AM/PM hour format
value: 1
enum/INIT:
bit_size: 1
variants:
- name: FreeRunningMode
description: Free running mode
value: 0
- name: InitMode
description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset."
value: 1
enum/INITFR:
bit_size: 1
variants:
- name: NotAllowed
description: Calendar registers update is not allowed
value: 0
- name: Allowed
description: Calendar registers update is allowed
value: 1
enum/INITSR:
bit_size: 1
variants:
- name: NotInitalized
description: Calendar has not been initialized
value: 0
- name: Initalized
description: Calendar has been initialized
value: 1
enum/ITSE:
bit_size: 1
variants:
- name: Disabled
description: Internal event timestamp is disabled
value: 0
- name: Enabled
description: Internal event timestamp is enabled
value: 1
enum/ITSFR:
bit_size: 1
variants:
- name: Match
description: This flag is set by hardware when a time-stamp on the internal event occurs
value: 1
enum/ITSFW:
bit_size: 1
variants:
- name: Clear
description: "This flag is cleared by software by writing 0, and must be cleared together with TSF bit by writing 0 in both bits"
value: 0
enum/OSEL:
bit_size: 2
variants:
- name: Disabled
description: Output disabled
value: 0
- name: AlarmA
description: Alarm A output enabled
value: 1
- name: AlarmB
description: Alarm B output enabled
value: 2
- name: Wakeup
description: Wakeup output enabled
value: 3
enum/POL:
bit_size: 1
variants:
- name: High
description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"
value: 0
- name: Low
description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"
value: 1
enum/RECALPFR:
bit_size: 1
variants:
- name: Pending
description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0"
value: 1
enum/REFCKON:
bit_size: 1
variants:
- name: Disabled
description: RTC_REFIN detection disabled
value: 0
- name: Enabled
description: RTC_REFIN detection enabled
value: 1
enum/RSFR:
bit_size: 1
variants:
- name: NotSynced
description: Calendar shadow registers not yet synchronized
value: 0
- name: Synced
description: Calendar shadow registers synchronized
value: 1
enum/RSFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/SHPFR:
bit_size: 1
variants:
- name: NoShiftPending
description: No shift operation is pending
value: 0
- name: ShiftPending
description: A shift operation is pending
value: 1
enum/SUB1HW:
bit_size: 1
variants:
- name: Sub1
description: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode
value: 1
enum/TAMP1FR:
bit_size: 1
variants:
- name: Tampered
description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input
value: 1
enum/TAMP1FW:
bit_size: 1
variants:
- name: Clear
description: Flag cleared by software writing 0
value: 0
enum/TR_PM:
bit_size: 1
variants:
- name: AM
description: AM or 24-hour format
value: 0
- name: PM
description: PM
value: 1
enum/TSE:
bit_size: 1
variants:
- name: Disabled
description: Timestamp disabled
value: 0
- name: Enabled
description: Timestamp enabled
value: 1
enum/TSEDGE:
bit_size: 1
variants:
- name: RisingEdge
description: RTC_TS input rising edge generates a time-stamp event
value: 0
- name: FallingEdge
description: RTC_TS input falling edge generates a time-stamp event
value: 1
enum/TSFR:
bit_size: 1
variants:
- name: TimestampEvent
description: This flag is set by hardware when a time-stamp event occurs
value: 1
enum/TSFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/TSIE:
bit_size: 1
variants:
- name: Disabled
description: Time-stamp Interrupt disabled
value: 0
- name: Enabled
description: Time-stamp Interrupt enabled
value: 1
enum/TSOVFR:
bit_size: 1
variants:
- name: Overflow
description: This flag is set by hardware when a time-stamp event occurs while TSF is already set
value: 1
enum/TSOVFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/WUCKSEL:
bit_size: 3
variants:
- name: Div16
description: RTC/16 clock is selected
value: 0
- name: Div8
description: RTC/8 clock is selected
value: 1
- name: Div4
description: RTC/4 clock is selected
value: 2
- name: Div2
description: RTC/2 clock is selected
value: 3
- name: ClockSpare
description: ck_spre (usually 1 Hz) clock is selected
value: 4
- name: ClockSpareWithOffset
description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
value: 6
enum/WUTE:
bit_size: 1
variants:
- name: Disabled
description: Wakeup timer disabled
value: 0
- name: Enabled
description: Wakeup timer enabled
value: 1
enum/WUTFR:
bit_size: 1
variants:
- name: Zero
description: This flag is set by hardware when the wakeup auto-reload counter reaches 0
value: 1
enum/WUTFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/WUTIE:
bit_size: 1
variants:
- name: Disabled
description: Wakeup timer interrupt disabled
value: 0
- name: Enabled
description: Wakeup timer interrupt enabled
value: 1
enum/WUTWFR:
bit_size: 1
variants:
- name: UpdateNotAllowed
description: Wakeup timer configuration update not allowed
value: 0
- name: UpdateAllowed
description: Wakeup timer configuration update allowed
value: 1
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