4450 lines
96 KiB
YAML
4450 lines
96 KiB
YAML
block/RCC:
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description: Reset and clock control
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items:
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- name: CR
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description: clock control register
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byte_offset: 0
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fieldset: CR
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- name: HSICFGR
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description: RCC HSI configuration register
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byte_offset: 4
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fieldset: HSICFGR
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- name: CRRCR
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description: RCC Clock Recovery RC Register
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byte_offset: 8
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access: Read
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fieldset: CRRCR
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- name: CSICFGR
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description: RCC CSI configuration register
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byte_offset: 12
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fieldset: CSICFGR
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- name: CFGR
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description: RCC Clock Configuration Register
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byte_offset: 16
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fieldset: CFGR
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- name: D1CFGR
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description: RCC Domain 1 Clock Configuration Register
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byte_offset: 24
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fieldset: D1CFGR
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- name: D2CFGR
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description: RCC Domain 2 Clock Configuration Register
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byte_offset: 28
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fieldset: D2CFGR
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- name: D3CFGR
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description: RCC Domain 3 Clock Configuration Register
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byte_offset: 32
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fieldset: D3CFGR
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- name: PLLCKSELR
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description: RCC PLLs Clock Source Selection Register
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byte_offset: 40
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fieldset: PLLCKSELR
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- name: PLLCFGR
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description: RCC PLLs Configuration Register
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byte_offset: 44
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fieldset: PLLCFGR
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- name: PLLDIVR
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description: RCC PLL1 Dividers Configuration Register
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array:
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len: 3
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stride: 8
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byte_offset: 48
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fieldset: PLLDIVR
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- name: PLLFRACR
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description: RCC PLL1 Fractional Divider Register
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array:
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len: 3
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stride: 8
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byte_offset: 52
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fieldset: PLLFRACR
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- name: D1CCIPR
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description: RCC Domain 1 Kernel Clock Configuration Register
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byte_offset: 76
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fieldset: D1CCIPR
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- name: D2CCIP1R
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description: RCC Domain 2 Kernel Clock Configuration Register
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byte_offset: 80
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fieldset: D2CCIP1R
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- name: D2CCIP2R
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description: RCC Domain 2 Kernel Clock Configuration Register
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byte_offset: 84
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fieldset: D2CCIP2R
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- name: D3CCIPR
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description: RCC Domain 3 Kernel Clock Configuration Register
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byte_offset: 88
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fieldset: D3CCIPR
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- name: CIER
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description: RCC Clock Source Interrupt Enable Register
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byte_offset: 96
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fieldset: CIER
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- name: CIFR
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description: RCC Clock Source Interrupt Flag Register
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byte_offset: 100
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access: Read
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fieldset: CIFR
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- name: CICR
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description: RCC Clock Source Interrupt Clear Register
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byte_offset: 104
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fieldset: CICR
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- name: BDCR
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description: RCC Backup Domain Control Register
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byte_offset: 112
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fieldset: BDCR
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- name: CSR
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description: RCC Clock Control and Status Register
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byte_offset: 116
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fieldset: CSR
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- name: AHB3RSTR
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description: RCC AHB3 Reset Register
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byte_offset: 124
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fieldset: AHB3RSTR
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- name: AHB1RSTR
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description: RCC AHB1 Peripheral Reset Register
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byte_offset: 128
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fieldset: AHB1RSTR
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- name: AHB2RSTR
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description: RCC AHB2 Peripheral Reset Register
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byte_offset: 132
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fieldset: AHB2RSTR
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- name: AHB4RSTR
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description: RCC AHB4 Peripheral Reset Register
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byte_offset: 136
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fieldset: AHB4RSTR
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- name: APB3RSTR
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description: RCC APB3 Peripheral Reset Register
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byte_offset: 140
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fieldset: APB3RSTR
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- name: APB1LRSTR
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description: RCC APB1 Peripheral Reset Register
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byte_offset: 144
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fieldset: APB1LRSTR
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- name: APB1HRSTR
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description: RCC APB1 Peripheral Reset Register
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byte_offset: 148
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fieldset: APB1HRSTR
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- name: APB2RSTR
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description: RCC APB2 Peripheral Reset Register
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byte_offset: 152
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fieldset: APB2RSTR
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- name: APB4RSTR
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description: RCC APB4 Peripheral Reset Register
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byte_offset: 156
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fieldset: APB4RSTR
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- name: GCR
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description: Global Control Register
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byte_offset: 160
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fieldset: GCR
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- name: D3AMR
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description: RCC D3 Autonomous mode Register
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byte_offset: 168
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fieldset: D3AMR
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- name: RSR
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description: RCC Reset Status Register
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byte_offset: 304
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fieldset: RSR
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- name: AHB3ENR
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description: RCC AHB3 Clock Register
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byte_offset: 308
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fieldset: AHB3ENR
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- name: AHB1ENR
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description: RCC AHB1 Clock Register
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byte_offset: 312
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fieldset: AHB1ENR
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- name: AHB2ENR
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description: RCC AHB2 Clock Register
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byte_offset: 316
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fieldset: AHB2ENR
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- name: AHB4ENR
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description: RCC AHB4 Clock Register
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byte_offset: 320
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fieldset: AHB4ENR
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- name: APB3ENR
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description: RCC APB3 Clock Register
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byte_offset: 324
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fieldset: APB3ENR
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- name: APB1LENR
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description: RCC APB1 Clock Register
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byte_offset: 328
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fieldset: APB1LENR
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- name: APB1HENR
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description: RCC APB1 Clock Register
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byte_offset: 332
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fieldset: APB1HENR
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- name: APB2ENR
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description: RCC APB2 Clock Register
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byte_offset: 336
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fieldset: APB2ENR
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- name: APB4ENR
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description: RCC APB4 Clock Register
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byte_offset: 340
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fieldset: APB4ENR
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- name: AHB3LPENR
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description: RCC AHB3 Sleep Clock Register
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byte_offset: 348
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fieldset: AHB3LPENR
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- name: AHB1LPENR
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description: RCC AHB1 Sleep Clock Register
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byte_offset: 352
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fieldset: AHB1LPENR
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- name: AHB2LPENR
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description: RCC AHB2 Sleep Clock Register
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byte_offset: 356
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fieldset: AHB2LPENR
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- name: AHB4LPENR
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description: RCC AHB4 Sleep Clock Register
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byte_offset: 360
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fieldset: AHB4LPENR
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- name: APB3LPENR
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description: RCC APB3 Sleep Clock Register
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byte_offset: 364
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fieldset: APB3LPENR
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- name: APB1LLPENR
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description: RCC APB1 Low Sleep Clock Register
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byte_offset: 368
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fieldset: APB1LLPENR
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- name: APB1HLPENR
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description: RCC APB1 High Sleep Clock Register
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byte_offset: 372
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fieldset: APB1HLPENR
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- name: APB2LPENR
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description: RCC APB2 Sleep Clock Register
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byte_offset: 376
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fieldset: APB2LPENR
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- name: APB4LPENR
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description: RCC APB4 Sleep Clock Register
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byte_offset: 380
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fieldset: APB4LPENR
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fieldset/AHB1ENR:
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description: RCC AHB1 Clock Register
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fields:
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- name: DMA1EN
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description: DMA1 Clock Enable
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bit_offset: 0
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bit_size: 1
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- name: DMA2EN
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description: DMA2 Clock Enable
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bit_offset: 1
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bit_size: 1
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- name: ADC12EN
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description: ADC1/2 Peripheral Clocks Enable
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bit_offset: 5
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bit_size: 1
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- name: ARTEN
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description: ART Clock Enable
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bit_offset: 14
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bit_size: 1
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- name: ETH1MACEN
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description: Ethernet MAC bus interface Clock Enable
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bit_offset: 15
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bit_size: 1
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- name: ETH1TXEN
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description: Ethernet Transmission Clock Enable
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bit_offset: 16
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bit_size: 1
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- name: ETH1RXEN
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description: Ethernet Reception Clock Enable
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bit_offset: 17
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bit_size: 1
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- name: USB_OTG_HSEN
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description: USB_OTG_HS Peripheral Clocks Enable
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bit_offset: 25
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bit_size: 1
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- name: USB_OTG_HS_ULPIEN
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description: USB_OTG_HS ULPI clock enable
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bit_offset: 26
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bit_size: 1
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- name: USB_OTG_FSEN
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description: USB_OTG_FS Peripheral Clocks Enable
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bit_offset: 27
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bit_size: 1
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- name: USB_OTG_FS_ULPIEN
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description: USB_OTG_FS ULPI clock enable
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bit_offset: 28
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bit_size: 1
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fieldset/AHB1LPENR:
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description: RCC AHB1 Sleep Clock Register
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fields:
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- name: DMA1LPEN
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description: DMA1 Clock Enable During CSleep Mode
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bit_offset: 0
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bit_size: 1
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- name: DMA2LPEN
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description: DMA2 Clock Enable During CSleep Mode
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bit_offset: 1
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bit_size: 1
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- name: ADC12LPEN
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description: ADC1/2 Peripheral Clocks Enable During CSleep Mode
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bit_offset: 5
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bit_size: 1
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- name: ARTLPEN
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description: ART Clock Enable During CSleep Mode
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bit_offset: 14
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bit_size: 1
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- name: ETH1MACLPEN
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description: Ethernet MAC bus interface Clock Enable During CSleep Mode
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bit_offset: 15
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bit_size: 1
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- name: ETH1TXLPEN
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description: Ethernet Transmission Clock Enable During CSleep Mode
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bit_offset: 16
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bit_size: 1
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- name: ETH1RXLPEN
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description: Ethernet Reception Clock Enable During CSleep Mode
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bit_offset: 17
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bit_size: 1
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- name: USB_OTG_HSLPEN
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description: USB_OTG_HS peripheral clock enable during CSleep mode
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bit_offset: 25
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bit_size: 1
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- name: USB_OTG_HS_ULPILPEN
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description: USB_PHY1 clock enable during CSleep mode
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bit_offset: 26
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bit_size: 1
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- name: USB_OTG_FSLPEN
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description: USB_OTG_FS peripheral clock enable during CSleep mode
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bit_offset: 27
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bit_size: 1
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- name: USB_OTG_FS_ULPILPEN
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description: USB_PHY2 clocks enable during CSleep mode
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bit_offset: 28
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bit_size: 1
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fieldset/AHB1RSTR:
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description: RCC AHB1 Peripheral Reset Register
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fields:
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- name: DMA1RST
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description: DMA1 block reset
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bit_offset: 0
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bit_size: 1
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- name: DMA2RST
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description: DMA2 block reset
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bit_offset: 1
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bit_size: 1
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- name: ADC12RST
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description: ADC1&2 block reset
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bit_offset: 5
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bit_size: 1
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- name: ARTRST
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description: ART block reset
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bit_offset: 14
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bit_size: 1
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- name: ETH1MACRST
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description: ETH1MAC block reset
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bit_offset: 15
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bit_size: 1
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- name: USB_OTG_HSRST
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description: USB_OTG_HS block reset
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bit_offset: 25
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bit_size: 1
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- name: USB_OTG_FSRST
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description: USB_OTG_FS block reset
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bit_offset: 27
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bit_size: 1
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fieldset/AHB2ENR:
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description: RCC AHB2 Clock Register
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fields:
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- name: DCMIEN
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description: DCMI peripheral clock
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bit_offset: 0
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bit_size: 1
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- name: CRYPTEN
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description: CRYPT peripheral clock enable
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bit_offset: 4
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bit_size: 1
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- name: HASHEN
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description: HASH peripheral clock enable
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bit_offset: 5
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bit_size: 1
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- name: RNGEN
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description: RNG peripheral clocks enable
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bit_offset: 6
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bit_size: 1
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- name: SDMMC2EN
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description: SDMMC2 and SDMMC2 delay clock enable
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bit_offset: 9
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bit_size: 1
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- name: BDMA1EN
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description: BDMA1 clock enable
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bit_offset: 11
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bit_size: 1
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- name: FMACEN
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description: FMAC enable
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bit_offset: 16
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bit_size: 1
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- name: CORDICEN
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description: CORDIC enable
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bit_offset: 17
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bit_size: 1
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- name: SRAM1EN
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description: SRAM1 block enable
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bit_offset: 29
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bit_size: 1
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- name: SRAM2EN
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description: SRAM2 block enable
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bit_offset: 30
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bit_size: 1
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- name: SRAM3EN
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description: SRAM3 block enable
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bit_offset: 31
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bit_size: 1
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fieldset/AHB2LPENR:
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description: RCC AHB2 Sleep Clock Register
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fields:
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- name: DCMILPEN
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description: DCMI peripheral clock enable during csleep mode
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bit_offset: 0
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bit_size: 1
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- name: CRYPTLPEN
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description: CRYPT peripheral clock enable during CSleep mode
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bit_offset: 4
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bit_size: 1
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- name: HASHLPEN
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description: HASH peripheral clock enable during CSleep mode
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bit_offset: 5
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bit_size: 1
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- name: RNGLPEN
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description: RNG peripheral clock enable during CSleep mode
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bit_offset: 6
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bit_size: 1
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- name: SDMMC2LPEN
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description: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode
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bit_offset: 9
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bit_size: 1
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- name: BDMA1LPEN
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description: BDMA1 Clock Enable During CSleep Mode
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bit_offset: 11
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bit_size: 1
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- name: FMACLPEN
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description: FMAC enable during CSleep Mode
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bit_offset: 16
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bit_size: 1
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- name: CORDICLPEN
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description: CORDIC enable during CSleep Mode
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bit_offset: 17
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bit_size: 1
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- name: SRAM1LPEN
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description: SRAM1 Clock Enable During CSleep Mode
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bit_offset: 29
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bit_size: 1
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- name: SRAM2LPEN
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description: SRAM2 Clock Enable During CSleep Mode
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bit_offset: 30
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bit_size: 1
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- name: SRAM3LPEN
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description: SRAM3 Clock Enable During CSleep Mode
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bit_offset: 31
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bit_size: 1
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fieldset/AHB2RSTR:
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description: RCC AHB2 Peripheral Reset Register
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fields:
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- name: DCMIRST
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description: DCMI block reset
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bit_offset: 0
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bit_size: 1
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- name: CRYPTRST
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description: Cryptography block reset
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bit_offset: 4
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bit_size: 1
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- name: HASHRST
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description: Hash block reset
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bit_offset: 5
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bit_size: 1
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- name: RNGRST
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description: Random Number Generator block reset
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bit_offset: 6
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bit_size: 1
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- name: SDMMC2RST
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description: SDMMC2 and SDMMC2 Delay block reset
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bit_offset: 9
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bit_size: 1
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- name: BDMA1RST
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description: BDMA1 block reset
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bit_offset: 11
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bit_size: 1
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- name: FMACRST
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description: FMAC reset
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bit_offset: 16
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bit_size: 1
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- name: CORDICRST
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description: CORDIC reset
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bit_offset: 17
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bit_size: 1
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fieldset/AHB3ENR:
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description: RCC AHB3 Clock Register
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fields:
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- name: MDMAEN
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description: MDMA Peripheral Clock Enable
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bit_offset: 0
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bit_size: 1
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- name: DMA2DEN
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description: DMA2D Peripheral Clock Enable
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bit_offset: 4
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bit_size: 1
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- name: JPGDECEN
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description: JPGDEC Peripheral Clock Enable
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bit_offset: 5
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bit_size: 1
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- name: FMCEN
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description: FMC Peripheral Clocks Enable
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bit_offset: 12
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bit_size: 1
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- name: QUADSPIEN
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description: QUADSPI and QUADSPI Delay Clock Enable
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bit_offset: 14
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bit_size: 1
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- name: SDMMC1EN
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description: SDMMC1 and SDMMC1 Delay Clock Enable
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bit_offset: 16
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bit_size: 1
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- name: OCTOSPI2EN
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description: OCTOSPI2 and OCTOSPI2 delay block enable
|
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bit_offset: 19
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bit_size: 1
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- name: IOMNGREN
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description: OCTOSPI IO manager enable
|
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bit_offset: 21
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bit_size: 1
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- name: OTFD1EN
|
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description: OTFDEC1 enable
|
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bit_offset: 22
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bit_size: 1
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- name: OTFD2EN
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description: OTFDEC2 enable
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bit_offset: 23
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bit_size: 1
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- name: DTCM1EN
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description: D1 DTCM1 block enable
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bit_offset: 28
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bit_size: 1
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- name: DTCM2EN
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description: D1 DTCM2 block enable
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bit_offset: 29
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bit_size: 1
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- name: ITCM1EN
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description: D1 ITCM block enable
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bit_offset: 30
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bit_size: 1
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- name: AXISRAMEN
|
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description: AXISRAM block enable
|
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bit_offset: 31
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bit_size: 1
|
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fieldset/AHB3LPENR:
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description: RCC AHB3 Sleep Clock Register
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fields:
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- name: MDMALPEN
|
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description: MDMA Clock Enable During CSleep Mode
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bit_offset: 0
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bit_size: 1
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- name: DMA2DLPEN
|
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description: DMA2D Clock Enable During CSleep Mode
|
|
bit_offset: 4
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bit_size: 1
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- name: JPGDECLPEN
|
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description: JPGDEC Clock Enable During CSleep Mode
|
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bit_offset: 5
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bit_size: 1
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- name: FLASHLPEN
|
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description: FLASH Clock Enable During CSleep Mode
|
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bit_offset: 8
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|
bit_size: 1
|
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- name: FMCLPEN
|
|
description: FMC Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: QSPILPEN
|
|
description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: SDMMC1LPEN
|
|
description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: OCTOSPI2LPEN
|
|
description: OCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: IOMNGRLPEN
|
|
description: OCTOSPI IO manager enable during CSleep Mode
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: OTFD1LPEN
|
|
description: OTFDEC1 enable during CSleep Mode
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: OTFD2LPEN
|
|
description: OTFDEC2 enable during CSleep Mode
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: D1DTCM1LPEN
|
|
description: D1DTCM1 Block Clock Enable During CSleep mode
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: DTCM2LPEN
|
|
description: D1 DTCM2 Block Clock Enable During CSleep mode
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: ITCMLPEN
|
|
description: D1ITCM Block Clock Enable During CSleep mode
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: AXISRAMLPEN
|
|
description: AXISRAM Block Clock Enable During CSleep mode
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/AHB3RSTR:
|
|
description: RCC AHB3 Reset Register
|
|
fields:
|
|
- name: MDMARST
|
|
description: MDMA block reset
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: DMA2DRST
|
|
description: DMA2D block reset
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: JPGDECRST
|
|
description: JPGDEC block reset
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: FMCRST
|
|
description: FMC block reset
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: QSPIRST
|
|
description: QUADSPI and QUADSPI delay block reset
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: SDMMC1RST
|
|
description: SDMMC1 and SDMMC1 delay block reset
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: OCTOSPI2RST
|
|
description: OCTOSPI2 and OCTOSPI2 delay block reset
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: IOMNGRRST
|
|
description: OCTOSPI IO manager reset
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: OTFD1RST
|
|
description: OTFDEC1 reset
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: OTFD2RST
|
|
description: OTFDEC2 reset
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: CPURST
|
|
description: CPU reset
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/AHB4ENR:
|
|
description: RCC AHB4 Clock Register
|
|
fields:
|
|
- name: GPIOAEN
|
|
description: 0GPIO peripheral clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: GPIOBEN
|
|
description: 0GPIO peripheral clock enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: GPIOCEN
|
|
description: 0GPIO peripheral clock enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: GPIODEN
|
|
description: 0GPIO peripheral clock enable
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: GPIOEEN
|
|
description: 0GPIO peripheral clock enable
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: GPIOFEN
|
|
description: 0GPIO peripheral clock enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: GPIOGEN
|
|
description: 0GPIO peripheral clock enable
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: GPIOHEN
|
|
description: 0GPIO peripheral clock enable
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: GPIOIEN
|
|
description: 0GPIO peripheral clock enable
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: GPIOJEN
|
|
description: 0GPIO peripheral clock enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: GPIOKEN
|
|
description: 0GPIO peripheral clock enable
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: CRCEN
|
|
description: CRC peripheral clock enable
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: BDMA2EN
|
|
description: BDMA2 and DMAMUX2 Clock Enable
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: BDMAEN
|
|
description: BDMA and DMAMUX2 Clock Enable
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: ADC3EN
|
|
description: ADC3 Peripheral Clocks Enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: HSEMEN
|
|
description: HSEM peripheral clock enable
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: BKPSRAMEN
|
|
description: Backup RAM Clock Enable
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
fieldset/AHB4LPENR:
|
|
description: RCC AHB4 Sleep Clock Register
|
|
fields:
|
|
- name: GPIOALPEN
|
|
description: GPIO peripheral clock enable during CSleep mode
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: GPIOBLPEN
|
|
description: GPIO peripheral clock enable during CSleep mode
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: GPIOCLPEN
|
|
description: GPIO peripheral clock enable during CSleep mode
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: GPIODLPEN
|
|
description: GPIO peripheral clock enable during CSleep mode
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: GPIOELPEN
|
|
description: GPIO peripheral clock enable during CSleep mode
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: GPIOFLPEN
|
|
description: GPIO peripheral clock enable during CSleep mode
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: GPIOGLPEN
|
|
description: GPIO peripheral clock enable during CSleep mode
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: GPIOHLPEN
|
|
description: GPIO peripheral clock enable during CSleep mode
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: GPIOILPEN
|
|
description: GPIO peripheral clock enable during CSleep mode
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: GPIOJLPEN
|
|
description: GPIO peripheral clock enable during CSleep mode
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: GPIOKLPEN
|
|
description: GPIO peripheral clock enable during CSleep mode
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: CRCLPEN
|
|
description: CRC peripheral clock enable during CSleep mode
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: BDMA2LPEN
|
|
description: BDMA2 Clock Enable During CSleep Mode
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: BDMALPEN
|
|
description: BDMA Clock Enable During CSleep Mode
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: ADC3LPEN
|
|
description: ADC3 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: BKPSRAMLPEN
|
|
description: Backup RAM Clock Enable During CSleep Mode
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: SRAM4LPEN
|
|
description: SRAM4 Clock Enable During CSleep Mode
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
fieldset/AHB4RSTR:
|
|
description: RCC AHB4 Peripheral Reset Register
|
|
fields:
|
|
- name: GPIOARST
|
|
description: GPIO block reset
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: GPIOBRST
|
|
description: GPIO block reset
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: GPIOCRST
|
|
description: GPIO block reset
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: GPIODRST
|
|
description: GPIO block reset
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: GPIOERST
|
|
description: GPIO block reset
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: GPIOFRST
|
|
description: GPIO block reset
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: GPIOGRST
|
|
description: GPIO block reset
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: GPIOHRST
|
|
description: GPIO block reset
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: GPIOIRST
|
|
description: GPIO block reset
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: GPIOJRST
|
|
description: GPIO block reset
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: GPIOKRST
|
|
description: GPIO block reset
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: CRCRST
|
|
description: CRC block reset
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: BDMA2RST
|
|
description: BDMA2 block reset
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: BDMARST
|
|
description: BDMA block reset
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: ADC3RST
|
|
description: ADC3 block reset
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: HSEMRST
|
|
description: HSEM block reset
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
fieldset/APB1HENR:
|
|
description: RCC APB1 Clock Register
|
|
fields:
|
|
- name: CRSEN
|
|
description: Clock Recovery System peripheral clock enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: SWPEN
|
|
description: SWPMI Peripheral Clocks Enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: OPAMPEN
|
|
description: OPAMP peripheral clock enable
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: MDIOSEN
|
|
description: MDIOS peripheral clock enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: FDCANEN
|
|
description: FDCAN Peripheral Clocks Enable
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: TIM23EN
|
|
description: TIM23 block enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: TIM24EN
|
|
description: TIM24 block enable
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
fieldset/APB1HLPENR:
|
|
description: RCC APB1 High Sleep Clock Register
|
|
fields:
|
|
- name: CRSLPEN
|
|
description: Clock Recovery System peripheral clock enable during CSleep mode
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: SWPLPEN
|
|
description: SWPMI Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: OPAMPLPEN
|
|
description: OPAMP peripheral clock enable during CSleep mode
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: MDIOSLPEN
|
|
description: MDIOS peripheral clock enable during CSleep mode
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: FDCANLPEN
|
|
description: FDCAN Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: TIM23LPEN
|
|
description: TIM23 block enable during CSleep Mode
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: TIM24LPEN
|
|
description: TIM24 block enable during CSleep Mode
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
fieldset/APB1HRSTR:
|
|
description: RCC APB1 Peripheral Reset Register
|
|
fields:
|
|
- name: CRSRST
|
|
description: Clock Recovery System reset
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: SWPRST
|
|
description: SWPMI block reset
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: OPAMPRST
|
|
description: OPAMP block reset
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: MDIOSRST
|
|
description: MDIOS block reset
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: FDCANRST
|
|
description: FDCAN block reset
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: TIM23RST
|
|
description: TIM23 block reset
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: TIM24RST
|
|
description: TIM24 block reset
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
fieldset/APB1LENR:
|
|
description: RCC APB1 Clock Register
|
|
fields:
|
|
- name: TIM2EN
|
|
description: TIM peripheral clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: TIM3EN
|
|
description: TIM peripheral clock enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: TIM4EN
|
|
description: TIM peripheral clock enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: TIM5EN
|
|
description: TIM peripheral clock enable
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: TIM6EN
|
|
description: TIM peripheral clock enable
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: TIM7EN
|
|
description: TIM peripheral clock enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: TIM12EN
|
|
description: TIM peripheral clock enable
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: TIM13EN
|
|
description: TIM peripheral clock enable
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: TIM14EN
|
|
description: TIM peripheral clock enable
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LPTIM1EN
|
|
description: LPTIM1 Peripheral Clocks Enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: WWDG2EN
|
|
description: WWDG2 peripheral clock enable
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI2EN
|
|
description: SPI2 Peripheral Clocks Enable
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: SPI3EN
|
|
description: SPI3 Peripheral Clocks Enable
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: SPDIFRXEN
|
|
description: SPDIFRX Peripheral Clocks Enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: USART2EN
|
|
description: USART2 Peripheral Clocks Enable
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: USART3EN
|
|
description: USART3 Peripheral Clocks Enable
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: UART4EN
|
|
description: UART4 Peripheral Clocks Enable
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: UART5EN
|
|
description: UART5 Peripheral Clocks Enable
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: I2C1EN
|
|
description: I2C1 Peripheral Clocks Enable
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: I2C2EN
|
|
description: I2C2 Peripheral Clocks Enable
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: I2C3EN
|
|
description: I2C3 Peripheral Clocks Enable
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: I2C5EN
|
|
description: "I2C5 Peripheral Clocks\r Enable"
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: CECEN
|
|
description: HDMI-CEC peripheral clock enable
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: DAC1EN
|
|
description: DAC1 (containing two converters) peripheral clock enable
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: UART7EN
|
|
description: UART7 Peripheral Clocks Enable
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: UART8EN
|
|
description: UART8 Peripheral Clocks Enable
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/APB1LLPENR:
|
|
description: RCC APB1 Low Sleep Clock Register
|
|
fields:
|
|
- name: TIM2LPEN
|
|
description: TIM2 peripheral clock enable during CSleep mode
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: TIM3LPEN
|
|
description: TIM3 peripheral clock enable during CSleep mode
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: TIM4LPEN
|
|
description: TIM4 peripheral clock enable during CSleep mode
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: TIM5LPEN
|
|
description: TIM5 peripheral clock enable during CSleep mode
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: TIM6LPEN
|
|
description: TIM6 peripheral clock enable during CSleep mode
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: TIM7LPEN
|
|
description: TIM7 peripheral clock enable during CSleep mode
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: TIM12LPEN
|
|
description: TIM12 peripheral clock enable during CSleep mode
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: TIM13LPEN
|
|
description: TIM13 peripheral clock enable during CSleep mode
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: TIM14LPEN
|
|
description: TIM14 peripheral clock enable during CSleep mode
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LPTIM1LPEN
|
|
description: LPTIM1 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: WWDG2LPEN
|
|
description: WWDG2 peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI2LPEN
|
|
description: SPI2 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: SPI3LPEN
|
|
description: SPI3 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: SPDIFRXLPEN
|
|
description: SPDIFRX Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: USART2LPEN
|
|
description: USART2 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: USART3LPEN
|
|
description: USART3 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: UART4LPEN
|
|
description: UART4 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: UART5LPEN
|
|
description: UART5 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: I2C1LPEN
|
|
description: I2C1 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: I2C2LPEN
|
|
description: I2C2 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: I2C3LPEN
|
|
description: I2C3 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: I2C5LPEN
|
|
description: I2C5 block enable during CSleep Mode
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: CECLPEN
|
|
description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: DAC1LPEN
|
|
description: DAC1 (containing two converters) peripheral clock enable during CSleep mode
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: UART7LPEN
|
|
description: UART7 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: UART8LPEN
|
|
description: UART8 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/APB1LRSTR:
|
|
description: RCC APB1 Peripheral Reset Register
|
|
fields:
|
|
- name: TIM2RST
|
|
description: TIM block reset
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: TIM3RST
|
|
description: TIM block reset
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: TIM4RST
|
|
description: TIM block reset
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: TIM5RST
|
|
description: TIM block reset
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: TIM6RST
|
|
description: TIM block reset
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: TIM7RST
|
|
description: TIM block reset
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: TIM12RST
|
|
description: TIM block reset
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: TIM13RST
|
|
description: TIM block reset
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: TIM14RST
|
|
description: TIM block reset
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LPTIM1RST
|
|
description: TIM block reset
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: SPI2RST
|
|
description: SPI2 block reset
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: SPI3RST
|
|
description: SPI3 block reset
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: SPDIFRXRST
|
|
description: SPDIFRX block reset
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: USART2RST
|
|
description: USART2 block reset
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: USART3RST
|
|
description: USART3 block reset
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: UART4RST
|
|
description: UART4 block reset
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: UART5RST
|
|
description: UART5 block reset
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: I2C1RST
|
|
description: I2C1 block reset
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: I2C2RST
|
|
description: I2C2 block reset
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: I2C3RST
|
|
description: I2C3 block reset
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: I2C5RST
|
|
description: I2C5 block reset
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: CECRST
|
|
description: HDMI-CEC block reset
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: DAC1RST
|
|
description: DAC1 (containing two converters) reset
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: UART7RST
|
|
description: UART7 block reset
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: UART8RST
|
|
description: UART8 block reset
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/APB2ENR:
|
|
description: RCC APB2 Clock Register
|
|
fields:
|
|
- name: TIM1EN
|
|
description: TIM1 peripheral clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: TIM8EN
|
|
description: TIM8 peripheral clock enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: USART1EN
|
|
description: USART1 Peripheral Clocks Enable
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: USART6EN
|
|
description: USART6 Peripheral Clocks Enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: UART9EN
|
|
description: "UART9 Peripheral Clocks\r Enable"
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: USART10EN
|
|
description: "USART10 Peripheral Clocks\r Enable"
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: SPI1EN
|
|
description: SPI1 Peripheral Clocks Enable
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: SPI4EN
|
|
description: SPI4 Peripheral Clocks Enable
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: TIM15EN
|
|
description: TIM15 peripheral clock enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: TIM16EN
|
|
description: TIM16 peripheral clock enable
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM17EN
|
|
description: TIM17 peripheral clock enable
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: SPI5EN
|
|
description: SPI5 Peripheral Clocks Enable
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: SAI1EN
|
|
description: SAI1 Peripheral Clocks Enable
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: SAI2EN
|
|
description: SAI2 Peripheral Clocks Enable
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: SAI3EN
|
|
description: SAI3 Peripheral Clocks Enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: DFSDM1EN
|
|
description: DFSDM1 Peripheral Clocks Enable
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: HRTIMEN
|
|
description: HRTIM peripheral clock enable
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
fieldset/APB2LPENR:
|
|
description: RCC APB2 Sleep Clock Register
|
|
fields:
|
|
- name: TIM1LPEN
|
|
description: TIM1 peripheral clock enable during CSleep mode
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: TIM8LPEN
|
|
description: TIM8 peripheral clock enable during CSleep mode
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: USART1LPEN
|
|
description: USART1 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: USART6LPEN
|
|
description: USART6 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: SPI1LPEN
|
|
description: SPI1 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: SPI4LPEN
|
|
description: SPI4 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: TIM15LPEN
|
|
description: TIM15 peripheral clock enable during CSleep mode
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: TIM16LPEN
|
|
description: TIM16 peripheral clock enable during CSleep mode
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM17LPEN
|
|
description: TIM17 peripheral clock enable during CSleep mode
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: SPI5LPEN
|
|
description: SPI5 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: SAI1LPEN
|
|
description: SAI1 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: SAI2LPEN
|
|
description: SAI2 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: SAI3LPEN
|
|
description: SAI3 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: DFSDM1LPEN
|
|
description: DFSDM1 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: HRTIMLPEN
|
|
description: HRTIM peripheral clock enable during CSleep mode
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
fieldset/APB2RSTR:
|
|
description: RCC APB2 Peripheral Reset Register
|
|
fields:
|
|
- name: TIM1RST
|
|
description: TIM1 block reset
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: TIM8RST
|
|
description: TIM8 block reset
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: USART1RST
|
|
description: USART1 block reset
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: USART6RST
|
|
description: USART6 block reset
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: UART9RST
|
|
description: UART9 block reset
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: USART10RST
|
|
description: USART10 block reset
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: SPI1RST
|
|
description: SPI1 block reset
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: SPI4RST
|
|
description: SPI4 block reset
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: TIM15RST
|
|
description: TIM15 block reset
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: TIM16RST
|
|
description: TIM16 block reset
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM17RST
|
|
description: TIM17 block reset
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: SPI5RST
|
|
description: SPI5 block reset
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: SAI1RST
|
|
description: SAI1 block reset
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: SAI2RST
|
|
description: SAI2 block reset
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: SAI3RST
|
|
description: SAI3 block reset
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: DFSDM1RST
|
|
description: DFSDM1 block reset
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: HRTIMRST
|
|
description: HRTIM block reset
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
fieldset/APB3ENR:
|
|
description: RCC APB3 Clock Register
|
|
fields:
|
|
- name: LTDCEN
|
|
description: LTDC peripheral clock enable
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: DSIEN
|
|
description: DSI Peripheral clocks enable
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: WWDG1EN
|
|
description: WWDG1 Clock Enable
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
fieldset/APB3LPENR:
|
|
description: RCC APB3 Sleep Clock Register
|
|
fields:
|
|
- name: LTDCLPEN
|
|
description: LTDC peripheral clock enable during CSleep mode
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: DSILPEN
|
|
description: DSI Peripheral Clock Enable During CSleep Mode
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: WWDG1LPEN
|
|
description: WWDG1 Clock Enable During CSleep Mode
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
fieldset/APB3RSTR:
|
|
description: RCC APB3 Peripheral Reset Register
|
|
fields:
|
|
- name: LTDCRST
|
|
description: LTDC block reset
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: DSIRST
|
|
description: DSI block reset
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
fieldset/APB4ENR:
|
|
description: RCC APB4 Clock Register
|
|
fields:
|
|
- name: SYSCFGEN
|
|
description: SYSCFG peripheral clock enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: LPUART1EN
|
|
description: LPUART1 Peripheral Clocks Enable
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: SPI6EN
|
|
description: SPI6 Peripheral Clocks Enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: I2C4EN
|
|
description: I2C4 Peripheral Clocks Enable
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: LPTIM2EN
|
|
description: LPTIM2 Peripheral Clocks Enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: LPTIM3EN
|
|
description: LPTIM3 Peripheral Clocks Enable
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: LPTIM4EN
|
|
description: LPTIM4 Peripheral Clocks Enable
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: LPTIM5EN
|
|
description: LPTIM5 Peripheral Clocks Enable
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: DAC2EN
|
|
description: DAC2 (containing one converter) peripheral clock enable
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: COMP12EN
|
|
description: COMP1/2 peripheral clock enable
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: VREFEN
|
|
description: VREF peripheral clock enable
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: RTCAPBEN
|
|
description: RTC APB Clock Enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: SAI4EN
|
|
description: SAI4 Peripheral Clocks Enable
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: DTSEN
|
|
description: Digital temperature sensor block enable
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
fieldset/APB4LPENR:
|
|
description: RCC APB4 Sleep Clock Register
|
|
fields:
|
|
- name: SYSCFGLPEN
|
|
description: SYSCFG peripheral clock enable during CSleep mode
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: LPUART1LPEN
|
|
description: LPUART1 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: SPI6LPEN
|
|
description: SPI6 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: I2C4LPEN
|
|
description: I2C4 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: LPTIM2LPEN
|
|
description: LPTIM2 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: LPTIM3LPEN
|
|
description: LPTIM3 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: LPTIM4LPEN
|
|
description: LPTIM4 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: LPTIM5LPEN
|
|
description: LPTIM5 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: DAC2LPEN
|
|
description: DAC2 (containing one converter) peripheral clock enable during CSleep mode
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: COMP12LPEN
|
|
description: COMP1/2 peripheral clock enable during CSleep mode
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: VREFLPEN
|
|
description: VREF peripheral clock enable during CSleep mode
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: RTCAPBLPEN
|
|
description: RTC APB Clock Enable During CSleep Mode
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: SAI4LPEN
|
|
description: SAI4 Peripheral Clocks Enable During CSleep Mode
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: DTSLPEN
|
|
description: Digital temperature sensor block enable during CSleep Mode
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
fieldset/APB4RSTR:
|
|
description: RCC APB4 Peripheral Reset Register
|
|
fields:
|
|
- name: SYSCFGRST
|
|
description: SYSCFG block reset
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: LPUART1RST
|
|
description: LPUART1 block reset
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: SPI6RST
|
|
description: SPI6 block reset
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: I2C4RST
|
|
description: I2C4 block reset
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: LPTIM2RST
|
|
description: LPTIM2 block reset
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: LPTIM3RST
|
|
description: LPTIM3 block reset
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: LPTIM4RST
|
|
description: LPTIM4 block reset
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: LPTIM5RST
|
|
description: LPTIM5 block reset
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: DAC2RST
|
|
description: DAC2 (containing one converter) reset
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: COMP12RST
|
|
description: COMP12 Blocks Reset
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: VREFRST
|
|
description: VREF block reset
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: SAI4RST
|
|
description: SAI4 block reset
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: DTSRST
|
|
description: Digital temperature sensor block reset
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
fieldset/BDCR:
|
|
description: RCC Backup Domain Control Register
|
|
fields:
|
|
- name: LSEON
|
|
description: LSE oscillator enabled
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDY
|
|
description: LSE oscillator ready
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: LSEBYP
|
|
description: LSE oscillator bypass
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: LSEDRV
|
|
description: LSE oscillator driving capability
|
|
bit_offset: 3
|
|
bit_size: 2
|
|
enum: LSEDRV
|
|
- name: LSECSSON
|
|
description: LSE clock security system enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: LSECSSD
|
|
description: LSE clock security system failure detection
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: RTCSEL
|
|
description: RTC clock source selection
|
|
bit_offset: 8
|
|
bit_size: 2
|
|
enum: RTCSEL
|
|
- name: RTCEN
|
|
description: RTC clock enable
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: BDRST
|
|
description: VSwitch domain software reset
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
fieldset/CFGR:
|
|
description: RCC Clock Configuration Register
|
|
fields:
|
|
- name: SW
|
|
description: System clock switch
|
|
bit_offset: 0
|
|
bit_size: 3
|
|
enum: SW
|
|
- name: SWS
|
|
description: System clock switch status
|
|
bit_offset: 3
|
|
bit_size: 3
|
|
enum: SW
|
|
- name: STOPWUCK
|
|
description: System clock selection after a wake up from system Stop
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: STOPWUCK
|
|
- name: STOPKERWUCK
|
|
description: Kernel clock selection after a wake up from system Stop
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: STOPWUCK
|
|
- name: RTCPRE
|
|
description: HSE division factor for RTC clock
|
|
bit_offset: 8
|
|
bit_size: 6
|
|
- name: HRTIMSEL
|
|
description: High Resolution Timer clock prescaler selection
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: HRTIMSEL
|
|
- name: TIMPRE
|
|
description: Timers clocks prescaler selection
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: TIMPRE
|
|
- name: MCO1PRE
|
|
description: MCO1 prescaler
|
|
bit_offset: 18
|
|
bit_size: 4
|
|
enum: MCOPRE
|
|
- name: MCO1SEL
|
|
description: Micro-controller clock output 1
|
|
bit_offset: 22
|
|
bit_size: 3
|
|
enum: MCO1SEL
|
|
- name: MCO2PRE
|
|
description: MCO2 prescaler
|
|
bit_offset: 25
|
|
bit_size: 4
|
|
enum: MCOPRE
|
|
- name: MCO2SEL
|
|
description: Micro-controller clock output 2
|
|
bit_offset: 29
|
|
bit_size: 3
|
|
enum: MCO2SEL
|
|
fieldset/CICR:
|
|
description: RCC Clock Source Interrupt Clear Register
|
|
fields:
|
|
- name: LSIRDYC
|
|
description: LSI ready Interrupt Clear
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYC
|
|
description: LSE ready Interrupt Clear
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: HSIRDYC
|
|
description: HSI ready Interrupt Clear
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSERDYC
|
|
description: HSE ready Interrupt Clear
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: HSE_ready_Interrupt_Clear
|
|
description: CSI ready Interrupt Clear
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: HSI48RDYC
|
|
description: RC48 ready Interrupt Clear
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: PLLRDYC
|
|
description: PLL1 ready Interrupt Clear
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
array:
|
|
len: 3
|
|
stride: 1
|
|
- name: LSECSSC
|
|
description: LSE clock security system Interrupt Clear
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HSECSSC
|
|
description: HSE clock security system Interrupt Clear
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
fieldset/CIER:
|
|
description: RCC Clock Source Interrupt Enable Register
|
|
fields:
|
|
- name: LSIRDYIE
|
|
description: LSI ready Interrupt Enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYIE
|
|
description: LSE ready Interrupt Enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: HSIRDYIE
|
|
description: HSI ready Interrupt Enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSERDYIE
|
|
description: HSE ready Interrupt Enable
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: CSIRDYIE
|
|
description: CSI ready Interrupt Enable
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: HSI48RDYIE
|
|
description: RC48 ready Interrupt Enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: PLLRDYIE
|
|
description: PLL1 ready Interrupt Enable
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
array:
|
|
len: 3
|
|
stride: 1
|
|
- name: LSECSSIE
|
|
description: LSE clock security system Interrupt Enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
fieldset/CIFR:
|
|
description: RCC Clock Source Interrupt Flag Register
|
|
fields:
|
|
- name: LSIRDYF
|
|
description: LSI ready Interrupt Flag
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYF
|
|
description: LSE ready Interrupt Flag
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: HSIRDYF
|
|
description: HSI ready Interrupt Flag
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSERDYF
|
|
description: HSE ready Interrupt Flag
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: CSIRDY
|
|
description: CSI ready Interrupt Flag
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: HSI48RDYF
|
|
description: RC48 ready Interrupt Flag
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: PLLRDYF
|
|
description: PLL1 ready Interrupt Flag
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
array:
|
|
len: 3
|
|
stride: 1
|
|
- name: LSECSSF
|
|
description: LSE clock security system Interrupt Flag
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HSECSSF
|
|
description: HSE clock security system Interrupt Flag
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
fieldset/CR:
|
|
description: clock control register
|
|
fields:
|
|
- name: HSION
|
|
description: Internal high-speed clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: HSIKERON
|
|
description: High Speed Internal clock enable in Stop mode
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: HSIRDY
|
|
description: HSI clock ready flag
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSIDIV
|
|
description: HSI clock divider
|
|
bit_offset: 3
|
|
bit_size: 2
|
|
enum: HSIDIV
|
|
- name: HSIDIVF
|
|
description: HSI divider flag
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: CSION
|
|
description: CSI clock enable
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: CSIRDY
|
|
description: CSI clock ready flag
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: CSIKERON
|
|
description: CSI clock enable in Stop mode
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HSI48ON
|
|
description: RC48 clock enable
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: HSI48RDY
|
|
description: RC48 clock ready flag
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: D1CKRDY
|
|
description: D1 domain clocks ready flag
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: D2CKRDY
|
|
description: D2 domain clocks ready flag
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: HSEON
|
|
description: HSE clock enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: HSERDY
|
|
description: HSE clock ready flag
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: HSEBYP
|
|
description: HSE clock bypass
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: HSECSSON
|
|
description: HSE Clock Security System enable
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: PLLON
|
|
description: PLL1 enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
array:
|
|
len: 3
|
|
stride: 2
|
|
- name: PLLRDY
|
|
description: PLL1 clock ready flag
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
array:
|
|
len: 3
|
|
stride: 2
|
|
fieldset/CRRCR:
|
|
description: RCC Clock Recovery RC Register
|
|
fields:
|
|
- name: HSI48CAL
|
|
description: Internal RC 48 MHz clock calibration
|
|
bit_offset: 0
|
|
bit_size: 10
|
|
fieldset/CSICFGR:
|
|
description: RCC CSI configuration register
|
|
fields:
|
|
- name: CSICAL
|
|
description: CSI clock calibration
|
|
bit_offset: 0
|
|
bit_size: 9
|
|
- name: CSITRIM
|
|
description: CSI clock trimming
|
|
bit_offset: 24
|
|
bit_size: 6
|
|
fieldset/CSR:
|
|
description: RCC Clock Control and Status Register
|
|
fields:
|
|
- name: LSION
|
|
description: LSI oscillator enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSIRDY
|
|
description: LSI oscillator ready
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
fieldset/D1CCIPR:
|
|
description: RCC Domain 1 Kernel Clock Configuration Register
|
|
fields:
|
|
- name: FMCSEL
|
|
description: FMC kernel clock source selection
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
enum: FMCSEL
|
|
- name: OCTOSPISEL
|
|
description: OCTOSPI kernel clock source selection
|
|
bit_offset: 4
|
|
bit_size: 2
|
|
enum: FMCSEL
|
|
- name: DSISEL
|
|
description: kernel clock source selection
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: SDMMCSEL
|
|
description: SDMMC kernel clock source selection
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: SDMMCSEL
|
|
- name: CKPERSEL
|
|
description: per_ck clock source selection
|
|
bit_offset: 28
|
|
bit_size: 2
|
|
enum: CKPERSEL
|
|
fieldset/D1CFGR:
|
|
description: RCC Domain 1 Clock Configuration Register
|
|
fields:
|
|
- name: HPRE
|
|
description: D1 domain AHB prescaler
|
|
bit_offset: 0
|
|
bit_size: 4
|
|
enum: HPRE
|
|
- name: D1PPRE
|
|
description: D1 domain APB3 prescaler
|
|
bit_offset: 4
|
|
bit_size: 3
|
|
enum: PPRE
|
|
- name: D1CPRE
|
|
description: D1 domain Core prescaler
|
|
bit_offset: 8
|
|
bit_size: 4
|
|
enum: HPRE
|
|
fieldset/D2CCIP1R:
|
|
description: RCC Domain 2 Kernel Clock Configuration Register
|
|
fields:
|
|
- name: SAI1SEL
|
|
description: SAI1 and DFSDM1 kernel Aclk clock source selection
|
|
bit_offset: 0
|
|
bit_size: 3
|
|
enum: SAISEL
|
|
- name: SAI2ASEL
|
|
description: SAI2 kernel clock source A source selection
|
|
bit_offset: 6
|
|
bit_size: 3
|
|
enum: SAIASEL
|
|
- name: SAI2BSEL
|
|
description: SAI2 kernel clock source B source selection
|
|
bit_offset: 9
|
|
bit_size: 3
|
|
enum: SAIASEL
|
|
- name: SPI123SEL
|
|
description: SPI/I2S1,2 and 3 kernel clock source selection
|
|
bit_offset: 12
|
|
bit_size: 3
|
|
enum: SAISEL
|
|
- name: SPI45SEL
|
|
description: SPI4 and 5 kernel clock source selection
|
|
bit_offset: 16
|
|
bit_size: 3
|
|
enum: SPI45SEL
|
|
- name: SPDIFRXSEL
|
|
description: SPDIFRX kernel clock source selection
|
|
bit_offset: 20
|
|
bit_size: 2
|
|
enum: SPDIFRXSEL
|
|
- name: DFSDM1SEL
|
|
description: DFSDM1 kernel Clk clock source selection
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: DFSDMSEL
|
|
- name: FDCANSEL
|
|
description: FDCAN kernel clock source selection
|
|
bit_offset: 28
|
|
bit_size: 2
|
|
enum: FDCANSEL
|
|
- name: SWPSEL
|
|
description: SWPMI kernel clock source selection
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: SWPSEL
|
|
fieldset/D2CCIP2R:
|
|
description: RCC Domain 2 Kernel Clock Configuration Register
|
|
fields:
|
|
- name: USART234578SEL
|
|
description: USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection
|
|
bit_offset: 0
|
|
bit_size: 3
|
|
enum: USART234578SEL
|
|
- name: USART16910SEL
|
|
description: USART1, 6, 9 and 10 kernel clock source selection
|
|
bit_offset: 3
|
|
bit_size: 3
|
|
enum: USART16910SEL
|
|
- name: RNGSEL
|
|
description: RNG kernel clock source selection
|
|
bit_offset: 8
|
|
bit_size: 2
|
|
enum: RNGSEL
|
|
- name: I2C1235SEL
|
|
description: I2C1,2,3 kernel clock source selection
|
|
bit_offset: 12
|
|
bit_size: 2
|
|
enum: I2C1235SEL
|
|
- name: USBSEL
|
|
description: USBOTG 1 and 2 kernel clock source selection
|
|
bit_offset: 20
|
|
bit_size: 2
|
|
enum: USBSEL
|
|
- name: CECSEL
|
|
description: HDMI-CEC kernel clock source selection
|
|
bit_offset: 22
|
|
bit_size: 2
|
|
enum: CECSEL
|
|
- name: LPTIM1SEL
|
|
description: LPTIM1 kernel clock source selection
|
|
bit_offset: 28
|
|
bit_size: 3
|
|
enum: LPTIM1SEL
|
|
fieldset/D2CFGR:
|
|
description: RCC Domain 2 Clock Configuration Register
|
|
fields:
|
|
- name: D2PPRE1
|
|
description: D2 domain APB1 prescaler
|
|
bit_offset: 4
|
|
bit_size: 3
|
|
enum: PPRE
|
|
- name: D2PPRE2
|
|
description: D2 domain APB2 prescaler
|
|
bit_offset: 8
|
|
bit_size: 3
|
|
enum: PPRE
|
|
fieldset/D3AMR:
|
|
description: RCC D3 Autonomous mode Register
|
|
fields:
|
|
- name: BDMA2AMEN
|
|
description: BDMA2 and DMAMUX Autonomous mode enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: BDMAAMEN
|
|
description: BDMA and DMAMUX Autonomous mode enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LPUART1AMEN
|
|
description: LPUART1 Autonomous mode enable
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: SPI6AMEN
|
|
description: SPI6 Autonomous mode enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: I2C4AMEN
|
|
description: I2C4 Autonomous mode enable
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: LPTIM2AMEN
|
|
description: LPTIM2 Autonomous mode enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: LPTIM3AMEN
|
|
description: LPTIM3 Autonomous mode enable
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: LPTIM4AMEN
|
|
description: LPTIM4 Autonomous mode enable
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: LPTIM5AMEN
|
|
description: LPTIM5 Autonomous mode enable
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: DAC2AMEN
|
|
description: DAC2 (containing one converter) Autonomous mode enable
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: COMP12AMEN
|
|
description: COMP12 Autonomous mode enable
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: VREFAMEN
|
|
description: VREF Autonomous mode enable
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: RTCAMEN
|
|
description: RTC Autonomous mode enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: CRCAMEN
|
|
description: CRC Autonomous mode enable
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: SAI4AMEN
|
|
description: SAI4 Autonomous mode enable
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: ADC3AMEN
|
|
description: ADC3 Autonomous mode enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: DTSAMEN
|
|
description: Digital temperature sensor Autonomous mode enable
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: BKPSRAMAMEN
|
|
description: Backup RAM Autonomous mode enable
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: SRAM4AMEN
|
|
description: SRAM4 Autonomous mode enable
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
fieldset/D3CCIPR:
|
|
description: RCC Domain 3 Kernel Clock Configuration Register
|
|
fields:
|
|
- name: LPUART1SEL
|
|
description: LPUART1 kernel clock source selection
|
|
bit_offset: 0
|
|
bit_size: 3
|
|
enum: LPUARTSEL
|
|
- name: I2C4SEL
|
|
description: I2C4 kernel clock source selection
|
|
bit_offset: 8
|
|
bit_size: 2
|
|
enum: I2C4SEL
|
|
- name: LPTIM2SEL
|
|
description: LPTIM2 kernel clock source selection
|
|
bit_offset: 10
|
|
bit_size: 3
|
|
enum: LPTIM2SEL
|
|
- name: LPTIM345SEL
|
|
description: LPTIM3,4,5 kernel clock source selection
|
|
bit_offset: 13
|
|
bit_size: 3
|
|
enum: LPTIM2SEL
|
|
- name: ADCSEL
|
|
description: SAR ADC kernel clock source selection
|
|
bit_offset: 16
|
|
bit_size: 2
|
|
enum: ADCSEL
|
|
- name: DFSDM2SEL
|
|
description: DFSDM2 kernel clock source selection
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: SPI6SEL
|
|
description: SPI6 kernel clock source selection
|
|
bit_offset: 28
|
|
bit_size: 3
|
|
enum: SPI6SEL
|
|
fieldset/D3CFGR:
|
|
description: RCC Domain 3 Clock Configuration Register
|
|
fields:
|
|
- name: D3PPRE
|
|
description: D3 domain APB4 prescaler
|
|
bit_offset: 4
|
|
bit_size: 3
|
|
enum: PPRE
|
|
fieldset/GCR:
|
|
description: Global Control Register
|
|
fields:
|
|
- name: WW1RSC
|
|
description: WWDG1 reset scope control
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
fieldset/HSICFGR:
|
|
description: RCC HSI configuration register
|
|
fields:
|
|
- name: HSICAL
|
|
description: HSI clock calibration
|
|
bit_offset: 0
|
|
bit_size: 12
|
|
- name: HSITRIM
|
|
description: HSI clock trimming
|
|
bit_offset: 24
|
|
bit_size: 7
|
|
fieldset/PLLCFGR:
|
|
description: RCC PLLs Configuration Register
|
|
fields:
|
|
- name: PLLFRACEN
|
|
description: PLL1 fractional latch enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
array:
|
|
len: 3
|
|
stride: 4
|
|
- name: PLLVCOSEL
|
|
description: PLL1 VCO selection
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
array:
|
|
len: 3
|
|
stride: 4
|
|
enum: PLLVCOSEL
|
|
- name: PLLRGE
|
|
description: PLL1 input frequency range
|
|
bit_offset: 2
|
|
bit_size: 2
|
|
array:
|
|
len: 3
|
|
stride: 4
|
|
enum: PLLRGE
|
|
- name: DIVPEN
|
|
description: PLL1 DIVP divider output enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
array:
|
|
len: 3
|
|
stride: 3
|
|
- name: DIVQEN
|
|
description: PLL1 DIVQ divider output enable
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
array:
|
|
len: 3
|
|
stride: 3
|
|
- name: DIVREN
|
|
description: PLL1 DIVR divider output enable
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
array:
|
|
len: 3
|
|
stride: 3
|
|
fieldset/PLLCKSELR:
|
|
description: RCC PLLs Clock Source Selection Register
|
|
fields:
|
|
- name: PLLSRC
|
|
description: DIVMx and PLLs clock source selection
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
enum: PLLSRC
|
|
- name: DIVM
|
|
description: Prescaler for PLL1
|
|
bit_offset: 4
|
|
bit_size: 6
|
|
array:
|
|
len: 3
|
|
stride: 8
|
|
enum: PLLM
|
|
fieldset/PLLDIVR:
|
|
description: RCC PLL1 Dividers Configuration Register
|
|
fields:
|
|
- name: PLLN
|
|
description: Multiplication factor for PLL1 VCO
|
|
bit_offset: 0
|
|
bit_size: 9
|
|
enum: PLLN
|
|
- name: PLLP
|
|
description: PLL DIVP division factor
|
|
bit_offset: 9
|
|
bit_size: 7
|
|
enum: PLLDIV
|
|
- name: PLLQ
|
|
description: PLL DIVQ division factor
|
|
bit_offset: 16
|
|
bit_size: 7
|
|
enum: PLLDIV
|
|
- name: PLLR
|
|
description: PLL DIVR division factor
|
|
bit_offset: 24
|
|
bit_size: 7
|
|
enum: PLLDIV
|
|
fieldset/PLLFRACR:
|
|
description: RCC PLL Fractional Divider Register
|
|
fields:
|
|
- name: FRACN
|
|
description: Fractional part of the multiplication factor for PLL VCO
|
|
bit_offset: 3
|
|
bit_size: 13
|
|
fieldset/RSR:
|
|
description: RCC Reset Status Register
|
|
fields:
|
|
- name: RMVF
|
|
description: Remove reset flag
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: CPURSTF
|
|
description: CPU reset flag
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: D1RSTF
|
|
description: D1 domain power switch reset flag
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: D2RSTF
|
|
description: D2 domain power switch reset flag
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: BORRSTF
|
|
description: BOR reset flag
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: PINRSTF
|
|
description: Pin reset flag (NRST)
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: PORRSTF
|
|
description: POR/PDR reset flag
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: SFTRSTF
|
|
description: System reset from CPU reset flag
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: IWDG1RSTF
|
|
description: Independent Watchdog reset flag
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: WWDG1RSTF
|
|
description: Window Watchdog reset flag
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: LPWRRSTF
|
|
description: Reset due to illegal D1 DStandby or CPU CStop flag
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum/ADCSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: PLL2_P
|
|
description: pll2_p selected as peripheral clock
|
|
value: 0
|
|
- name: PLL3_R
|
|
description: pll3_r selected as peripheral clock
|
|
value: 1
|
|
- name: PER
|
|
description: PER selected as peripheral clock
|
|
value: 2
|
|
enum/CECSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: LSE
|
|
description: LSE selected as peripheral clock
|
|
value: 0
|
|
- name: LSI
|
|
description: LSI selected as peripheral clock
|
|
value: 1
|
|
- name: CSI
|
|
description: csi_ker selected as peripheral clock
|
|
value: 2
|
|
enum/CKPERSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: HSI
|
|
description: HSI selected as peripheral clock
|
|
value: 0
|
|
- name: CSI
|
|
description: CSI selected as peripheral clock
|
|
value: 1
|
|
- name: HSE
|
|
description: HSE selected as peripheral clock
|
|
value: 2
|
|
enum/DFSDMSEL:
|
|
bit_size: 1
|
|
variants:
|
|
- name: APB2
|
|
description: rcc_pclk2 selected as peripheral clock
|
|
value: 0
|
|
- name: SYS
|
|
description: System clock selected as peripheral clock
|
|
value: 1
|
|
enum/FDCANSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: HSE
|
|
description: HSE selected as peripheral clock
|
|
value: 0
|
|
- name: PLL1_Q
|
|
description: pll1_q selected as peripheral clock
|
|
value: 1
|
|
- name: PLL2_Q
|
|
description: pll2_q selected as peripheral clock
|
|
value: 2
|
|
enum/FMCSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: AHB3
|
|
description: rcc_hclk3 selected as peripheral clock
|
|
value: 0
|
|
- name: PLL1_Q
|
|
description: pll1_q selected as peripheral clock
|
|
value: 1
|
|
- name: PLL2_R
|
|
description: pll2_r selected as peripheral clock
|
|
value: 2
|
|
- name: PER
|
|
description: PER selected as peripheral clock
|
|
value: 3
|
|
enum/HPRE:
|
|
bit_size: 4
|
|
variants:
|
|
- name: Div1
|
|
description: sys_ck not divided
|
|
value: 0
|
|
- name: Div2
|
|
description: sys_ck divided by 2
|
|
value: 8
|
|
- name: Div4
|
|
description: sys_ck divided by 4
|
|
value: 9
|
|
- name: Div8
|
|
description: sys_ck divided by 8
|
|
value: 10
|
|
- name: Div16
|
|
description: sys_ck divided by 16
|
|
value: 11
|
|
- name: Div64
|
|
description: sys_ck divided by 64
|
|
value: 12
|
|
- name: Div128
|
|
description: sys_ck divided by 128
|
|
value: 13
|
|
- name: Div256
|
|
description: sys_ck divided by 256
|
|
value: 14
|
|
- name: Div512
|
|
description: sys_ck divided by 512
|
|
value: 15
|
|
enum/HRTIMSEL:
|
|
bit_size: 1
|
|
variants:
|
|
- name: TIMY_KER
|
|
description: The HRTIM prescaler clock source is the same as other timers (rcc_timy_ker_ck)
|
|
value: 0
|
|
- name: C_CK
|
|
description: The HRTIM prescaler clock source is the CPU clock (c_ck)
|
|
value: 1
|
|
enum/HSIDIV:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Div1
|
|
description: No division
|
|
value: 0
|
|
- name: Div2
|
|
description: Division by 2
|
|
value: 1
|
|
- name: Div4
|
|
description: Division by 4
|
|
value: 2
|
|
- name: Div8
|
|
description: Division by 8
|
|
value: 3
|
|
enum/I2C1235SEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: APB1
|
|
description: rcc_pclk1 selected as peripheral clock
|
|
value: 0
|
|
- name: PLL3_R
|
|
description: pll3_r selected as peripheral clock
|
|
value: 1
|
|
- name: HSI
|
|
description: hsi_ker selected as peripheral clock
|
|
value: 2
|
|
- name: CSI
|
|
description: csi_ker selected as peripheral clock
|
|
value: 3
|
|
enum/I2C4SEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: APB4
|
|
description: rcc_pclk4 selected as peripheral clock
|
|
value: 0
|
|
- name: PLL3_R
|
|
description: pll3_r selected as peripheral clock
|
|
value: 1
|
|
- name: HSI
|
|
description: hsi_ker selected as peripheral clock
|
|
value: 2
|
|
- name: CSI
|
|
description: csi_ker selected as peripheral clock
|
|
value: 3
|
|
enum/LPTIM1SEL:
|
|
bit_size: 3
|
|
variants:
|
|
- name: APB1
|
|
description: rcc_pclk1 selected as peripheral clock
|
|
value: 0
|
|
- name: PLL2_P
|
|
description: pll2_p selected as peripheral clock
|
|
value: 1
|
|
- name: PLL3_R
|
|
description: pll3_r selected as peripheral clock
|
|
value: 2
|
|
- name: LSE
|
|
description: LSE selected as peripheral clock
|
|
value: 3
|
|
- name: LSI
|
|
description: LSI selected as peripheral clock
|
|
value: 4
|
|
- name: PER
|
|
description: PER selected as peripheral clock
|
|
value: 5
|
|
enum/LPTIM2SEL:
|
|
bit_size: 3
|
|
variants:
|
|
- name: APB4
|
|
description: rcc_pclk4 selected as peripheral clock
|
|
value: 0
|
|
- name: PLL2_P
|
|
description: pll2_p selected as peripheral clock
|
|
value: 1
|
|
- name: PLL3_R
|
|
description: pll3_r selected as peripheral clock
|
|
value: 2
|
|
- name: LSE
|
|
description: LSE selected as peripheral clock
|
|
value: 3
|
|
- name: LSI
|
|
description: LSI selected as peripheral clock
|
|
value: 4
|
|
- name: PER
|
|
description: PER selected as peripheral clock
|
|
value: 5
|
|
enum/LPUARTSEL:
|
|
bit_size: 3
|
|
variants:
|
|
- name: RCC_PCLK_D3
|
|
description: rcc_pclk_d3 selected as peripheral clock
|
|
value: 0
|
|
- name: PLL2_Q
|
|
description: pll2_q selected as peripheral clock
|
|
value: 1
|
|
- name: PLL3_Q
|
|
description: pll3_q selected as peripheral clock
|
|
value: 2
|
|
- name: HSI
|
|
description: hsi_ker selected as peripheral clock
|
|
value: 3
|
|
- name: CSI
|
|
description: csi_ker selected as peripheral clock
|
|
value: 4
|
|
- name: LSE
|
|
description: LSE selected as peripheral clock
|
|
value: 5
|
|
enum/LSEDRV:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Low
|
|
description: Low driving capability
|
|
value: 0
|
|
- name: MediumLow
|
|
description: Medium low driving capability
|
|
value: 1
|
|
- name: MediumHigh
|
|
description: Medium high driving capability
|
|
value: 2
|
|
- name: High
|
|
description: High driving capability
|
|
value: 3
|
|
enum/MCO1SEL:
|
|
bit_size: 3
|
|
variants:
|
|
- name: HSI
|
|
description: HSI selected for micro-controller clock output
|
|
value: 0
|
|
- name: LSE
|
|
description: LSE selected for micro-controller clock output
|
|
value: 1
|
|
- name: HSE
|
|
description: HSE selected for micro-controller clock output
|
|
value: 2
|
|
- name: PLL1_Q
|
|
description: pll1_q selected for micro-controller clock output
|
|
value: 3
|
|
- name: HSI48
|
|
description: HSI48 selected for micro-controller clock output
|
|
value: 4
|
|
enum/MCO2SEL:
|
|
bit_size: 3
|
|
variants:
|
|
- name: SYSCLK
|
|
description: System clock selected for micro-controller clock output
|
|
value: 0
|
|
- name: PLL2_P
|
|
description: pll2_p selected for micro-controller clock output
|
|
value: 1
|
|
- name: HSE
|
|
description: HSE selected for micro-controller clock output
|
|
value: 2
|
|
- name: PLL1_P
|
|
description: pll1_p selected for micro-controller clock output
|
|
value: 3
|
|
- name: CSI
|
|
description: CSI selected for micro-controller clock output
|
|
value: 4
|
|
- name: LSI
|
|
description: LSI selected for micro-controller clock output
|
|
value: 5
|
|
enum/MCOPRE:
|
|
bit_size: 4
|
|
variants:
|
|
- name: Div1
|
|
description: Divide by 1
|
|
value: 1
|
|
- name: Div2
|
|
description: Divide by 2
|
|
value: 2
|
|
- name: Div3
|
|
description: Divide by 3
|
|
value: 3
|
|
- name: Div4
|
|
description: Divide by 4
|
|
value: 4
|
|
- name: Div5
|
|
description: Divide by 5
|
|
value: 5
|
|
- name: Div6
|
|
description: Divide by 6
|
|
value: 6
|
|
- name: Div7
|
|
description: Divide by 7
|
|
value: 7
|
|
- name: Div8
|
|
description: Divide by 8
|
|
value: 8
|
|
- name: Div9
|
|
description: Divide by 9
|
|
value: 9
|
|
- name: Div10
|
|
description: Divide by 10
|
|
value: 10
|
|
- name: Div11
|
|
description: Divide by 11
|
|
value: 11
|
|
- name: Div12
|
|
description: Divide by 12
|
|
value: 12
|
|
- name: Div13
|
|
description: Divide by 13
|
|
value: 13
|
|
- name: Div14
|
|
description: Divide by 14
|
|
value: 14
|
|
- name: Div15
|
|
description: Divide by 15
|
|
value: 15
|
|
enum/PLLDIV:
|
|
bit_size: 7
|
|
variants:
|
|
- name: Div1
|
|
value: 0
|
|
- name: Div2
|
|
value: 1
|
|
- name: Div3
|
|
value: 2
|
|
- name: Div4
|
|
value: 3
|
|
- name: Div5
|
|
value: 4
|
|
- name: Div6
|
|
value: 5
|
|
- name: Div7
|
|
value: 6
|
|
- name: Div8
|
|
value: 7
|
|
- name: Div9
|
|
value: 8
|
|
- name: Div10
|
|
value: 9
|
|
- name: Div11
|
|
value: 10
|
|
- name: Div12
|
|
value: 11
|
|
- name: Div13
|
|
value: 12
|
|
- name: Div14
|
|
value: 13
|
|
- name: Div15
|
|
value: 14
|
|
- name: Div16
|
|
value: 15
|
|
- name: Div17
|
|
value: 16
|
|
- name: Div18
|
|
value: 17
|
|
- name: Div19
|
|
value: 18
|
|
- name: Div20
|
|
value: 19
|
|
- name: Div21
|
|
value: 20
|
|
- name: Div22
|
|
value: 21
|
|
- name: Div23
|
|
value: 22
|
|
- name: Div24
|
|
value: 23
|
|
- name: Div25
|
|
value: 24
|
|
- name: Div26
|
|
value: 25
|
|
- name: Div27
|
|
value: 26
|
|
- name: Div28
|
|
value: 27
|
|
- name: Div29
|
|
value: 28
|
|
- name: Div30
|
|
value: 29
|
|
- name: Div31
|
|
value: 30
|
|
- name: Div32
|
|
value: 31
|
|
- name: Div33
|
|
value: 32
|
|
- name: Div34
|
|
value: 33
|
|
- name: Div35
|
|
value: 34
|
|
- name: Div36
|
|
value: 35
|
|
- name: Div37
|
|
value: 36
|
|
- name: Div38
|
|
value: 37
|
|
- name: Div39
|
|
value: 38
|
|
- name: Div40
|
|
value: 39
|
|
- name: Div41
|
|
value: 40
|
|
- name: Div42
|
|
value: 41
|
|
- name: Div43
|
|
value: 42
|
|
- name: Div44
|
|
value: 43
|
|
- name: Div45
|
|
value: 44
|
|
- name: Div46
|
|
value: 45
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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bit_size: 6
|
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variants:
|
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|
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|
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|
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|
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|
|
value: 196
|
|
- name: Mul198
|
|
value: 197
|
|
- name: Mul199
|
|
value: 198
|
|
- name: Mul200
|
|
value: 199
|
|
- name: Mul201
|
|
value: 200
|
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- name: Mul202
|
|
value: 201
|
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- name: Mul203
|
|
value: 202
|
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- name: Mul204
|
|
value: 203
|
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- name: Mul205
|
|
value: 204
|
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- name: Mul206
|
|
value: 205
|
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- name: Mul207
|
|
value: 206
|
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- name: Mul208
|
|
value: 207
|
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- name: Mul209
|
|
value: 208
|
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- name: Mul210
|
|
value: 209
|
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- name: Mul211
|
|
value: 210
|
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- name: Mul212
|
|
value: 211
|
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- name: Mul213
|
|
value: 212
|
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- name: Mul214
|
|
value: 213
|
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- name: Mul215
|
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value: 214
|
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- name: Mul216
|
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value: 215
|
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- name: Mul217
|
|
value: 216
|
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- name: Mul218
|
|
value: 217
|
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- name: Mul219
|
|
value: 218
|
|
- name: Mul220
|
|
value: 219
|
|
- name: Mul221
|
|
value: 220
|
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- name: Mul222
|
|
value: 221
|
|
- name: Mul223
|
|
value: 222
|
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- name: Mul224
|
|
value: 223
|
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- name: Mul225
|
|
value: 224
|
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- name: Mul226
|
|
value: 225
|
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- name: Mul227
|
|
value: 226
|
|
- name: Mul228
|
|
value: 227
|
|
- name: Mul229
|
|
value: 228
|
|
- name: Mul230
|
|
value: 229
|
|
- name: Mul231
|
|
value: 230
|
|
- name: Mul232
|
|
value: 231
|
|
- name: Mul233
|
|
value: 232
|
|
- name: Mul234
|
|
value: 233
|
|
- name: Mul235
|
|
value: 234
|
|
- name: Mul236
|
|
value: 235
|
|
- name: Mul237
|
|
value: 236
|
|
- name: Mul238
|
|
value: 237
|
|
- name: Mul239
|
|
value: 238
|
|
- name: Mul240
|
|
value: 239
|
|
- name: Mul241
|
|
value: 240
|
|
- name: Mul242
|
|
value: 241
|
|
- name: Mul243
|
|
value: 242
|
|
- name: Mul244
|
|
value: 243
|
|
- name: Mul245
|
|
value: 244
|
|
- name: Mul246
|
|
value: 245
|
|
- name: Mul247
|
|
value: 246
|
|
- name: Mul248
|
|
value: 247
|
|
- name: Mul249
|
|
value: 248
|
|
- name: Mul250
|
|
value: 249
|
|
- name: Mul251
|
|
value: 250
|
|
- name: Mul252
|
|
value: 251
|
|
- name: Mul253
|
|
value: 252
|
|
- name: Mul254
|
|
value: 253
|
|
- name: Mul255
|
|
value: 254
|
|
- name: Mul256
|
|
value: 255
|
|
- name: Mul257
|
|
value: 256
|
|
- name: Mul258
|
|
value: 257
|
|
- name: Mul259
|
|
value: 258
|
|
- name: Mul260
|
|
value: 259
|
|
- name: Mul261
|
|
value: 260
|
|
- name: Mul262
|
|
value: 261
|
|
- name: Mul263
|
|
value: 262
|
|
- name: Mul264
|
|
value: 263
|
|
- name: Mul265
|
|
value: 264
|
|
- name: Mul266
|
|
value: 265
|
|
- name: Mul267
|
|
value: 266
|
|
- name: Mul268
|
|
value: 267
|
|
- name: Mul269
|
|
value: 268
|
|
- name: Mul270
|
|
value: 269
|
|
- name: Mul271
|
|
value: 270
|
|
- name: Mul272
|
|
value: 271
|
|
- name: Mul273
|
|
value: 272
|
|
- name: Mul274
|
|
value: 273
|
|
- name: Mul275
|
|
value: 274
|
|
- name: Mul276
|
|
value: 275
|
|
- name: Mul277
|
|
value: 276
|
|
- name: Mul278
|
|
value: 277
|
|
- name: Mul279
|
|
value: 278
|
|
- name: Mul280
|
|
value: 279
|
|
- name: Mul281
|
|
value: 280
|
|
- name: Mul282
|
|
value: 281
|
|
- name: Mul283
|
|
value: 282
|
|
- name: Mul284
|
|
value: 283
|
|
- name: Mul285
|
|
value: 284
|
|
- name: Mul286
|
|
value: 285
|
|
- name: Mul287
|
|
value: 286
|
|
- name: Mul288
|
|
value: 287
|
|
- name: Mul289
|
|
value: 288
|
|
- name: Mul290
|
|
value: 289
|
|
- name: Mul291
|
|
value: 290
|
|
- name: Mul292
|
|
value: 291
|
|
- name: Mul293
|
|
value: 292
|
|
- name: Mul294
|
|
value: 293
|
|
- name: Mul295
|
|
value: 294
|
|
- name: Mul296
|
|
value: 295
|
|
- name: Mul297
|
|
value: 296
|
|
- name: Mul298
|
|
value: 297
|
|
- name: Mul299
|
|
value: 298
|
|
- name: Mul300
|
|
value: 299
|
|
- name: Mul301
|
|
value: 300
|
|
- name: Mul302
|
|
value: 301
|
|
- name: Mul303
|
|
value: 302
|
|
- name: Mul304
|
|
value: 303
|
|
- name: Mul305
|
|
value: 304
|
|
- name: Mul306
|
|
value: 305
|
|
- name: Mul307
|
|
value: 306
|
|
- name: Mul308
|
|
value: 307
|
|
- name: Mul309
|
|
value: 308
|
|
- name: Mul310
|
|
value: 309
|
|
- name: Mul311
|
|
value: 310
|
|
- name: Mul312
|
|
value: 311
|
|
- name: Mul313
|
|
value: 312
|
|
- name: Mul314
|
|
value: 313
|
|
- name: Mul315
|
|
value: 314
|
|
- name: Mul316
|
|
value: 315
|
|
- name: Mul317
|
|
value: 316
|
|
- name: Mul318
|
|
value: 317
|
|
- name: Mul319
|
|
value: 318
|
|
- name: Mul320
|
|
value: 319
|
|
- name: Mul321
|
|
value: 320
|
|
- name: Mul322
|
|
value: 321
|
|
- name: Mul323
|
|
value: 322
|
|
- name: Mul324
|
|
value: 323
|
|
- name: Mul325
|
|
value: 324
|
|
- name: Mul326
|
|
value: 325
|
|
- name: Mul327
|
|
value: 326
|
|
- name: Mul328
|
|
value: 327
|
|
- name: Mul329
|
|
value: 328
|
|
- name: Mul330
|
|
value: 329
|
|
- name: Mul331
|
|
value: 330
|
|
- name: Mul332
|
|
value: 331
|
|
- name: Mul333
|
|
value: 332
|
|
- name: Mul334
|
|
value: 333
|
|
- name: Mul335
|
|
value: 334
|
|
- name: Mul336
|
|
value: 335
|
|
- name: Mul337
|
|
value: 336
|
|
- name: Mul338
|
|
value: 337
|
|
- name: Mul339
|
|
value: 338
|
|
- name: Mul340
|
|
value: 339
|
|
- name: Mul341
|
|
value: 340
|
|
- name: Mul342
|
|
value: 341
|
|
- name: Mul343
|
|
value: 342
|
|
- name: Mul344
|
|
value: 343
|
|
- name: Mul345
|
|
value: 344
|
|
- name: Mul346
|
|
value: 345
|
|
- name: Mul347
|
|
value: 346
|
|
- name: Mul348
|
|
value: 347
|
|
- name: Mul349
|
|
value: 348
|
|
- name: Mul350
|
|
value: 349
|
|
- name: Mul351
|
|
value: 350
|
|
- name: Mul352
|
|
value: 351
|
|
- name: Mul353
|
|
value: 352
|
|
- name: Mul354
|
|
value: 353
|
|
- name: Mul355
|
|
value: 354
|
|
- name: Mul356
|
|
value: 355
|
|
- name: Mul357
|
|
value: 356
|
|
- name: Mul358
|
|
value: 357
|
|
- name: Mul359
|
|
value: 358
|
|
- name: Mul360
|
|
value: 359
|
|
- name: Mul361
|
|
value: 360
|
|
- name: Mul362
|
|
value: 361
|
|
- name: Mul363
|
|
value: 362
|
|
- name: Mul364
|
|
value: 363
|
|
- name: Mul365
|
|
value: 364
|
|
- name: Mul366
|
|
value: 365
|
|
- name: Mul367
|
|
value: 366
|
|
- name: Mul368
|
|
value: 367
|
|
- name: Mul369
|
|
value: 368
|
|
- name: Mul370
|
|
value: 369
|
|
- name: Mul371
|
|
value: 370
|
|
- name: Mul372
|
|
value: 371
|
|
- name: Mul373
|
|
value: 372
|
|
- name: Mul374
|
|
value: 373
|
|
- name: Mul375
|
|
value: 374
|
|
- name: Mul376
|
|
value: 375
|
|
- name: Mul377
|
|
value: 376
|
|
- name: Mul378
|
|
value: 377
|
|
- name: Mul379
|
|
value: 378
|
|
- name: Mul380
|
|
value: 379
|
|
- name: Mul381
|
|
value: 380
|
|
- name: Mul382
|
|
value: 381
|
|
- name: Mul383
|
|
value: 382
|
|
- name: Mul384
|
|
value: 383
|
|
- name: Mul385
|
|
value: 384
|
|
- name: Mul386
|
|
value: 385
|
|
- name: Mul387
|
|
value: 386
|
|
- name: Mul388
|
|
value: 387
|
|
- name: Mul389
|
|
value: 388
|
|
- name: Mul390
|
|
value: 389
|
|
- name: Mul391
|
|
value: 390
|
|
- name: Mul392
|
|
value: 391
|
|
- name: Mul393
|
|
value: 392
|
|
- name: Mul394
|
|
value: 393
|
|
- name: Mul395
|
|
value: 394
|
|
- name: Mul396
|
|
value: 395
|
|
- name: Mul397
|
|
value: 396
|
|
- name: Mul398
|
|
value: 397
|
|
- name: Mul399
|
|
value: 398
|
|
- name: Mul400
|
|
value: 399
|
|
- name: Mul401
|
|
value: 400
|
|
- name: Mul402
|
|
value: 401
|
|
- name: Mul403
|
|
value: 402
|
|
- name: Mul404
|
|
value: 403
|
|
- name: Mul405
|
|
value: 404
|
|
- name: Mul406
|
|
value: 405
|
|
- name: Mul407
|
|
value: 406
|
|
- name: Mul408
|
|
value: 407
|
|
- name: Mul409
|
|
value: 408
|
|
- name: Mul410
|
|
value: 409
|
|
- name: Mul411
|
|
value: 410
|
|
- name: Mul412
|
|
value: 411
|
|
- name: Mul413
|
|
value: 412
|
|
- name: Mul414
|
|
value: 413
|
|
- name: Mul415
|
|
value: 414
|
|
- name: Mul416
|
|
value: 415
|
|
- name: Mul417
|
|
value: 416
|
|
- name: Mul418
|
|
value: 417
|
|
- name: Mul419
|
|
value: 418
|
|
- name: Mul420
|
|
value: 419
|
|
- name: Mul421
|
|
value: 420
|
|
- name: Mul422
|
|
value: 421
|
|
- name: Mul423
|
|
value: 422
|
|
- name: Mul424
|
|
value: 423
|
|
- name: Mul425
|
|
value: 424
|
|
- name: Mul426
|
|
value: 425
|
|
- name: Mul427
|
|
value: 426
|
|
- name: Mul428
|
|
value: 427
|
|
- name: Mul429
|
|
value: 428
|
|
- name: Mul430
|
|
value: 429
|
|
- name: Mul431
|
|
value: 430
|
|
- name: Mul432
|
|
value: 431
|
|
- name: Mul433
|
|
value: 432
|
|
- name: Mul434
|
|
value: 433
|
|
- name: Mul435
|
|
value: 434
|
|
- name: Mul436
|
|
value: 435
|
|
- name: Mul437
|
|
value: 436
|
|
- name: Mul438
|
|
value: 437
|
|
- name: Mul439
|
|
value: 438
|
|
- name: Mul440
|
|
value: 439
|
|
- name: Mul441
|
|
value: 440
|
|
- name: Mul442
|
|
value: 441
|
|
- name: Mul443
|
|
value: 442
|
|
- name: Mul444
|
|
value: 443
|
|
- name: Mul445
|
|
value: 444
|
|
- name: Mul446
|
|
value: 445
|
|
- name: Mul447
|
|
value: 446
|
|
- name: Mul448
|
|
value: 447
|
|
- name: Mul449
|
|
value: 448
|
|
- name: Mul450
|
|
value: 449
|
|
- name: Mul451
|
|
value: 450
|
|
- name: Mul452
|
|
value: 451
|
|
- name: Mul453
|
|
value: 452
|
|
- name: Mul454
|
|
value: 453
|
|
- name: Mul455
|
|
value: 454
|
|
- name: Mul456
|
|
value: 455
|
|
- name: Mul457
|
|
value: 456
|
|
- name: Mul458
|
|
value: 457
|
|
- name: Mul459
|
|
value: 458
|
|
- name: Mul460
|
|
value: 459
|
|
- name: Mul461
|
|
value: 460
|
|
- name: Mul462
|
|
value: 461
|
|
- name: Mul463
|
|
value: 462
|
|
- name: Mul464
|
|
value: 463
|
|
- name: Mul465
|
|
value: 464
|
|
- name: Mul466
|
|
value: 465
|
|
- name: Mul467
|
|
value: 466
|
|
- name: Mul468
|
|
value: 467
|
|
- name: Mul469
|
|
value: 468
|
|
- name: Mul470
|
|
value: 469
|
|
- name: Mul471
|
|
value: 470
|
|
- name: Mul472
|
|
value: 471
|
|
- name: Mul473
|
|
value: 472
|
|
- name: Mul474
|
|
value: 473
|
|
- name: Mul475
|
|
value: 474
|
|
- name: Mul476
|
|
value: 475
|
|
- name: Mul477
|
|
value: 476
|
|
- name: Mul478
|
|
value: 477
|
|
- name: Mul479
|
|
value: 478
|
|
- name: Mul480
|
|
value: 479
|
|
- name: Mul481
|
|
value: 480
|
|
- name: Mul482
|
|
value: 481
|
|
- name: Mul483
|
|
value: 482
|
|
- name: Mul484
|
|
value: 483
|
|
- name: Mul485
|
|
value: 484
|
|
- name: Mul486
|
|
value: 485
|
|
- name: Mul487
|
|
value: 486
|
|
- name: Mul488
|
|
value: 487
|
|
- name: Mul489
|
|
value: 488
|
|
- name: Mul490
|
|
value: 489
|
|
- name: Mul491
|
|
value: 490
|
|
- name: Mul492
|
|
value: 491
|
|
- name: Mul493
|
|
value: 492
|
|
- name: Mul494
|
|
value: 493
|
|
- name: Mul495
|
|
value: 494
|
|
- name: Mul496
|
|
value: 495
|
|
- name: Mul497
|
|
value: 496
|
|
- name: Mul498
|
|
value: 497
|
|
- name: Mul499
|
|
value: 498
|
|
- name: Mul500
|
|
value: 499
|
|
- name: Mul501
|
|
value: 500
|
|
- name: Mul502
|
|
value: 501
|
|
- name: Mul503
|
|
value: 502
|
|
- name: Mul504
|
|
value: 503
|
|
- name: Mul505
|
|
value: 504
|
|
- name: Mul506
|
|
value: 505
|
|
- name: Mul507
|
|
value: 506
|
|
- name: Mul508
|
|
value: 507
|
|
- name: Mul509
|
|
value: 508
|
|
- name: Mul510
|
|
value: 509
|
|
- name: Mul511
|
|
value: 510
|
|
- name: Mul512
|
|
value: 511
|
|
enum/PLLRGE:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Range1
|
|
description: Frequency is between 1 and 2 MHz
|
|
value: 0
|
|
- name: Range2
|
|
description: Frequency is between 2 and 4 MHz
|
|
value: 1
|
|
- name: Range4
|
|
description: Frequency is between 4 and 8 MHz
|
|
value: 2
|
|
- name: Range8
|
|
description: Frequency is between 8 and 16 MHz
|
|
value: 3
|
|
enum/PLLSRC:
|
|
bit_size: 2
|
|
variants:
|
|
- name: HSI
|
|
description: HSI selected as PLL clock
|
|
value: 0
|
|
- name: CSI
|
|
description: CSI selected as PLL clock
|
|
value: 1
|
|
- name: HSE
|
|
description: HSE selected as PLL clock
|
|
value: 2
|
|
- name: None
|
|
description: No clock sent to DIVMx dividers and PLLs
|
|
value: 3
|
|
enum/PLLVCOSEL:
|
|
bit_size: 1
|
|
variants:
|
|
- name: WideVCO
|
|
description: VCO frequency range 192 to 836 MHz
|
|
value: 0
|
|
- name: MediumVCO
|
|
description: VCO frequency range 150 to 420 MHz
|
|
value: 1
|
|
enum/PPRE:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Div1
|
|
description: rcc_hclk not divided
|
|
value: 0
|
|
- name: Div2
|
|
description: rcc_hclk divided by 2
|
|
value: 4
|
|
- name: Div4
|
|
description: rcc_hclk divided by 4
|
|
value: 5
|
|
- name: Div8
|
|
description: rcc_hclk divided by 8
|
|
value: 6
|
|
- name: Div16
|
|
description: rcc_hclk divided by 16
|
|
value: 7
|
|
enum/RNGSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: HSI48
|
|
description: HSI48 selected as peripheral clock
|
|
value: 0
|
|
- name: PLL1_Q
|
|
description: pll1_q selected as peripheral clock
|
|
value: 1
|
|
- name: LSE
|
|
description: LSE selected as peripheral clock
|
|
value: 2
|
|
- name: LSI
|
|
description: LSI selected as peripheral clock
|
|
value: 3
|
|
enum/RTCSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: NoClock
|
|
description: No clock
|
|
value: 0
|
|
- name: LSE
|
|
description: LSE oscillator clock used as RTC clock
|
|
value: 1
|
|
- name: LSI
|
|
description: LSI oscillator clock used as RTC clock
|
|
value: 2
|
|
- name: HSE
|
|
description: HSE oscillator clock divided by a prescaler used as RTC clock
|
|
value: 3
|
|
enum/SAIASEL:
|
|
bit_size: 3
|
|
variants:
|
|
- name: PLL1_Q
|
|
description: pll1_q selected as peripheral clock
|
|
value: 0
|
|
- name: PLL2_P
|
|
description: pll2_p selected as peripheral clock
|
|
value: 1
|
|
- name: PLL3_P
|
|
description: pll3_p selected as peripheral clock
|
|
value: 2
|
|
- name: I2S_CKIN
|
|
description: i2s_ckin selected as peripheral clock
|
|
value: 3
|
|
- name: PER
|
|
description: PER selected as peripheral clock
|
|
value: 4
|
|
enum/SAISEL:
|
|
bit_size: 3
|
|
variants:
|
|
- name: PLL1_Q
|
|
description: pll1_q selected as peripheral clock
|
|
value: 0
|
|
- name: PLL2_P
|
|
description: pll2_p selected as peripheral clock
|
|
value: 1
|
|
- name: PLL3_P
|
|
description: pll3_p selected as peripheral clock
|
|
value: 2
|
|
- name: I2S_CKIN
|
|
description: I2S_CKIN selected as peripheral clock
|
|
value: 3
|
|
- name: PER
|
|
description: PER selected as peripheral clock
|
|
value: 4
|
|
enum/SDMMCSEL:
|
|
bit_size: 1
|
|
variants:
|
|
- name: PLL1_Q
|
|
description: pll1_q selected as peripheral clock
|
|
value: 0
|
|
- name: PLL2_R
|
|
description: pll2_r selected as peripheral clock
|
|
value: 1
|
|
enum/SPDIFRXSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: PLL1_Q
|
|
description: pll1_q selected as peripheral clock
|
|
value: 0
|
|
- name: PLL2_R
|
|
description: pll2_r selected as peripheral clock
|
|
value: 1
|
|
- name: PLL3_R
|
|
description: pll3_r selected as peripheral clock
|
|
value: 2
|
|
- name: HSI
|
|
description: hsi_ker selected as peripheral clock
|
|
value: 3
|
|
enum/SPI45SEL:
|
|
bit_size: 3
|
|
variants:
|
|
- name: APB
|
|
description: APB clock selected as peripheral clock
|
|
value: 0
|
|
- name: PLL2_Q
|
|
description: pll2_q selected as peripheral clock
|
|
value: 1
|
|
- name: PLL3_Q
|
|
description: pll3_q selected as peripheral clock
|
|
value: 2
|
|
- name: HSI
|
|
description: hsi_ker selected as peripheral clock
|
|
value: 3
|
|
- name: CSI
|
|
description: csi_ker selected as peripheral clock
|
|
value: 4
|
|
- name: HSE
|
|
description: HSE selected as peripheral clock
|
|
value: 5
|
|
enum/SPI6SEL:
|
|
bit_size: 3
|
|
variants:
|
|
- name: APB4
|
|
description: rcc_pclk4 selected as peripheral clock
|
|
value: 0
|
|
- name: PLL2_Q
|
|
description: pll2_q selected as peripheral clock
|
|
value: 1
|
|
- name: PLL3_Q
|
|
description: pll3_q selected as peripheral clock
|
|
value: 2
|
|
- name: HSI
|
|
description: hsi_ker selected as peripheral clock
|
|
value: 3
|
|
- name: CSI
|
|
description: csi_ker selected as peripheral clock
|
|
value: 4
|
|
- name: HSE
|
|
description: HSE selected as peripheral clock
|
|
value: 5
|
|
enum/STOPWUCK:
|
|
bit_size: 1
|
|
variants:
|
|
- name: HSI
|
|
description: HSI selected as wake up clock from system Stop
|
|
value: 0
|
|
- name: CSI
|
|
description: CSI selected as wake up clock from system Stop
|
|
value: 1
|
|
enum/SW:
|
|
bit_size: 3
|
|
variants:
|
|
- name: HSI
|
|
description: HSI selected as system clock
|
|
value: 0
|
|
- name: CSI
|
|
description: CSI selected as system clock
|
|
value: 1
|
|
- name: HSE
|
|
description: HSE selected as system clock
|
|
value: 2
|
|
- name: PLL1
|
|
description: PLL1 selected as system clock
|
|
value: 3
|
|
enum/SWPSEL:
|
|
bit_size: 1
|
|
variants:
|
|
- name: PCLK
|
|
description: pclk selected as peripheral clock
|
|
value: 0
|
|
- name: HSI
|
|
description: hsi_ker selected as peripheral clock
|
|
value: 1
|
|
enum/TIMPRE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: DefaultX2
|
|
description: Timer kernel clock equal to 2x pclk by default
|
|
value: 0
|
|
- name: DefaultX4
|
|
description: Timer kernel clock equal to 4x pclk by default
|
|
value: 1
|
|
enum/USART16910SEL:
|
|
bit_size: 3
|
|
variants:
|
|
- name: APB2
|
|
description: rcc_pclk2 selected as peripheral clock
|
|
value: 0
|
|
- name: PLL2_Q
|
|
description: pll2_q selected as peripheral clock
|
|
value: 1
|
|
- name: PLL3_Q
|
|
description: pll3_q selected as peripheral clock
|
|
value: 2
|
|
- name: HSI
|
|
description: hsi_ker selected as peripheral clock
|
|
value: 3
|
|
- name: CSI
|
|
description: csi_ker selected as peripheral clock
|
|
value: 4
|
|
- name: LSE
|
|
description: LSE selected as peripheral clock
|
|
value: 5
|
|
enum/USART234578SEL:
|
|
bit_size: 3
|
|
variants:
|
|
- name: APB1
|
|
description: rcc_pclk1 selected as peripheral clock
|
|
value: 0
|
|
- name: PLL2_Q
|
|
description: pll2_q selected as peripheral clock
|
|
value: 1
|
|
- name: PLL3_Q
|
|
description: pll3_q selected as peripheral clock
|
|
value: 2
|
|
- name: HSI
|
|
description: hsi_ker selected as peripheral clock
|
|
value: 3
|
|
- name: CSI
|
|
description: csi_ker selected as peripheral clock
|
|
value: 4
|
|
- name: LSE
|
|
description: LSE selected as peripheral clock
|
|
value: 5
|
|
enum/USBSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: DISABLE
|
|
description: Disable the kernel clock
|
|
value: 0
|
|
- name: PLL1_Q
|
|
description: pll1_q selected as peripheral clock
|
|
value: 1
|
|
- name: PLL3_Q
|
|
description: pll3_q selected as peripheral clock
|
|
value: 2
|
|
- name: HSI48
|
|
description: HSI48 selected as peripheral clock
|
|
value: 3
|