stm32-data/data/registers/flash_h5.yaml

block/FLASH:
  description: FLASH address block description
  items:
  - name: ACR
    description: FLASH access control register
    byte_offset: 0
    fieldset: ACR
  - name: NSKEYR
    description: FLASH non-secure key register
    byte_offset: 4
    fieldset: NSKEYR
  - name: SECKEYR
    description: FLASH secure key register
    byte_offset: 8
    fieldset: SECKEYR
  - name: OPTKEYR
    description: FLASH option key register
    byte_offset: 12
    fieldset: OPTKEYR
  - name: NSOBKKEYR
    description: FLASH non-secure OBK key register
    byte_offset: 16
    fieldset: NSOBKKEYR
  - name: SECOBKKEYR
    description: FLASH secure OBK key register
    byte_offset: 20
    fieldset: SECOBKKEYR
  - name: OPSR
    description: FLASH operation status register
    byte_offset: 24
    fieldset: OPSR
  - name: OPTCR
    description: FLASH option control register
    byte_offset: 28
    fieldset: OPTCR
  - name: NSSR
    description: FLASH non-secure status register
    byte_offset: 32
    fieldset: NSSR
  - name: SECSR
    description: FLASH secure status register
    byte_offset: 36
    fieldset: SECSR
  - name: NSCR
    description: FLASH non-secure control register
    byte_offset: 40
    fieldset: NSCR
  - name: SECCR
    description: FLASH secure control register
    byte_offset: 44
    fieldset: SECCR
  - name: NSCCR
    description: FLASH non-secure clear control register
    byte_offset: 48
    fieldset: NSCCR
  - name: SECCCR
    description: FLASH secure clear control register
    byte_offset: 52
    fieldset: SECCCR
  - name: PRIVCFGR
    description: FLASH privilege configuration register
    byte_offset: 60
    fieldset: PRIVCFGR
  - name: NSOBKCFGR
    description: FLASH non-secure OBK configuration register
    byte_offset: 64
    fieldset: NSOBKCFGR
  - name: SECOBKCFGR
    description: FLASH secure OBK configuration register
    byte_offset: 68
    fieldset: SECOBKCFGR
  - name: HDPEXTR
    description: FLASH HDP extension register
    byte_offset: 72
    fieldset: HDPEXTR
  - name: OPTSR_CUR
    description: FLASH option status register
    byte_offset: 80
    fieldset: OPTSR
  - name: OPTSR_PRG
    description: FLASH option status register
    byte_offset: 84
    fieldset: OPTSR
  - name: NSEPOCHR_CUR
    description: FLASH non-secure EPOCH register
    byte_offset: 96
    fieldset: NSEPOCHR
  - name: SECEPOCHR_CUR
    description: FLASH secure EPOCH register
    byte_offset: 104
    fieldset: SECEPOCHR
  - name: OPTSR2_CUR
    description: FLASH option status register 2
    byte_offset: 112
    fieldset: OPTSR2
  - name: OPTSR2_PRG
    description: FLASH option status register 2
    byte_offset: 116
    fieldset: OPTSR2
  - name: NSBOOTR_CUR
    description: FLASH non-secure boot register
    byte_offset: 128
    fieldset: NSBOOTR
  - name: NSBOOTR_PRG
    description: FLASH non-secure boot register
    byte_offset: 132
    fieldset: NSBOOTR
  - name: SECBOOTR_CUR
    description: FLASH secure boot register
    byte_offset: 136
    fieldset: SECBOOTR
  - name: BOOTR_PRG
    description: FLASH secure boot register
    byte_offset: 140
    fieldset: BOOTR
  - name: OTPBLR_CUR
    description: FLASH non-secure OTP block lock
    byte_offset: 144
    fieldset: OTPBLR
  - name: OTPBLR_PRG
    description: FLASH non-secure OTP block lock
    byte_offset: 148
    fieldset: OTPBLR
  - name: SECBB1R1
    description: FLASH secure block based register for Bank 1
    byte_offset: 160
    fieldset: SECBB
  - name: SECBB1R2
    description: FLASH secure block based register for Bank 1
    byte_offset: 164
    fieldset: SECBB
  - name: SECBB1R3
    description: FLASH secure block based register for Bank 1
    byte_offset: 168
    fieldset: SECBB
  - name: SECBB1R4
    description: FLASH secure block based register for Bank 1
    byte_offset: 172
    fieldset: SECBB
  - name: PRIVBB1R1
    description: FLASH privilege block based register for Bank 1
    byte_offset: 192
    fieldset: PRIVBB
  - name: PRIVBB1R2
    description: FLASH privilege block based register for Bank 1
    byte_offset: 196
    fieldset: PRIVBB
  - name: PRIVBB1R3
    description: FLASH privilege block based register for Bank 1
    byte_offset: 200
    fieldset: PRIVBB
  - name: PRIVBB1R4
    description: FLASH privilege block based register for Bank 1
    byte_offset: 204
    fieldset: PRIVBB
  - name: SECWM1R_CUR
    description: FLASH security watermark for Bank 1
    byte_offset: 224
    fieldset: SECWM
  - name: SECWM1R_PRG
    description: FLASH security watermark for Bank 1
    byte_offset: 228
    fieldset: SECWM
  - name: WRP1R_CUR
    description: FLASH write sector group protection for Bank 1
    byte_offset: 232
    fieldset: WRP
  - name: WRP1R_PRG
    description: FLASH write sector group protection for Bank 1
    byte_offset: 236
    fieldset: WRP
  - name: EDATA1R_CUR
    description: FLASH data sector configuration Bank 1
    byte_offset: 240
    fieldset: EDATA1R
  - name: EDATA1R_PRG
    description: FLASH data sector configuration Bank 1
    byte_offset: 244
    fieldset: EDATA1R
  - name: HDP1R_CUR
    description: FLASH HDP Bank 1 configuration
    byte_offset: 248
    fieldset: HDP1R
  - name: HDP1R_PRG
    description: FLASH HDP Bank 1 configuration
    byte_offset: 252
    fieldset: HDP1R
  - name: ECCCORR
    description: FLASH ECC correction register
    byte_offset: 256
    fieldset: ECCCORR
  - name: ECCDETR
    description: FLASH ECC detection register
    byte_offset: 260
    fieldset: ECCDETR
  - name: ECCDR
    description: FLASH ECC data
    byte_offset: 264
    fieldset: ECCDR
  - name: SECBB2R1
    description: FLASH secure block-based register for Bank 2
    byte_offset: 416
    fieldset: SECBB
  - name: SECBB2R2
    description: FLASH secure block-based register for Bank 2
    byte_offset: 420
    fieldset: SECBB
  - name: SECBB2R3
    description: FLASH secure block-based register for Bank 2
    byte_offset: 424
    fieldset: SECBB
  - name: SECBB2R4
    description: FLASH secure block-based register for Bank 2
    byte_offset: 428
    fieldset: SECBB
  - name: PRIVBB2R1
    description: FLASH privilege block-based register for Bank 2
    byte_offset: 448
    fieldset: PRIVBB
  - name: PRIVBB2R2
    description: FLASH privilege block-based register for Bank 2
    byte_offset: 452
    fieldset: PRIVBB
  - name: PRIVBB2R3
    description: FLASH privilege block-based register for Bank 2
    byte_offset: 456
    fieldset: PRIVBB
  - name: PRIVBB2R4
    description: FLASH privilege block-based register for Bank 2
    byte_offset: 460
    fieldset: PRIVBB
  - name: SECWM2R_CUR
    description: FLASH security watermark for Bank 2
    byte_offset: 480
    fieldset: SECWM
  - name: SECWM2R_PRG
    description: FLASH security watermark for Bank 2
    byte_offset: 484
    fieldset: SECWM
  - name: WRP2R_CUR
    description: FLASH write sector group protection for Bank 2
    byte_offset: 488
    fieldset: WRP
  - name: WRP2R_PRG
    description: FLASH write sector group protection for Bank 2
    byte_offset: 492
    fieldset: WRP
  - name: EDATA2R_CUR
    description: FLASH data sectors configuration Bank 2
    byte_offset: 496
    fieldset: EDATA2R
  - name: EDATA2R_PRG
    description: FLASH data sector configuration Bank 2
    byte_offset: 500
    fieldset: EDATA2R
  - name: HDP2R_CUR
    description: FLASH HDP Bank 2 configuration
    byte_offset: 504
    fieldset: HDP2R
  - name: HDP2R_PRG
    description: FLASH HDP Bank 2 configuration
    byte_offset: 508
    fieldset: HDP2R
fieldset/ACR:
  description: FLASH access control register
  fields:
  - name: LATENCY
    description: "Read latency\r These bits are used to control the number of wait states used during read operations on both nonvolatile memory banks. The application software has to program them to the correct value depending on the embedded flash memory interface frequency and voltage conditions.\r ...\r Note: No check is performed by hardware to verify that the configuration is correct."
    bit_offset: 0
    bit_size: 4
  - name: WRHIGHFREQ
    description: "Flash signal delay \r These bits are used to control the delay between nonvolatile memory signals during programming operations. Application software has to program them to the correct value depending on the embedded flash memory interface frequency. Please refer to Table<6C>44 for details.\r Note: No check is performed to verify that the configuration is correct. \r Note: Two WRHIGHFREQ values can be selected for some frequencies."
    bit_offset: 4
    bit_size: 2
  - name: PRFTEN
    description: "Prefetch enable. When bit value is modified, user must read back ACR register to be sure PRFTEN has been taken into account.\r Bits used to control the prefetch."
    bit_offset: 8
    bit_size: 1
fieldset/BOOTR:
  description: FLASH secure boot register
  fields:
  - name: SECBOOT_LOCK
    description: A field locking the values of UBE, SWAP_ BANK, and SECBOOTADD setting.
    bit_offset: 0
    bit_size: 8
    enum: BOOTR_SECBOOT_LOCK
  - name: SECBOOTADD
    description: "Secure unique boot entry address.\r These bits allow configuring the secure UBE address."
    bit_offset: 8
    bit_size: 24
fieldset/ECCCORR:
  description: FLASH ECC correction register
  fields:
  - name: ADDR_ECC
    description: "ECC error address\r When an ECC error occurs (for single correction) during a read operation, the ADDR_ECC contains the address that generated the error. \r ADDR_ECC is reset when the flag error is reset. \r The flash interface programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an ECC error is saved.\r The address in ADDR_ECC is relative to the flash memory area where the error occurred (user flash memory, system flash memory, data area, read-only/OTP area)."
    bit_offset: 0
    bit_size: 16
  - name: OBK_ECC
    description: Single ECC error corrected in flash OB Keys storage area. It indicates the OBK storage concerned by ECC error.
    bit_offset: 20
    bit_size: 1
  - name: EDATA_ECC
    description: "ECC fail for corrected ECC error in flash high-cycle data area\r It indicates if flash high-cycle data area is concerned by ECC error."
    bit_offset: 21
    bit_size: 1
  - name: BK_ECC
    description: "ECC fail bank for corrected ECC error\r It indicates which bank is concerned by ECC error"
    bit_offset: 22
    bit_size: 1
  - name: SYSF_ECC
    description: "ECC fail for corrected ECC error in system flash memory\r It indicates if system flash memory is concerned by ECC error."
    bit_offset: 23
    bit_size: 1
  - name: OTP_ECC
    description: "OTP ECC error bit\r This bit is set to 1 when one single ECC correction occurred during the last successful read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bitfield."
    bit_offset: 24
    bit_size: 1
  - name: ECCCIE
    description: "ECC single correction error interrupt enable bit\r When ECCCIE bit is set to 1, an interrupt is generated when an ECC single correction error occurs during a read operation."
    bit_offset: 25
    bit_size: 1
  - name: ECCC
    description: "ECC correction set by hardware when single ECC error has been detected and corrected.\r Cleared by writing 1."
    bit_offset: 30
    bit_size: 1
fieldset/ECCDETR:
  description: FLASH ECC detection register
  fields:
  - name: ADDR_ECC
    description: "ECC error address\r When an ECC error occurs (double detection) during a read operation, the ADDR_ECC contains the address that generated the error. \r ADDR_ECC is reset when the flag error is reset. \r The flash interface programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an double ECC error is saved.\r The address in ADDR_ECC is relative to the flash memory area where the error occurred (user flash memory, system flash memory, data area, read-only/OTP area)."
    bit_offset: 0
    bit_size: 16
  - name: OBK_ECC
    description: ECC fail double ECC error in flash OB Keys storage area. It indicates the OBK storage concerned by ECC error.
    bit_offset: 20
    bit_size: 1
  - name: EDATA_ECC
    description: "ECC fail double ECC error in flash high-cycle data area\r It indicates if flash high-cycle data area is concerned by ECC error."
    bit_offset: 21
    bit_size: 1
  - name: BK_ECC
    description: "ECC fail bank for double ECC error\r It indicates which bank is concerned by ECC error"
    bit_offset: 22
    bit_size: 1
  - name: SYSF_ECC
    description: "ECC fail for double ECC error in system flash memory\r It indicates if system flash memory is concerned by ECC error."
    bit_offset: 23
    bit_size: 1
  - name: OTP_ECC
    description: "OTP ECC error bit\r This bit is set to 1 when double ECC detection occurred during the last read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bitfield."
    bit_offset: 24
    bit_size: 1
  - name: ECCD
    description: "ECC detection\r Set by hardware when two ECC error has been detected.\r When this bit is set, a NMI is generated.\r Cleared by writing 1. Needs to be cleared in order to detect subsequent double ECC errors."
    bit_offset: 31
    bit_size: 1
fieldset/ECCDR:
  description: FLASH ECC data
  fields:
  - name: DATA_ECC
    description: "ECC error data\r When an double detection ECC error occurs on special areas with 6-bit ECC on 16-bit data (data area, read-only/OTP area), the failing data is read to this register.\r By checking if it is possible to determine whether the failure was on a real data, or due to access to uninitialized memory."
    bit_offset: 0
    bit_size: 16
fieldset/EDATA1R:
  description: FLASH data sector configuration Bank 1
  fields:
  - name: EDATA1_STRT
    description: "EDATA1_STRT contains the start sectors of the flash high-cycle data area in Bank 1 There is no hardware effect to those bits. They shall be managed by ST tools in Flasher.\r ...\r Note: 111: The eight last sectors of the Bank 1 are reserved for flash high-cycle data"
    bit_offset: 0
    bit_size: 3
  - name: EDATA1_EN
    description: Bank 1 flash high-cycle data enable
    bit_offset: 15
    bit_size: 1
fieldset/EDATA2R:
  description: FLASH data sector configuration Bank 2
  fields:
  - name: EDATA2_STRT
    description: "EDATA2_STRT contains the start sectors of the flash high-cycle data area in Bank 2 There is no hardware effect to those bits. They shall be managed by ST tools in Flasher.\r ...\r Note: 111: The eight last sectors of the Bank 2 are reserved for flash high-cycle data."
    bit_offset: 0
    bit_size: 3
  - name: EDATA2_EN
    description: Bank 2 flash high-cycle data enable
    bit_offset: 15
    bit_size: 1
fieldset/HDP1R:
  description: FLASH HDP Bank 1 configuration
  fields:
  - name: HDP1_STRT
    description: HDPL barrier start set in number of 8-Kbyte sectors
    bit_offset: 0
    bit_size: 7
  - name: HDP1_END
    description: HDPL barrier end set in number of 8-Kbyte sectors
    bit_offset: 16
    bit_size: 7
fieldset/HDP2R:
  description: FLASH HDP Bank 2 configuration
  fields:
  - name: HDP2_STRT
    description: HDPL barrier start set in number of 8-Kbyte sectors
    bit_offset: 0
    bit_size: 7
  - name: HDP2_END
    description: HDPL barrier end set in number of 8-Kbyte sectors
    bit_offset: 16
    bit_size: 7
fieldset/HDPEXTR:
  description: FLASH HDP extension register
  fields:
  - name: HDP1_EXT
    description: HDP area extension in 8<>Kbytes sectors in Bank1. Extension is added after the HDP1_END sector (included).
    bit_offset: 0
    bit_size: 7
  - name: HDP2_EXT
    description: HDP area extension in 8<>Kbytes sectors in bank 2. Extension is added after the HDP2_END sector (included).
    bit_offset: 16
    bit_size: 7
fieldset/NSBOOTR:
  description: FLASH non-secure boot register
  fields:
  - name: NSBOOT_LOCK
    description: A field locking the values of SWAP_ BANK, and NSBOOTADD settings.
    bit_offset: 0
    bit_size: 8
    enum: NSBOOTR_NSBOOT_LOCK
  - name: NSBOOTADD
    description: "Non secure unique boot entry address \r These bits allow configuring the Non secure BOOT address"
    bit_offset: 8
    bit_size: 24
fieldset/NSCCR:
  description: FLASH non-secure clear control register
  fields:
  - name: CLR_EOP
    description: "EOP flag clear bit\r Setting this bit to 1 resets to 0 EOP flag in FLASH_NSSR register."
    bit_offset: 16
    bit_size: 1
  - name: CLR_WRPERR
    description: "WRPERR flag clear bit\r Setting this bit to 1 resets to 0 WRPERR flag in FLASH_NSSR register."
    bit_offset: 17
    bit_size: 1
  - name: CLR_PGSERR
    description: "PGSERR flag clear bit\r Setting this bit to 1 resets to 0 PGSERR flag in FLASH_NSSR register."
    bit_offset: 18
    bit_size: 1
  - name: CLR_STRBERR
    description: "STRBERR flag clear bit\r Setting this bit to 1 resets to 0 STRBERR flag in FLASH_NSSR register."
    bit_offset: 19
    bit_size: 1
  - name: CLR_INCERR
    description: "INCERR flag clear bit\r Setting this bit to 1 resets to 0 INCERR flag in FLASH_NSSR register."
    bit_offset: 20
    bit_size: 1
  - name: CLR_OBKERR
    description: "OBKERR flag clear bit.\r Setting this bit to 1 resets to 0 OBKERR flag in FLASH_NSSR register."
    bit_offset: 21
    bit_size: 1
  - name: CLR_OBKWERR
    description: "OBKWERR flag clear bit.\r Setting this bit to 1 resets to 0 OBKWERR flag in FLASH_NSSR register."
    bit_offset: 22
    bit_size: 1
  - name: CLR_OPTCHANGEERR
    description: Clear the flag corresponding flag in FLASH_NSSR by writing this bit.
    bit_offset: 23
    bit_size: 1
fieldset/NSCR:
  description: FLASH non-secure control register
  fields:
  - name: LOCK
    description: "configuration lock bit\r This bit locks the FLASH_NSCR register. The correct write sequence to FLASH_NSKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_NSKEYR is performed twice, this bit remains locked until the next system reset. \r LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_NSCR register do not change."
    bit_offset: 0
    bit_size: 1
  - name: PG
    description: "programming control bit\r PG can be programmed only when LOCK is cleared to 0. \r PG allows programming in Bank1 and Bank2."
    bit_offset: 1
    bit_size: 1
  - name: SER
    description: "sector erase request\r Setting SER bit to 1 requests a sector erase. SER can be programmed only when LOCK is cleared to 0. \r If MER and SER are also set, a PGSERR is raised."
    bit_offset: 2
    bit_size: 1
  - name: BER
    description: "erase request\r Setting BER bit to 1 requests a bank erase operation (user flash memory only). BER can be programmed only when LOCK is cleared to 0. \r If MER and SER are also set, a PGSERR is raised.\r Note: Write protection error is triggered when a bank erase is required and some sectors are protected."
    bit_offset: 3
    bit_size: 1
  - name: FW
    description: "write forcing control bit\r FW forces a write operation even if the write buffer is not full. In this case all bits not written are set to 1 by hardware. FW can be programmed only when LOCK is cleared to 0. \r The embedded flash memory resets FW when the corresponding operation has been acknowledged. \r Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it leads to permanent ECC error.\r Write forcing is effective only if the write buffer is not empty and was filled by non-secure access (in particular, FW does not start several write operations when the force-write operations are performed consecutively). \r Since there is just one write buffer, FW can force a write in bank1 or bank2."
    bit_offset: 4
    bit_size: 1
  - name: STRT
    description: "erase start control bit\r STRT bit is used to start a sector erase or a bank erase operation. STRT can be programmed only when LOCK is cleared to 0. \r STRT is reset at the end of the operation or when an error occurs. It cannot be reseted by software."
    bit_offset: 5
    bit_size: 1
  - name: SNB
    description: "sector erase selection number\r These bits are used to select the target sector for an erase operation (they are unused otherwise). SNB can be programmed only when LOCK is cleared to 0.\r .."
    bit_offset: 6
    bit_size: 7
  - name: MER
    description: "Mass erase request\r Setting MER bit to 1 requests a mass erase operation (user flash memory only). MER can be programmed only when LOCK is cleared to 0. \r If BER or SER are both set, a PGSERR is raised.\r Error is triggered when a mass erase is required and some sectors are protected."
    bit_offset: 15
    bit_size: 1
  - name: EOPIE
    description: "end of operation interrupt control bit\r Setting EOPIE bit to 1 enables the generation of an interrupt at the end of a program or erase operation. EOPIE can be programmed only when LOCK is cleared to 0."
    bit_offset: 16
    bit_size: 1
  - name: WRPERRIE
    description: "write protection error interrupt enable bit\r When this bit is set to 1, an interrupt is generated when a protection error occurs during a program operation. WRPERRIE can be programmed only when LOCK is cleared to 0."
    bit_offset: 17
    bit_size: 1
  - name: PGSERRIE
    description: "programming sequence error interrupt enable bit\r When this bit is set to 1, an interrupt is generated when a sequence error occurs during a program operation. PGSERRIE can be programmed only when LOCK is cleared to 0."
    bit_offset: 18
    bit_size: 1
  - name: STRBERRIE
    description: "strobe error interrupt enable bit\r When STRBERRIE bit is set to 1, an interrupt is generated when a strobe error occurs (the master programs several times the same byte in the write buffer) during a write operation. STRBERRIE can be programmed only when LOCK is cleared to 0."
    bit_offset: 19
    bit_size: 1
  - name: INCERRIE
    description: "inconsistency error interrupt enable bit\r When INCERRIE bit is set to 1, an interrupt is generated when an inconsistency error occurs during a write operation. INCERRIE can be programmed only when LOCK is cleared to 0."
    bit_offset: 20
    bit_size: 1
  - name: OBKERRIE
    description: "OBK general error interrupt enable bit\r OBKERRIE enables generating an interrupt in case of OBK specific access error. This bit can be programmed only when LOCK bit is cleared to 0."
    bit_offset: 21
    bit_size: 1
  - name: OBKWERRIE
    description: "OBK write error interrupt enable bit\r OBKWERRIE enables generation of interrupt in case of OBK specific write error. This bit can be programmed only when LOCK bit is cleared to 0."
    bit_offset: 22
    bit_size: 1
  - name: OPTCHANGEERRIE
    description: "Option byte change error interrupt enable bit\r This bit controls if an interrupt must be generated when an error occurs during an option byte change. It can be programmed only when LOCK bit is cleared to 0."
    bit_offset: 23
    bit_size: 1
  - name: BKSEL
    description: "Bank selector bit\r BKSEL can only be programmed when LOCK is cleared to 0. The bit selects physical bank, SWAP_BANK setting is ignored."
    bit_offset: 31
    bit_size: 1
    enum: NSCR_BKSEL
fieldset/NSEPOCHR:
  description: FLASH non-secure EPOCH register
  fields:
  - name: NS_EPOCH
    description: Non-volatile non-secure EPOCH counter
    bit_offset: 0
    bit_size: 24
fieldset/NSKEYR:
  description: FLASH non-secure key register
  fields:
  - name: NSKEY
    description: Non-volatile memory non-secure configuration access unlock key
    bit_offset: 0
    bit_size: 32
fieldset/NSOBKCFGR:
  description: FLASH non-secure OBK configuration register
  fields:
  - name: LOCK
    description: "OBKCFGR lock option configuration bit\r This bit locks the FLASH_NSOBKCFGR register. The correct write sequence to FLASH_NSOBKKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_NSOBKKEYR is performed twice, this bit remains locked until the next system reset. LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_NSCR register do not change."
    bit_offset: 0
    bit_size: 1
  - name: SWAP_SECT_REQ
    description: "OBK swap sector request bit\r When set, all the OBKs which have not been updated in the alternate sector is copied from current sector to alternate one.\r The SWAP_OFFSET value must be a certain minimum value in order for the swap to be launched in OBK-HDPL ≠ 0. Minimum value is 16 for OBK-HDPL = 1, 144 for OBK-HDPL = 2 and 192 for OBK-HDPL = 3."
    bit_offset: 1
    bit_size: 1
  - name: ALT_SECT
    description: "alternate sector bit\r This bit must not change while filling the write buffer, otherwise an error (OBKERR) is generated"
    bit_offset: 2
    bit_size: 1
  - name: ALT_SECT_ERASE
    description: "alternate sector erase bit\r When ALT_SECT bit is set, use this bit to generate an erase command for the OBK alternate sector. It is set only by Software and cleared when the OBK swap operation is completed or an error occurs (PGSERR). It is reseted at the same time as BUSY bit."
    bit_offset: 3
    bit_size: 1
  - name: SWAP_OFFSET
    description: "Key index (offset /16 bits) pointing for next swap.\r 0x01 means that only the first OBK data (128 bits) is copied from current to alternate OBK sector\r 0x02 means that the two first OBK data is copied …\r …"
    bit_offset: 16
    bit_size: 9
fieldset/NSOBKKEYR:
  description: FLASH non-secure OBK key register
  fields:
  - name: NSOBKKEY
    description: FLASH non-secure option bytes keys control access unlock key
    bit_offset: 0
    bit_size: 32
fieldset/NSSR:
  description: FLASH non-secure status register
  fields:
  - name: BSY
    description: "busy flag\r BSY flag indicates that a flash memory is busy by an operation (write, erase, option byte change, OBK operation). It is set at the beginning of a flash memory operation and cleared when the operation finishes, or an error occurs."
    bit_offset: 0
    bit_size: 1
  - name: WBNE
    description: "write buffer not empty flag \r WBNE flag is set when the flash interface is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below:\r the application software forces the write operation using FW bit in FLASH_NSCR\r the embedded flash memory detects an error that involves data loss\r This bit cannot be reset by software writing 0 directly. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data."
    bit_offset: 1
    bit_size: 1
  - name: DBNE
    description: "data buffer not empty flag \r DBNE flag is set when the flash interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free."
    bit_offset: 3
    bit_size: 1
  - name: EOP
    description: "end of operation flag\r EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to 1. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_NSCCR register."
    bit_offset: 16
    bit_size: 1
  - name: WRPERR
    description: "write protection error flag\r WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_NSCCR register clears WRPERR."
    bit_offset: 17
    bit_size: 1
  - name: PGSERR
    description: "programming sequence error flag\r PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_NSCCR register clears PGSERR."
    bit_offset: 18
    bit_size: 1
  - name: STRBERR
    description: "strobe error flag \r STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_NSCCR register clears STRBERR."
    bit_offset: 19
    bit_size: 1
  - name: INCERR
    description: "inconsistency error flag\r NSINCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_NSCCR register clears NSINCERR."
    bit_offset: 20
    bit_size: 1
  - name: OBKERR
    description: "OBK general error flag\r OBKERR flag is raised when the OBK-HDPL signal from the SBS does not match the HDPL value associated with the key slot during access to the key location. Alternatively also when the ALT_SECT is unexpectedly changed while the write buffer is being filled."
    bit_offset: 21
    bit_size: 1
  - name: OBKWERR
    description: "OBK write error flag\r OBKWERR flag is raised when the address is not virgin on a write access to the OBK storage. Alternatively also when the OBK selector in the alternate sector is not virgin during a swap operation."
    bit_offset: 22
    bit_size: 1
  - name: OPTCHANGEERR
    description: "Option byte change error flag \r OPTCHANGEERR flag indicates that an error occurred during an option byte change operation. When OPTCHANGEERR is set to 1, the option byte change operation did not successfully complete. An interrupt is generated when this flag is raised if the OPTCHANGEERRIE bit of FLASH_NSCR register is set to 1. \r Writing 1 to CLR_OPTCHANGEERR of register FLASH_NSCCR clears OPTCHANGEERR.\r Note: The OPTSTRT bit in FLASH_OPTCR cannot be set while OPTCHANGEERR is set."
    bit_offset: 23
    bit_size: 1
fieldset/OPSR:
  description: FLASH operation status register
  fields:
  - name: ADDR_OP
    description: Interrupted operation address
    bit_offset: 0
    bit_size: 20
  - name: DATA_OP
    description: "Flash high-cycle data area operation interrupted\r It indicates if flash high-cycle data area is concerned by operation."
    bit_offset: 21
    bit_size: 1
  - name: BK_OP
    description: "Interrupted operation bank\r It indicates which bank was concerned by operation."
    bit_offset: 22
    bit_size: 1
  - name: SYSF_OP
    description: "Operation in system flash memory interrupted \r Indicates that reset interrupted an ongoing operation in system flash."
    bit_offset: 23
    bit_size: 1
  - name: OTP_OP
    description: "OTP operation interrupted\r Indicates that reset interrupted an ongoing operation in OTP area (or OBKeys area)."
    bit_offset: 24
    bit_size: 1
  - name: CODE_OP
    description: Flash memory operation code
    bit_offset: 29
    bit_size: 3
    enum: CODE_OP
fieldset/OPTCR:
  description: FLASH option control register
  fields:
  - name: OPTLOCK
    description: "FLASH_OPTCR lock option configuration bit\r The OPTLOCK bit locks the FLASH_OPTCR register as well as all _PRG registers. The correct write sequence to FLASH_OPTKEYR register unlocks this bit. If a wrong sequence is executed, or the unlock sequence to FLASH_OPTKEYR is performed twice, this bit remains locked until next system reset. \r It is possible to set OPTLOCK by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When OPTLOCK changes from 0 to 1, the others bits of FLASH_OPTCR register do not change."
    bit_offset: 0
    bit_size: 1
  - name: OPTSTRT
    description: "Option byte start change option configuration bit\r OPTSTRT triggers an option byte change operation. The user can set OPTSTRT only when the OPTLOCK bit is cleared to 0. It is set only by Software and cleared when the option byte change is completed or an error occurs (PGSERR or OPTCHANGEERR). It is reseted at the same time as BSY bit.\r The user application cannot modify any FLASH_XXX_PRG flash interface register until the option change operation has been completed.\r Before setting this bit, the user has to write the required values in the FLASH_XXX_PRG registers. The FLASH_XXX_PRG registers are locked until the option byte change operation has been executed in nonvolatile memory."
    bit_offset: 1
    bit_size: 1
  - name: SWAP_BANK
    description: "Bank swapping option configuration bit\r SWAP_BANK controls whether Bank1 and Bank2 are swapped or not. This bit is loaded with the SWAP_BANK bit of FLASH_OPTSR_CUR register only after reset or POR."
    bit_offset: 31
    bit_size: 1
    enum: OPTCR_SWAP_BANK
fieldset/OPTKEYR:
  description: FLASH option key register
  fields:
  - name: OPTKEY
    description: FLASH option bytes control access unlock key
    bit_offset: 0
    bit_size: 32
fieldset/OPTSR:
  description: FLASH option status register
  fields:
  - name: BOR_LEV
    description: "Brownout level option status bit\r These bits reflects the power level that generates a system reset.\r 00 or 11: BOR Level 1, the threshold level is low (around 2.1<EFBFBD>V)"
    bit_offset: 0
    bit_size: 2
    enum: OPTSR_BOR_LEV
  - name: BORH_EN
    description: Brownout high enable
    bit_offset: 2
    bit_size: 1
  - name: IWDG_SW
    description: IWDG control mode option status bit
    bit_offset: 3
    bit_size: 1
    enum: OPTSR_IWDG_SW
  - name: WWDG_SW
    description: WWDG control mode option status bit
    bit_offset: 4
    bit_size: 1
    enum: OPTSR_WWDG_SW
  - name: NRST_STOP
    description: Core domain Stop entry reset option status bit
    bit_offset: 6
    bit_size: 1
    enum: OPTSR_NRST_STOP
  - name: NRST_STDBY
    description: Core domain Standby entry reset option status bit
    bit_offset: 7
    bit_size: 1
    enum: OPTSR_NRST_STDBY
  - name: PRODUCT_STATE
    description: 'Life state code (based on Hamming 8,4). More information in Section<6F>7.6.11: Product state transitions.'
    bit_offset: 8
    bit_size: 8
  - name: IO_VDD_HSLV
    description: "High-speed IO at low V<sub>DD</sub> voltage configuration bit.\r This bit can be set only with V<sub>DD</sub> below 2.7<EFBFBD>V."
    bit_offset: 16
    bit_size: 1
    enum: OPTSR_IO_VDD_HSLV
  - name: IO_VDDIO2_HSLV
    description: "High-speed IO at low V<sub>DDIO2</sub> voltage configuration bit.\r This bit can be set only with V<sub>DDIO2</sub> below 2.7<EFBFBD>V."
    bit_offset: 17
    bit_size: 1
    enum: OPTSR_IO_VDDIO_HSLV
  - name: IWDG_STOP
    description: "IWDG Stop mode freeze option status bit\r When set the independent watchdog IWDG is in system Stop mode."
    bit_offset: 20
    bit_size: 1
    enum: OPTSR_IWDG_STOP
  - name: IWDG_STDBY
    description: "IWDG Standby mode freeze option status bit\r When set the independent watchdog IWDG is frozen in system Standby mode."
    bit_offset: 21
    bit_size: 1
    enum: OPTSR_IWDG_STDBY
  - name: BOOT_UBE
    description: "Available only on cryptography enabled devices.\r Unique boot entry control, selects either ST or OEM iRoT for secure boot."
    bit_offset: 22
    bit_size: 8
    enum: OPTSR_BOOT_UBE
  - name: SWAP_BANK
    description: "Bank swapping option status bit\r SWAP_BANK reflects whether Bank1 and Bank2 are swapped or not. \r SWAP_BANK is loaded to SWAP_BANK of FLASH_OPTCR after a reset."
    bit_offset: 31
    bit_size: 1
    enum: OPTSR_SWAP_BANK
fieldset/OPTSR2:
  description: FLASH option status register 2
  fields:
  - name: SRAM13_RST
    description: SRAM1 and SRAM3 erase upon system reset
    bit_offset: 2
    bit_size: 1
  - name: SRAM2_RST
    description: SRAM2 erase when system reset
    bit_offset: 3
    bit_size: 1
  - name: BKPRAM_ECC
    description: Backup RAM ECC detection and correction disable
    bit_offset: 4
    bit_size: 1
    enum: OPTSR_BKPRAM_ECC
  - name: SRAM3_ECC
    description: SRAM3 ECC detection and correction disable
    bit_offset: 5
    bit_size: 1
    enum: OPTSR_SRAM_ECC
  - name: SRAM2_ECC
    description: SRAM2 ECC detection and correction disable
    bit_offset: 6
    bit_size: 1
    enum: OPTSR_SRAM_ECC
  - name: USBPD_DIS
    description: USB power delivery configuration option bit
    bit_offset: 8
    bit_size: 1
  - name: TZEN
    description: "TrustZone enable configuration bits\r This bit enables the device is in TrustZone mode during an option byte change."
    bit_offset: 24
    bit_size: 8
    enum: OPTSR_TZEN
fieldset/OTPBLR:
  description: FLASH non-secure OTP block lock
  fields:
  - name: LOCKBL
    description: "OTP block lock \r Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31.\r LOCKBL[n] = 1 indicates that all OTP 16-bit words in OTP Block n are locked and attempt to program them results in WRPERR.\r LOCKBL[n] = 0 indicates that all OTP 16-bit words in OTP Block n are not locked.\r When one block is locked, it’s not possible to remove the write protection.\r Also if not locked, it is not possible to erase OTP words."
    bit_offset: 0
    bit_size: 32
fieldset/PRIVBB:
  description: FLASH privilege block-based register for Bank 2
  fields:
  - name: PRIVBB
    description: Privileged / non-privileged 8-Kbyte flash Bank 2 sector attribute
    bit_offset: 0
    bit_size: 32
    enum: PRIVBBR_PRIVBB
fieldset/PRIVCFGR:
  description: FLASH privilege configuration register
  fields:
  - name: SPRIV
    description: privilege attribute for secure registers
    bit_offset: 0
    bit_size: 1
    enum: SPRIV
  - name: NSPRIV
    description: privilege attribute for non secure registers
    bit_offset: 1
    bit_size: 1
    enum: NSPRIV
fieldset/SECBB:
  description: FLASH secure block-based register for Bank 2
  fields:
  - name: SECBB
    description: Secure/non-secure flash Bank 2 sector attribute
    bit_offset: 0
    bit_size: 32
    enum: SECBBR_SECBB
fieldset/SECBOOTR:
  description: FLASH secure boot register
  fields:
  - name: SECBOOT_LOCK
    description: A field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings.
    bit_offset: 0
    bit_size: 8
    enum: SECBOOTR_SECBOOT_LOCK
  - name: SECBOOTADD
    description: "Unique boot entry secure address \r These bits reflect the Secure UBE address"
    bit_offset: 8
    bit_size: 24
fieldset/SECCCR:
  description: FLASH secure clear control register
  fields:
  - name: CLR_EOP
    description: "EOP flag clear bit\r Setting this bit to 1 resets to 0 EOP flag in FLASH_SECSR register."
    bit_offset: 16
    bit_size: 1
  - name: CLR_WRPERR
    description: "WRPERR flag clear bit\r Setting this bit to 1 resets to 0 WRPERR flag in FLASH_SECSR register."
    bit_offset: 17
    bit_size: 1
  - name: CLR_PGSERR
    description: "PGSERR flag clear bit\r Setting this bit to 1 resets to 0 PGSERR flag in FLASH_SECSR register."
    bit_offset: 18
    bit_size: 1
  - name: CLR_STRBERR
    description: "STRBERR flag clear bit\r Setting this bit to 1 resets to 0 STRBERR flag in FLASH_SECSR register."
    bit_offset: 19
    bit_size: 1
  - name: CLR_INCERR
    description: "INCERR flag clear bit\r Setting this bit to 1 resets to 0 INCERR flag in FLASH_SECSR register."
    bit_offset: 20
    bit_size: 1
  - name: CLR_OBKERR
    description: "OBKWERR flag clear bit\r Setting this bit to 1 resets to 0 OBKWERR flag in FLASH_SECSR register."
    bit_offset: 21
    bit_size: 1
  - name: CLR_OBKWERR
    description: "OBKWERR flag clear bit\r Setting this bit to 1 resets to 0 OBKWERR flag in FLASH_SECSR register."
    bit_offset: 22
    bit_size: 1
fieldset/SECCR:
  description: FLASH secure control register
  fields:
  - name: LOCK
    description: "configuration lock bit \r This bit locks the FLASH_SECCR register. The correct write sequence to FLASH_SECKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_NSKEYR is performed twice, this bit remains locked until the next system reset. \r LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_SECCR register do not change."
    bit_offset: 0
    bit_size: 1
  - name: PG
    description: "programming control bit\r PG can be programmed only when LOCK is cleared to 0. \r PG allows programming in Bank1 and Bank2."
    bit_offset: 1
    bit_size: 1
  - name: SER
    description: "sector erase request\r Setting SER bit to 1 requests a sector erase. SER can be programmed only when LOCK is cleared to 0. \r If BER and MER are also set, a PGSERR is raised."
    bit_offset: 2
    bit_size: 1
  - name: BER
    description: "erase request \r Setting BER bit to 1 requests a bank erase operation (user flash memory only). BER can be programmed only when LOCK is cleared to 0. \r If MER and SER are also set, a PGSERR is raised.\r Note: Write protection error is triggered when a bank erase is required and some sectors are protected."
    bit_offset: 3
    bit_size: 1
  - name: FW
    description: "write forcing control bit\r FW forces a write operation even if the write buffer is not full. In this case all bits not written are set to 1 by hardware. FW can be programmed only when LOCK is cleared to 0. \r The embedded flash memory resets FW when the corresponding operation has been acknowledged. \r Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it leads to permanent ECC error.\r Write forcing is effective only if the write buffer is not empty and was filled by secure access (in particular, FW does not start several write operations when the force-write operations are performed consecutively). \r Since there is just one write buffer, FW can force a write in bank1 or bank2."
    bit_offset: 4
    bit_size: 1
  - name: STRT
    description: "erase start control bit\r STRT bit is used to start a sector erase or a bank erase operation. STRT can be programmed only when LOCK is cleared to 0. \r STRT is reseted at the end of the operation or when an error occurs. It cannot be reset by software."
    bit_offset: 5
    bit_size: 1
  - name: SNB
    description: "sector erase selection number\r These bits are used to select the target sector for an erase operation (they are unused otherwise). SNB can be programmed only when LOCK is cleared to 0.\r .."
    bit_offset: 6
    bit_size: 7
  - name: MER
    description: "mass erase request\r Setting MER bit to 1 requests a mass erase operation (user flash memory only). MER can be programmed only when LOCK is cleared to 0. \r If BER or SER are also set, a PGSERR is raised.\r Error is triggered when a mass erase is required and some sectors are protected."
    bit_offset: 15
    bit_size: 1
  - name: EOPIE
    description: "end of operation interrupt control bit\r Setting EOPIE bit to 1 enables the generation of an interrupt at the end of a program/erase operation. EOPIE can be programmed only when LOCK is cleared to 0."
    bit_offset: 16
    bit_size: 1
  - name: WRPERRIE
    description: "write protection error interrupt enable bit\r When WRPERRIE bit is set to 1, an interrupt is generated when a protection error occurs during a program operation. WRPERRIE can be programmed only when LOCK is cleared to 0."
    bit_offset: 17
    bit_size: 1
  - name: PGSERRIE
    description: "programming sequence error interrupt enable bit\r When PGSERRIE bit is set to 1, an interrupt is generated when a sequence error occurs during a program operation. PGSERRIE can be programmed only when LOCK is cleared to 0."
    bit_offset: 18
    bit_size: 1
  - name: STRBERRIE
    description: "strobe error interrupt enable bit\r When STRBERRIE bit is set to 1, an interrupt is generated when a strobe error occurs (the master programs several times the same byte in the write buffer) during a write operation. STRBERRIE can be programmed only when LOCK is cleared to 0."
    bit_offset: 19
    bit_size: 1
  - name: INCERRIE
    description: "inconsistency error interrupt enable bit\r When INCERRIE bit is set to 1, an interrupt is generated when an inconsistency error occurs during a write operation. INCERRIE can be programmed only when LOCK is cleared to 0."
    bit_offset: 20
    bit_size: 1
  - name: OBKERRIE
    description: "OBK general error interrupt enable bit\r OBKERRIE enables generating an interrupt in case of OBK specific access error. OBKERRIE can be programmed only when LOCK is cleared to 0."
    bit_offset: 21
    bit_size: 1
  - name: OBKWERRIE
    description: "OBK write error interrupt enable bit\r OBKWERRIE enables generation of interrupt in case of OBK specific write error. OBKWERRIE can be programmed only when LOCK is cleared to 0."
    bit_offset: 22
    bit_size: 1
  - name: INV
    description: "Flash memory security state invert.\r This bit inverts the flash memory security state."
    bit_offset: 29
    bit_size: 1
  - name: BKSEL
    description: "bank selector bit\r BKSEL can only be programmed when LOCK is cleared to 0. The bit selects physical bank, SWAP_BANK setting is ignored."
    bit_offset: 31
    bit_size: 1
    enum: SECCR_BKSEL
fieldset/SECEPOCHR:
  description: FLASH secure EPOCH register
  fields:
  - name: SEC_EPOCH
    description: Non-volatile secure EPOCH counter
    bit_offset: 0
    bit_size: 24
fieldset/SECKEYR:
  description: FLASH secure key register
  fields:
  - name: SECKEY
    description: Non-volatile memory secure configuration access unlock key
    bit_offset: 0
    bit_size: 32
fieldset/SECOBKCFGR:
  description: FLASH secure OBK configuration register
  fields:
  - name: LOCK
    description: "OBKCFGR lock option configuration bit\r This bit locks the FLASH_OBKCFGR register. The correct write sequence to FLASH_SECOBKKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_SECOBKKEYR is performed twice, this bit remains locked until the next system reset. LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_NSCR register do not change."
    bit_offset: 0
    bit_size: 1
  - name: SWAP_SECT_REQ
    description: "OBK swap sector request bit\r When set, all the OBKs which have not been updated in the alternate sector is copied from current sector to alternate one.\r The SWAP_OFFSET value must be a certain minimum value in order for the swap to be launched in OBK-HDPL ≠ 0. Minimum value is 16 for OBK-HDPL = 1, 144 for OBK-HDPL = 2 and 192 for OBK-HDPL = 3."
    bit_offset: 1
    bit_size: 1
  - name: ALT_SECT
    description: "alternate sector bit\r This bit must not change while filling the write buffer, otherwise an error is generated"
    bit_offset: 2
    bit_size: 1
  - name: ALT_SECT_ERASE
    description: "alternate sector erase bit\r When ALT_SECT bit is set, use this bit to generate an erase command for the OBK alternate sector. It is set only by Software and cleared when the OBK swap operation is completed or an error occurs (PGSERR). It is reseted at the same time as the BUSY bit."
    bit_offset: 3
    bit_size: 1
  - name: SWAP_OFFSET
    description: "key index (offset /16 bits) pointing for next swap.\r …"
    bit_offset: 16
    bit_size: 9
fieldset/SECOBKKEYR:
  description: FLASH secure OBK key register
  fields:
  - name: SECOBKKEY
    description: FLASH secure option bytes keys control access unlock key
    bit_offset: 0
    bit_size: 32
fieldset/SECSR:
  description: FLASH secure status register
  fields:
  - name: BSY
    description: "busy flag\r BSY flag indicates that a FLASH memory is busy (write, erase, option byte change, OBK operations). It is set at the beginning of a flash memory operation and cleared when the operation finishes or an error occurs."
    bit_offset: 0
    bit_size: 1
  - name: WBNE
    description: "write buffer not empty flag \r WBNE flag is set when the flash interface is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below:\r the application software forces the write operation using FW bit in FLASH_SECCR\r the flash interface detects an error that involves data loss\r This bit cannot be reset by writing 0 directly by software. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data."
    bit_offset: 1
    bit_size: 1
  - name: DBNE
    description: "data buffer not empty flag \r DBNE flag is set when the embedded flash memory interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free."
    bit_offset: 3
    bit_size: 1
  - name: EOP
    description: "end of operation flag\r EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_SECCCR register."
    bit_offset: 16
    bit_size: 1
  - name: WRPERR
    description: "write protection error flag\r WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_SECCCR register clears WRPERR."
    bit_offset: 17
    bit_size: 1
  - name: PGSERR
    description: "programming sequence error flag\r PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_SECCCR register clears PGSERR."
    bit_offset: 18
    bit_size: 1
  - name: STRBERR
    description: "strobe error flag \r STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_SECCCR register clears STRBERR."
    bit_offset: 19
    bit_size: 1
  - name: INCERR
    description: "inconsistency error flag\r INCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_SECCCR register clears INCERR."
    bit_offset: 20
    bit_size: 1
  - name: OBKERR
    description: "OBK general error flag\r OBKERR flag is raised when the OBK-HDPL signal from the SBS does not match the HDPL value associated with the key slot during access to the key location. Alternatively also when the ALT_SECT is unexpectedly changed while the write buffer is being filled."
    bit_offset: 21
    bit_size: 1
  - name: OBKWERR
    description: "OBK write error flag\r OBKWERR flag is raised when the address is not virgin on a write access to the OBK storage. Alternatively also when the OBK selector in the alternate sector is not virgin during a swap operation."
    bit_offset: 22
    bit_size: 1
fieldset/SECWM:
  description: FLASH security watermark for Bank 2
  fields:
  - name: SECWMSTRT
    description: Bank2 security WM area start sector
    bit_offset: 0
    bit_size: 7
  - name: SECWMEND
    description: Bank2 security WM end sector
    bit_offset: 16
    bit_size: 7
fieldset/WRP:
  description: FLASH write sector group protection for Bank 1
  fields:
  - name: WRPSG
    description: "Bank1 sector group protection option status byte\r Setting WRPSG1 bits to 0 write protects the corresponding group of four consecutive sectors in bank 1 (0: the group is write protected; 1: the group is not write protected)\r Bit 0: Group embedding sectors 0 to 3\r Bit 1: Group embedding sectors 4 to 7\r Bit N: Group embedding sectors 4 x N to 4 x N + 3\r Bit 31: Group embedding sectors 124 to 127"
    bit_offset: 0
    bit_size: 32
enum/BOOTR_SECBOOT_LOCK:
  bit_size: 8
  variants:
  - name: B_0xB4
    description: The BOOT_UBE and SECBOOTADD are frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled).
    value: 180
  - name: B_0xC3
    description: The BOOT_UBE, SWAP_ BANK and SECBOOTADD can still be modified following their individual rules.
    value: 195
enum/CODE_OP:
  bit_size: 3
  variants:
  - name: B_0x0
    description: No flash operation on going during previous reset
    value: 0
  - name: B_0x1
    description: Single write operation interrupted
    value: 1
  - name: B_0x2
    description: OBK alternate sector erase
    value: 2
  - name: B_0x3
    description: Sector erase operation interrupted
    value: 3
  - name: B_0x4
    description: Bank erase operation interrupted
    value: 4
  - name: B_0x5
    description: Mass erase operation interrupted
    value: 5
  - name: B_0x6
    description: Option change operation interrupted
    value: 6
  - name: B_0x7
    description: OBK swap sector request
    value: 7
enum/NSBOOTR_NSBOOT_LOCK:
  bit_size: 8
  variants:
  - name: B_0xB4
    description: The NSBOOTADD is frozen. SWAP_ BANK can only be modified with TZEN set to 0xB4 (enabled).
    value: 180
  - name: B_0xC3
    description: The SWAP_ BANK and NSBOOTADD can still be modified following their individual rules.
    value: 195
enum/NSCR_BKSEL:
  bit_size: 1
  variants:
  - name: B_0x0
    description: Bank1 is selected for Bank erase / sector erase / interrupt enable
    value: 0
  - name: B_0x1
    description: Bank2 is selected for BER / SER
    value: 1
enum/NSPRIV:
  bit_size: 1
  variants:
  - name: B_0x0
    description: access to non secure registers is always granted
    value: 0
  - name: B_0x1
    description: access to non secure registers is denied in case of unprivileged access.
    value: 1
enum/OPTCR_SWAP_BANK:
  bit_size: 1
  variants:
  - name: B_0x0
    description: Bank1 and Bank2 not swapped
    value: 0
  - name: B_0x1
    description: Bank1 and Bank2 swapped
    value: 1
enum/OPTSR_BKPRAM_ECC:
  bit_size: 1
  variants:
  - name: B_0x0
    description: BKPRAM ECC check enabled
    value: 0
  - name: B_0x1
    description: BKPRAM ECC check disabled
    value: 1
enum/OPTSR_BOOT_UBE:
  bit_size: 8
  variants:
  - name: B_0xB4
    description: OEM-iRoT (user flash) selected. In Open PRODUCT_STATE this value selects bootloader. Defaut value.
    value: 180
  - name: B_0xC3
    description: ST-iRoT (system flash) selected
    value: 195
enum/OPTSR_BOR_LEV:
  bit_size: 2
  variants:
  - name: B_0x1
    description: BOR Level 2, the threshold level is medium (around 2.4 V)
    value: 1
  - name: B_0x2
    description: BOR Level 3, the threshold level is high (around 2.7 V)
    value: 2
enum/OPTSR_IO_VDDIO_HSLV:
  bit_size: 1
  variants:
  - name: B_0x0
    description: High-speed IO at low V<sub>DDIO2</sub> voltage feature disabled (V<sub>DDIO2</sub> can exceed 2.7<EFBFBD>V)
    value: 0
  - name: B_0x1
    description: High-speed IO at low V<sub>DDIO2</sub> voltage feature enabled (V<sub>DDIO2</sub> remains below 2.7<EFBFBD>V)
    value: 1
enum/OPTSR_IO_VDD_HSLV:
  bit_size: 1
  variants:
  - name: B_0x0
    description: High-speed IO at low V<sub>DD</sub> voltage feature disabled (V<sub>DD</sub> can exceed 2.7<EFBFBD>V)
    value: 0
  - name: B_0x1
    description: High-speed IO at low V<sub>DD</sub> voltage feature enabled (V<sub>DD</sub> remains below 2.7<EFBFBD>V)
    value: 1
enum/OPTSR_IWDG_STDBY:
  bit_size: 1
  variants:
  - name: B_0x0
    description: Independent watchdog frozen in Standby mode
    value: 0
  - name: B_0x1
    description: Independent watchdog keep running in Standby mode.
    value: 1
enum/OPTSR_IWDG_STOP:
  bit_size: 1
  variants:
  - name: B_0x0
    description: Independent watchdog frozen in system Stop mode
    value: 0
  - name: B_0x1
    description: Independent watchdog keep running in system Stop mode.
    value: 1
enum/OPTSR_IWDG_SW:
  bit_size: 1
  variants:
  - name: B_0x0
    description: IWDG watchdog is controlled by hardware
    value: 0
  - name: B_0x1
    description: IWDG watchdog is controlled by software
    value: 1
enum/OPTSR_NRST_STDBY:
  bit_size: 1
  variants:
  - name: B_0x0
    description: a reset is generated when entering Standby mode on core domain
    value: 0
  - name: B_0x1
    description: no reset generated when entering Standby mode on core domain.
    value: 1
enum/OPTSR_NRST_STOP:
  bit_size: 1
  variants:
  - name: B_0x0
    description: a reset is generated when entering Stop mode on core domain
    value: 0
  - name: B_0x1
    description: no reset generated when entering Stop mode on core domain.
    value: 1
enum/OPTSR_SRAM_ECC:
  bit_size: 1
  variants:
  - name: B_0x0
    description: SRAM2 ECC check enabled
    value: 0
  - name: B_0x1
    description: SRAM2 ECC check disabled
    value: 1
enum/OPTSR_SWAP_BANK:
  bit_size: 1
  variants:
  - name: B_0x0
    description: Bank1 and Bank2 not swapped
    value: 0
  - name: B_0x1
    description: Bank1 and Bank2 swapped
    value: 1
enum/OPTSR_TZEN:
  bit_size: 8
  variants:
  - name: B_0xB4
    description: TrustZone enabled.
    value: 180
  - name: B_0xC3
    description: TrustZone disabled
    value: 195
enum/OPTSR_WWDG_SW:
  bit_size: 1
  variants:
  - name: B_0x0
    description: WWDG watchdog is controlled by hardware
    value: 0
  - name: B_0x1
    description: WWDG watchdog is controlled by software
    value: 1
enum/PRIVBBR_PRIVBB:
  bit_size: 32
  variants:
  - name: B_0x0
    description: sectors (32 * (x-1) + y) in bank 2 is unprivileged
    value: 0
  - name: B_0x1
    description: sector (32 * (x-1) + y) in bank 2 is privileged
    value: 1
enum/SECBBR_SECBB:
  bit_size: 32
  variants:
  - name: B_0x0
    description: sectors (32 * (x-1) + y) in bank 2 is non secure
    value: 0
  - name: B_0x1
    description: sector (32 * (x-1) + y) in bank 2 is secure
    value: 1
enum/SECBOOTR_SECBOOT_LOCK:
  bit_size: 8
  variants:
  - name: B_0xB4
    description: The BOOT_UBE and SECBOOTADD are frozen. SWAP_ BANK can only be modified with TZEN set to 0xC3 (disabled).
    value: 180
  - name: B_0xC3
    description: The BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules.
    value: 195
enum/SECCR_BKSEL:
  bit_size: 1
  variants:
  - name: B_0x0
    description: Bank1 is selected for Bank erase / sector erase / interrupt enable
    value: 0
  - name: B_0x1
    description: Bank2 is selected for BER / SER
    value: 1
enum/SPRIV:
  bit_size: 1
  variants:
  - name: B_0x0
    description: access to secure registers is always granted
    value: 0
  - name: B_0x1
    description: access to secure registers is denied in case of unprivileged access.
    value: 1