776 lines
15 KiB
YAML
776 lines
15 KiB
YAML
block/CAN:
|
|
description: Controller area network
|
|
items:
|
|
- name: MCR
|
|
description: master control register
|
|
byte_offset: 0
|
|
fieldset: MCR
|
|
- name: MSR
|
|
description: master status register
|
|
byte_offset: 4
|
|
fieldset: MSR
|
|
- name: TSR
|
|
description: transmit status register
|
|
byte_offset: 8
|
|
fieldset: TSR
|
|
- name: RFR
|
|
description: receive FIFO 0 register
|
|
array:
|
|
len: 2
|
|
stride: 4
|
|
byte_offset: 12
|
|
fieldset: RFR
|
|
- name: IER
|
|
description: interrupt enable register
|
|
byte_offset: 20
|
|
fieldset: IER
|
|
- name: ESR
|
|
description: error status register
|
|
byte_offset: 24
|
|
fieldset: ESR
|
|
- name: BTR
|
|
description: bit timing register
|
|
byte_offset: 28
|
|
fieldset: BTR
|
|
- name: TX
|
|
description: CAN Transmit cluster
|
|
array:
|
|
len: 3
|
|
stride: 16
|
|
byte_offset: 384
|
|
block: TX
|
|
- name: RX
|
|
description: CAN Receive cluster
|
|
array:
|
|
len: 2
|
|
stride: 16
|
|
byte_offset: 432
|
|
block: RX
|
|
- name: FMR
|
|
description: filter master register
|
|
byte_offset: 512
|
|
fieldset: FMR
|
|
- name: FM1R
|
|
description: filter mode register
|
|
byte_offset: 516
|
|
fieldset: FM1R
|
|
- name: FS1R
|
|
description: filter scale register
|
|
byte_offset: 524
|
|
fieldset: FS1R
|
|
- name: FFA1R
|
|
description: filter FIFO assignment register
|
|
byte_offset: 532
|
|
fieldset: FFA1R
|
|
- name: FA1R
|
|
description: filter activation register
|
|
byte_offset: 540
|
|
fieldset: FA1R
|
|
- name: FB
|
|
description: CAN Filter Bank cluster
|
|
array:
|
|
len: 28
|
|
stride: 8
|
|
byte_offset: 576
|
|
block: FB
|
|
block/FB:
|
|
description: CAN Filter Bank cluster
|
|
items:
|
|
- name: FR1
|
|
description: Filter bank 0 register 1
|
|
byte_offset: 0
|
|
fieldset: FR1
|
|
- name: FR2
|
|
description: Filter bank 0 register 2
|
|
byte_offset: 4
|
|
fieldset: FR2
|
|
block/RX:
|
|
description: CAN Receive cluster
|
|
items:
|
|
- name: RIR
|
|
description: receive FIFO mailbox identifier register
|
|
byte_offset: 0
|
|
access: Read
|
|
fieldset: RIR
|
|
- name: RDTR
|
|
description: mailbox data high register
|
|
byte_offset: 4
|
|
access: Read
|
|
fieldset: RDTR
|
|
- name: RDLR
|
|
description: mailbox data high register
|
|
byte_offset: 8
|
|
access: Read
|
|
fieldset: RDLR
|
|
- name: RDHR
|
|
description: receive FIFO mailbox data high register
|
|
byte_offset: 12
|
|
access: Read
|
|
fieldset: RDHR
|
|
block/TX:
|
|
description: CAN Transmit cluster
|
|
items:
|
|
- name: TIR
|
|
description: TX mailbox identifier register
|
|
byte_offset: 0
|
|
fieldset: TIR
|
|
- name: TDTR
|
|
description: mailbox data length control and time stamp register
|
|
byte_offset: 4
|
|
fieldset: TDTR
|
|
- name: TDLR
|
|
description: mailbox data low register
|
|
byte_offset: 8
|
|
fieldset: TDLR
|
|
- name: TDHR
|
|
description: mailbox data high register
|
|
byte_offset: 12
|
|
fieldset: TDHR
|
|
fieldset/BTR:
|
|
description: bit timing register
|
|
fields:
|
|
- name: BRP
|
|
description: BRP
|
|
bit_offset: 0
|
|
bit_size: 10
|
|
- name: TS
|
|
description: TS1
|
|
bit_offset: 16
|
|
bit_size: 4
|
|
array:
|
|
len: 2
|
|
stride: 4
|
|
- name: SJW
|
|
description: SJW
|
|
bit_offset: 24
|
|
bit_size: 2
|
|
- name: LBKM
|
|
description: LBKM
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: LBKM
|
|
- name: SILM
|
|
description: SILM
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: SILM
|
|
fieldset/ESR:
|
|
description: interrupt enable register
|
|
fields:
|
|
- name: EWGF
|
|
description: EWGF
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: EPVF
|
|
description: EPVF
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: BOFF
|
|
description: BOFF
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: LEC
|
|
description: LEC
|
|
bit_offset: 4
|
|
bit_size: 3
|
|
enum: LEC
|
|
- name: TEC
|
|
description: TEC
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
- name: REC
|
|
description: REC
|
|
bit_offset: 24
|
|
bit_size: 8
|
|
fieldset/FA1R:
|
|
description: filter activation register
|
|
fields:
|
|
- name: FACT
|
|
description: Filter active
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
array:
|
|
len: 28
|
|
stride: 1
|
|
fieldset/FFA1R:
|
|
description: filter FIFO assignment register
|
|
fields:
|
|
- name: FFA
|
|
description: Filter FIFO assignment for filter 0
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
array:
|
|
len: 28
|
|
stride: 1
|
|
fieldset/FM1R:
|
|
description: filter mode register
|
|
fields:
|
|
- name: FBM
|
|
description: Filter mode
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
array:
|
|
len: 28
|
|
stride: 1
|
|
fieldset/FMR:
|
|
description: filter master register
|
|
fields:
|
|
- name: FINIT
|
|
description: FINIT
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: CAN2SB
|
|
description: CAN2SB
|
|
bit_offset: 8
|
|
bit_size: 6
|
|
fieldset/FR1:
|
|
description: Filter bank 0 register 1
|
|
fields:
|
|
- name: FB
|
|
description: Filter bits
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
array:
|
|
len: 32
|
|
stride: 1
|
|
fieldset/FR2:
|
|
description: Filter bank 0 register 2
|
|
fields:
|
|
- name: FB
|
|
description: Filter bits
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
array:
|
|
len: 32
|
|
stride: 1
|
|
fieldset/FS1R:
|
|
description: filter scale register
|
|
fields:
|
|
- name: FSC
|
|
description: Filter scale configuration
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
array:
|
|
len: 28
|
|
stride: 1
|
|
fieldset/IER:
|
|
description: interrupt enable register
|
|
fields:
|
|
- name: TMEIE
|
|
description: TMEIE
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: TMEIE
|
|
- name: FMPIE
|
|
description: FMPIE0
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
array:
|
|
len: 2
|
|
stride: 3
|
|
enum: FMPIE
|
|
- name: FFIE
|
|
description: FFIE0
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
array:
|
|
len: 2
|
|
stride: 3
|
|
enum: FFIE
|
|
- name: FOVIE
|
|
description: FOVIE0
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
array:
|
|
len: 2
|
|
stride: 3
|
|
enum: FOVIE
|
|
- name: EWGIE
|
|
description: EWGIE
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: EWGIE
|
|
- name: EPVIE
|
|
description: EPVIE
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: EPVIE
|
|
- name: BOFIE
|
|
description: BOFIE
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: BOFIE
|
|
- name: LECIE
|
|
description: LECIE
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: LECIE
|
|
- name: ERRIE
|
|
description: ERRIE
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: ERRIE
|
|
- name: WKUIE
|
|
description: WKUIE
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: WKUIE
|
|
- name: SLKIE
|
|
description: SLKIE
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: SLKIE
|
|
fieldset/MCR:
|
|
description: master control register
|
|
fields:
|
|
- name: INRQ
|
|
description: INRQ
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: SLEEP
|
|
description: SLEEP
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: TXFP
|
|
description: TXFP
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: RFLM
|
|
description: RFLM
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: NART
|
|
description: NART
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: AWUM
|
|
description: AWUM
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: ABOM
|
|
description: ABOM
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: TTCM
|
|
description: TTCM
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: RESET
|
|
description: RESET
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: DBF
|
|
description: DBF
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
fieldset/MSR:
|
|
description: master status register
|
|
fields:
|
|
- name: INAK
|
|
description: INAK
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: SLAK
|
|
description: SLAK
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: ERRI
|
|
description: ERRI
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: WKUI
|
|
description: WKUI
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: SLAKI
|
|
description: SLAKI
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: TXM
|
|
description: TXM
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: RXM
|
|
description: RXM
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: SAMP
|
|
description: SAMP
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: RX
|
|
description: RX
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
fieldset/RDHR:
|
|
description: receive FIFO mailbox data high register
|
|
fields:
|
|
- name: DATA
|
|
description: DATA4
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
array:
|
|
len: 4
|
|
stride: 8
|
|
fieldset/RDLR:
|
|
description: mailbox data high register
|
|
fields:
|
|
- name: DATA
|
|
description: DATA0
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
array:
|
|
len: 4
|
|
stride: 8
|
|
fieldset/RDTR:
|
|
description: mailbox data high register
|
|
fields:
|
|
- name: DLC
|
|
description: DLC
|
|
bit_offset: 0
|
|
bit_size: 4
|
|
- name: FMI
|
|
description: FMI
|
|
bit_offset: 8
|
|
bit_size: 8
|
|
- name: TIME
|
|
description: TIME
|
|
bit_offset: 16
|
|
bit_size: 16
|
|
fieldset/RFR:
|
|
description: receive FIFO 0 register
|
|
fields:
|
|
- name: FMP
|
|
description: FMP0
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: FULL
|
|
description: FULL0
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: FOVR
|
|
description: FOVR0
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: RFOM
|
|
description: RFOM0
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
fieldset/RIR:
|
|
description: receive FIFO mailbox identifier register
|
|
fields:
|
|
- name: RTR
|
|
description: RTR
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: RIR_RTR
|
|
- name: IDE
|
|
description: IDE
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: RIR_IDE
|
|
- name: EXID
|
|
description: EXID
|
|
bit_offset: 3
|
|
bit_size: 18
|
|
- name: STID
|
|
description: STID
|
|
bit_offset: 21
|
|
bit_size: 11
|
|
fieldset/TDHR:
|
|
description: mailbox data high register
|
|
fields:
|
|
- name: DATA
|
|
description: DATA4
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
array:
|
|
len: 4
|
|
stride: 8
|
|
fieldset/TDLR:
|
|
description: mailbox data low register
|
|
fields:
|
|
- name: DATA
|
|
description: DATA0
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
array:
|
|
len: 4
|
|
stride: 8
|
|
fieldset/TDTR:
|
|
description: mailbox data length control and time stamp register
|
|
fields:
|
|
- name: DLC
|
|
description: DLC
|
|
bit_offset: 0
|
|
bit_size: 4
|
|
- name: TGT
|
|
description: TGT
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: TIME
|
|
description: TIME
|
|
bit_offset: 16
|
|
bit_size: 16
|
|
fieldset/TIR:
|
|
description: TX mailbox identifier register
|
|
fields:
|
|
- name: TXRQ
|
|
description: TXRQ
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: RTR
|
|
description: RTR
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: TIR_RTR
|
|
- name: IDE
|
|
description: IDE
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: TIR_IDE
|
|
- name: EXID
|
|
description: EXID
|
|
bit_offset: 3
|
|
bit_size: 18
|
|
- name: STID
|
|
description: STID
|
|
bit_offset: 21
|
|
bit_size: 11
|
|
fieldset/TSR:
|
|
description: transmit status register
|
|
fields:
|
|
- name: RQCP
|
|
description: RQCP0
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
array:
|
|
len: 3
|
|
stride: 8
|
|
- name: TXOK
|
|
description: TXOK0
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
array:
|
|
len: 3
|
|
stride: 8
|
|
- name: ALST
|
|
description: ALST0
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
array:
|
|
len: 3
|
|
stride: 8
|
|
- name: TERR
|
|
description: TERR0
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
array:
|
|
len: 3
|
|
stride: 8
|
|
- name: ABRQ
|
|
description: ABRQ0
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
array:
|
|
len: 3
|
|
stride: 8
|
|
- name: CODE
|
|
description: CODE
|
|
bit_offset: 24
|
|
bit_size: 2
|
|
- name: TME
|
|
description: Lowest priority flag for mailbox 0
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
array:
|
|
len: 3
|
|
stride: 1
|
|
- name: LOW
|
|
description: Lowest priority flag for mailbox 0
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
array:
|
|
len: 3
|
|
stride: 1
|
|
enum/BOFIE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: ERRI bit will not be set when BOFF is set
|
|
value: 0
|
|
- name: Enabled
|
|
description: ERRI bit will be set when BOFF is set
|
|
value: 1
|
|
enum/EPVIE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: ERRI bit will not be set when EPVF is set
|
|
value: 0
|
|
- name: Enabled
|
|
description: ERRI bit will be set when EPVF is set
|
|
value: 1
|
|
enum/ERRIE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: No interrupt will be generated when an error condition is pending in the CAN_ESR
|
|
value: 0
|
|
- name: Enabled
|
|
description: An interrupt will be generation when an error condition is pending in the CAN_ESR
|
|
value: 1
|
|
enum/EWGIE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: ERRI bit will not be set when EWGF is set
|
|
value: 0
|
|
- name: Enabled
|
|
description: ERRI bit will be set when EWGF is set
|
|
value: 1
|
|
enum/FFIE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: No interrupt when FULL bit is set
|
|
value: 0
|
|
- name: Enabled
|
|
description: Interrupt generated when FULL bit is set
|
|
value: 1
|
|
enum/FMPIE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: No interrupt generated when state of FMP[1:0] bits are not 00b
|
|
value: 0
|
|
- name: Enabled
|
|
description: Interrupt generated when state of FMP[1:0] bits are not 00b
|
|
value: 1
|
|
enum/FOVIE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: No interrupt when FOVR bit is set
|
|
value: 0
|
|
- name: Enabled
|
|
description: Interrupt generated when FOVR bit is set
|
|
value: 1
|
|
enum/LBKM:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Loop Back Mode disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: Loop Back Mode enabled
|
|
value: 1
|
|
enum/LEC:
|
|
bit_size: 3
|
|
variants:
|
|
- name: NoError
|
|
description: No Error
|
|
value: 0
|
|
- name: Stuff
|
|
description: Stuff Error
|
|
value: 1
|
|
- name: Form
|
|
description: Form Error
|
|
value: 2
|
|
- name: Ack
|
|
description: Acknowledgment Error
|
|
value: 3
|
|
- name: BitRecessive
|
|
description: Bit recessive Error
|
|
value: 4
|
|
- name: BitDominant
|
|
description: Bit dominant Error
|
|
value: 5
|
|
- name: Crc
|
|
description: CRC Error
|
|
value: 6
|
|
- name: Custom
|
|
description: Set by software
|
|
value: 7
|
|
enum/LECIE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection
|
|
value: 0
|
|
- name: Enabled
|
|
description: ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection
|
|
value: 1
|
|
enum/RIR_IDE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Standard
|
|
description: Standard identifier
|
|
value: 0
|
|
- name: Extended
|
|
description: Extended identifier
|
|
value: 1
|
|
enum/RIR_RTR:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Data
|
|
description: Data frame
|
|
value: 0
|
|
- name: Remote
|
|
description: Remote frame
|
|
value: 1
|
|
enum/SILM:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Normal
|
|
description: Normal operation
|
|
value: 0
|
|
- name: Silent
|
|
description: Silent Mode
|
|
value: 1
|
|
enum/SLKIE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: No interrupt when SLAKI bit is set
|
|
value: 0
|
|
- name: Enabled
|
|
description: Interrupt generated when SLAKI bit is set
|
|
value: 1
|
|
enum/TIR_IDE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Standard
|
|
description: Standard identifier
|
|
value: 0
|
|
- name: Extended
|
|
description: Extended identifier
|
|
value: 1
|
|
enum/TIR_RTR:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Data
|
|
description: Data frame
|
|
value: 0
|
|
- name: Remote
|
|
description: Remote frame
|
|
value: 1
|
|
enum/TMEIE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: No interrupt when RQCPx bit is set
|
|
value: 0
|
|
- name: Enabled
|
|
description: Interrupt generated when RQCPx bit is set
|
|
value: 1
|
|
enum/WKUIE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: No interrupt when WKUI is set
|
|
value: 0
|
|
- name: Enabled
|
|
description: Interrupt generated when WKUI bit is set
|
|
value: 1
|